1.

Design Methods
The basic architecture of this processor is design by using
language HDL i.e Hardware Description language . The HDL language
like Verilog or HDL are used in Programming .Here we use VHDL code
i.e the input to the Design is given by writing The VHDL Code
For the data path and the control unit . The synthesis process
generate a circuit and simulation verifies the functionality of the circuit
based on the input given to it .Finally it is implemented on the FPGA kit
which is knows as Physical Design .
2. Hardware Description language
In Electronics , a hardware description language or HDL is any
language from the class of computer language for the formal description
of electronics circuit .It can describe the circuit .it can be describe as the
circuit operation ,its design and organisation and test to verify its
operation by mean of simulation
An HDL is a standard text based Expression of the temporal l
behevorial and or circuit structure of a electronics system . In contrast to
a software programing language ,an an HDL Syntax and semantics
include explicit natation for expression time and concurrency which are
primary attribute of hardware .
HDL’s are used to design two kinds of system .First they are
used to design a dedicated integrated circuit ,such as processor or a kind
of digital logic circuit .The second use involve programing programmable
logic device such as FPGA .The HDL code is fed to a logic complier and
the output is loaded into the device.
3. Types of HDL

Hardware Description Language is classified into two categories

which are as follows :

Verilog HDL

VHDL
 Here we are using the VHDL . so the following section discuss
the concept of VHDL Language.

4. About VHDL

VHDL or VHSIC Hardware Description language is commonly

used as a design entity language for the field programming gate array and the
application specific integrated circuit in the electronic design automation of
digital circuit .

VHDL was originally developed at the behest of the US

department Of Defence .The initial version of VHDL , designed to IEEE
Standard 1076-1987,include a wide range of data types. Included numerical
,logical ,character and time ,plus of bit called bit –vector and of character
called string . An Additional Standard ,the 1164 was later to introduce a
multi-valued logic system ,VHDL is intended for circuit synthesis as well as
circuit simulation .

A fundamental motivation to use VHDL is that VHDL is a standard

technology and is therefore portable and reusable .The two main application
of VHDL are in field of programmable logic device (including CPLDs and
FPGAs)and in the field of ASICs . Once the VHDL code has been written it
can be used either to implement the circuit in a programmable device (from
Altera ,Xilinx Atmel , etc )or can be submitted to foundry for the fabrication
of ASICs chip .The key Advantage of VHDL, when used for the system
design is that it allows the Behavioural of the allowed system to be describe
(modelled ) and verified (simulation ) before synthesis tool translate the
design into real hardware (gates and wires) .

VHDL is a Dataflow Language , unlike procedural computing

language like such as BASIC ,C , and assembly code ,which all run
sequentially ,one instruction at a time . When a VHDL model is translated
into the “gates and wires” that are mapped into a programmable logic device
such as CPLD or FPGA ,then it is the actual hardware being configured
,rather the VHDL code being “Executed ” as if on some processor chip .
 VHSIC HDL consist of two type of design unit namely : primary
design unit and secondary design unit and secondary design unit . Primary
design is the type of design unit which deals with the entity part of the
VHDL .

5. Terms associated with VHDL

Following are some terms associated with VHDL

ENTITY: It declare the external or user interface of the module similar to

the declaration of the function n .It specifies the name of the entity and its
interface .The interface consist of the signal to be passed into the entity or
out from it using the two keyword IN or OUT ,respectively .

ARCHITCTURE: It defines the actual implementation of the functionality

of the entity .This is similar to the definition or implementation of a function
..The Syntax for the Architecture varies , depending on the model .

GENERIC : Generic allows information to be passed an entity .Generic of

an entity are declared with the GENERIC Keyword before the PORT list
declaration for the entity .An identifier that is declared as declared as
GENERIC is a Constant that only can be read.

DRIVER: It is defined as the source on a signal .If the signal is having two
sources ,then the signal is said to have two drivers .

BUS: Bus is the groups of wires which connects two or more blocks in the
design . Bus is the groups of wires with its drivers turns off.

6. VHDL Model
The programmer can write the program in three different ways ..
1. Data Flow Model
2. Behavioral Model
3. Structural Model

A) DATA FLOW METHOD :-

In the data flow model , the logic of the design is implemented in with
the help of the simple equation . So it is always a simple and efficient
way to write the VHDL program so as to get the result by applying the
certain stimuli or input .
B) BEHAVIORAL MODEL :-

In the behevioral model there is certain process to write the logic of the
design .The behevioral model uses the process statement.

C) STRUCTURAL MODEL :-

In the structural model the logic of the design is implemented by

describing the input and the output ports and the logic of each component
associated with the design.

7. Synthesis

Synthesis is the translation of high level design into a specified

hardware . It translates a register transfer level model of hardware (written
in HDL) into a optimized technology specific gate level implementation
.That is to say ,the synthesis tool will take the designer’s code and remodel it
maintain it desire logic in order to optimized it . Because of this it was
important that the design to be presented well , free of latches and
unsupported VHDL constructs so that the optimization of the synthesis tool
did not affect the desired logic .It was imperative that the design was
synthesizable. Aside from declaration constructs , the only VHDL language
constructs used in the design are the process ,case ,if then else and
concurrent signal assignment .Only code that can be synthesis can be
converted by the complier into a valid net list of ports , which then can be
translated and mapped into a physical hardware .Not only would a
synthesizable design be downloadable to the target project board but would
that an efficient design is in plane.

8. Simulation

Simulation is defined as the exersing a model to behave just like an

actual model by applying certain stimuli or input .For the simulation of the
VHDL code it requires a simulator such as model- sim simulator or in build
ISE simulator and use xilinx software .
 A VHDL Simulator is used to verify the funcinality of the VHDL RTL
description .The VHDL RTL description of the propsed work is simulation
with standard VHDL simulator to verify that the description is correct .A
simulato needs two input : the description of the language and the stimulus
to drive the design .Sometime , the design are self –simulation and don’t
need any external stimulus ,but in most cases , the VHDL designer use a
VHDL test bench of one kind or another to driver being tested .

FPGA

FPGA – As the name suggest ,field programmable Gate Arrays the

standard logic elements are available for the designer and he has only to
interconnect with these this element to achive the desired functional
performance .It combine the versatility of gate array with the
programmable of PLDs .It is usually larger and more complex than a
PLD .Interconnects can be programmed ,through which we can
implement combinational as well as sequential logic .The FPGA core is a
regular array of basic programmable logic cell . It is surrounded by the
programmable interconnects .Further programmable input output cell
surrounds the core .The design turn around time is few hours .In this
design the desiner is only based on designing the interconnects and
communication .The user enter her /his schematic ,simulation the design
and then with the help of software turns the connection into the string s of
bits . The programmable equipment makes necessary connection in
accordance with the configuration file and the FPGA is ready to use .
The basic constituents of a FPGA are
 Configurable Logic Blocks (CLBs)
 Configurable I/O Blocks (IOBs)
Two layers of blocks metals network of vertical and horizontal lines
interconnecting the CLBs and IOBs .
We can categories FPGA according to their combination of programming
technology and device architecture as:
CPLDs- complex programming logic Devices
SRAM –FPGA
Anti fuse FPGAs
COMPLEX PROGRAMMING LOGIC DEVICE :(CPLDs)
A complex Programming logic devices (CPLD) is a programming logic
device with complicity between that of PALs and FPGAs , and architecture
feature of both. The building block is the Macro cell ,which contain logic
implementation disjunctive normal form expression and more specialized
operation.

 Feature in common with PALs.

Non-volatile configuration memory unlike many FPGA , an external

configuration ROM isn’t required ,and the CPLD can functional immediately
on system start-up .

CPLDs typically have the equivalent to thousand to ten thousand of logic gates
,allowing implementation of moderately complicated data processing device.

 Uses of CPLDs

CPLDs are often used in modern digital to perform ‘boot loader’ function
before loading over control to other device not having this capability

It is used to load configuration data for an FPGA from non-volatile memory.