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CDC and LINT

CDC stands for "Clock Domain Crossing" and refers to transferring data between different clock domains within a system-on-chip. Lint is a verification tool that checks RTL code for inconsistent coding styles that could lead to synthesis vs simulation mismatches. A CDC issue occurs when data is transferred from one flip flop to another in asynchronous clock domains, which can cause metastability, data incoherence, and data loss issues. Lint is run after writing RTL code to check for logic errors like hanging wires or floating signals.

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3K views2 pages

CDC and LINT

CDC stands for "Clock Domain Crossing" and refers to transferring data between different clock domains within a system-on-chip. Lint is a verification tool that checks RTL code for inconsistent coding styles that could lead to synthesis vs simulation mismatches. A CDC issue occurs when data is transferred from one flip flop to another in asynchronous clock domains, which can cause metastability, data incoherence, and data loss issues. Lint is run after writing RTL code to check for logic errors like hanging wires or floating signals.

Uploaded by

Srinivas Cheruku
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CDC and LINT

CDC stands for “Clock Domain Crossing”. Different sub-systems within a SoC usually run on
different clocks and have may different reset signals. For e.g. peripheral sub-system such as
SPI may run on a slow 50 MHz clock while a high-performance CPU cluster will most likely
run on a clock in the GHz range. For data to be transferred between these 2 different clock
domains, clock (and reset) synchronization logic are required to be put in place at clock
crossing boundaries. The CDC flow is a verification tool flow which reads the RTL source
files, checks for missing or inadequate synchronization logic and reports them back to the
engineer.

Lint, on the other hand, is a verification tool flow which checks the RTL source code for
inconsistent coding style that would potentially lead to Synthesis vs Simulation mismatches.
For example, the verilog code below would synthesize to a latch due to the missing ‘else’
clause although the intention was to infer pure combinational logic:

1. always@(*)
2. if (something)
3. nothing = 0;
4. else if (something_else)
5. nothing = 1;
Atrenta Spyglass (now part of Synopsys) is a widely used Lint & CDC tool in the industry.

A Clock domain Crossing(CDC) is one where the data is transferred from one flip flop
to another where the two clock domain are asynchronous to each other.

A CDC often raised to many issues in digital circuits. Some of the common issues is:-

 Metastability
 Data incoherence
 Data loss
The asynchronous issues in Digital circuits can be controlled using Synchronizers,most
probably using a 2 FF or a 3 FF Synchronizers considering MTBF.

Other methods of controlling CDC are FIFO,Sample and Hold Circuits,Handshaking


Protocol,Gray Pointer,Mux Recirculation Techniques.

Lint is generally run after writing the RTL codes to check for
any hangingwires,floating signals within the synthesized RTL codes.
RTL Design - Senior Engineer (3 of 12)
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4.0 ★ Thinci– Hyderabad

Required Skills:

 Experience of multi-million gate ASIC design and verification methodologies.

 Knowledge of Computer architecture.

 Knowledge of digital design methodologies and tool flow.

 Excellent logic design, debugging and problem-solving skills.

 Experience in logic design with Verilog and/or System Verilog and validation/verification.

 Experience in synthesis and timing analysis.

 Multi-clock domain.

 Interconnects.

 Algorithm to Architecture.

 Low power design.

 Memory subsystem.

Desired Skill set:

 Experience with DSP, Datapath design and floating-point math a plus.

 Knowledge of SIMD, MIMD, VLIW and parallel processing a plus.

Required Experience:

 2-8 years of RTL design with multiple tape-outs.

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