Digital Electronics Lab SE Computer

Pad Dr. D. Y. Patil Institute of Engineering Management &

Research, Akurdi

DEPARTMENT OF COMPUTER ENGINEERING

LAB MANUAL

FOR
S.E. COMPUTER (SEM – I)

DIGITAL ELECTRONICS LABORATORY

Academic Year 2017-18

TEACHING SCHEME EXAMINATION SCHEME

PRACTICAL: 2 HRS/WEEK TERM WORK: 25 MARKS

Prepared By: Ms. Mohini Avatade

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PREFACE

INFORMATION ABOUT LAB: Digital Electronics Laboratory

SOFTWARE REQUIRED : Xillinx, ModelSim

HARDWARE REQUIRED : Digital trainer Kit, Connecting Wires, IC’s

OPERATING SYSTEM : Windows-2000, XP

OBJECTIVES OF LAB

 To learn and understand basic digital design techniques.

 To learn and understand design and construction of combinational and
sequential circuits.
 To introduce to Digital logic design Software

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ASSIGNMENT NO: A1

PROBLEM STATEMENT:
T.T.L Characteristics (Study and Write up only).

PLATFORM: Windows XP

PREREQUISIT :

THEORY:

Logic gates are classified not only by their logical functions, but also by their logical
families. In any implementation of a digital system, an understanding of a logic
element's physical capabilities and limitations, determined by its logic family, are
critical to proper operation. The
Purpose of this experiment is to provide an understanding of some of the characteristics
of the
Transistor transistor logic (TTL) family and Complementary Metal Oxide
Semiconductor logic (CMOS) family.

TTL FAMILY
The logic family refers to the general physical realization of a logical element, such as
the TTL, emitter- coupled logic (ECL), or complementary metal - oxide semiconductor
(CMOS) logic families. Within each logic family are one or more logic series that have
distinctive characteristics, relative to other series within the same logic family. For
example, in the TTL logic family, there are several logic series: the 74 standard, 74L
low - power, 74H high – speed , 74S standard Schottky, 74LS low - power Schottky
series, and 74ALS advanced low - power Schottky series.
The TTL family was the most widely used logic family for several years, characterized
by its relatively high speed operation. However, it has now been largely replaced by
CMOS logic. The physical representation of the binary logic states in these families are
high and low voltages, as described in Experiment 1. Assuming positive logic, in the
74LS TTL family LOW (L) voltages in the range 0 V to 0.8 V are considered to be
logic 0, and HIGH (H) voltages in the range 2.0 V to 5.5 V are considered to be logic 1.
Figure A1.1 illustrates the voltage levels for all possible input combinations to a two -
input TTL NAND gate- input TTL NAND Gate

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Fig A1.1 Voltage Level Table

You may wonder why the NAND gate is so popular in the TTL logic families. Perhaps
the most important factor in the use of such gates is the presence of transistors.
Transistors are active devices that tend to restore signal levels and preclude signal
deterioration which could cause 1 and 0 become indistinguishable. No degradation of
signal levels occurs, even for long chains of TTL NAND gates. In the TTL family the
number of transistors required to implement a NAND
gate is less than that required to implement other gates such as AND, OR and NOR.
Another factor in favor of NAND gates is the fact that any combinational logic function
can be realized using just NAND gates.

TTL CHARACTERISTICS
Each logic family is characterized by several important parameters. These properties,
and how they relate to the TTL logic family in particular, are explained below:
Fan- in is the maximum number of inputs to a gate. Although physical considerations
limit fan - in, more pragmatic factors, such as limitations on the number of pins
possible on IC packages and their standardization predominate. TTL NAND gates
typically provide 1, 2, 4, or 8 inputs. If more than eight in puts are required, then a
network of NAND gates must be employed.
Fan - out specifies the number of standard loads that the output of a gate can drive
without impairing its normal operation. A standard load is defined to be the amount of
current required t o drive an input of another gate in the same logic family. Due to the
nature of TTL gates, two different fanout values are given, one for HIGH outputs and
one for LOW outputs. Typically when an input is at logic 1 at most 40μA flows into an
input (IIH(max) and it must be provided (sourced) by the driving output. For logic 0, at
most 1.6 mA flows from the input (IILmax), which the driving output must "sink". By
convention the current flowing into an input or output is considered positive while a
current flowing out of an input or output is considered negative; hence, IILmax = -
1.6mA. A typical TTL gate can source 400 μA (I0H(max)) of current and can sink 16
mA (I0L(max)). Hence TTL gates typically have a HIGH (logic level) fanout
of|I0H(max)/IIH(max)| = |-400 μA / 40 μA| = 10,and a LOW fanout
of|I0L(max)/IIL(max)| = |16mA / -1.6 mA| = 10.Exceeding these fan-out limits may
result in incorrect voltage levels at the output, as a gate cannot provide or sink enough

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current. The lower value of the two fanout values determines the fanout of the gate. In
the case of 7400 TTL logic, they are equal, but for some other types of TTL logic the
limiting value is the LOW fanout. Some TTL structures have fan - outs of at least 20
for both logic levels.
A voltage transfer curve is a graph of the input voltage to a gate versus its output
voltage;
Figure A1.2 shows the transfer curve for TTL inverter without any fanout. When the
input voltage is 0 V, the output is HIGH at 3.3 V. As the input voltage is increased from
0 to 0.7 V, the output remains relatively constant (Region I). Beyond 0.7 V to about 1.2
V, the output decreases more gradually with increasing input voltage (Region II). The
threshold voltage, the voltage on the transfer curve at which Vout= Vin and occurs in
Region III, is found at the intersection of the transfer curve and the line Vout = Vin.
Finally, in Region IV, the output remains constant at 0.2 V as the input voltage is
increased.
Noise immunity is a measure of the ability of a digital circuit to avert logic level
changes on signal lines when noise causes voltage level changes. (See Figure A1.3.)
One measure of noise
immunity is characterized by a pair of parameters: the dc HIGH and LOW noise
margins,DC1 and DC0, respectively. They are defined as follows:DC1 = VOH(min) -
VIH(min) and DC0 = VIL(max) -VOL(max).The minimum values of DC1 and DC0
determine worst case noise margin.

Fig A1.2 Voltage Transfer Curve for a TTL Gate.

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Fig A1.3 Input and Output TTL Voltage Levels Illustrating DC Noise Margin

Recall from Experiment 1 that VOL(max) is the largest voltage that can occur on the
output of a gate when the output is in the LOW (logic 0) voltage range. VOH(min) is
the smallest voltage that can occur on a gate output when the output is in the HIGH
(logic 1) voltage range output. In addition, VIH(min)is the smallest input voltage that
will be interpreted as a HIGH input and VIL(max) is the greatest input voltage that will
be interpreted as a LOW input. Note that VOL and VOH are specified by the
manufacturer on the data sheets for the device. VIL and VIH can be determined, given
VOL and VOH, from the voltage transfer curve, as indicated in Figure A1. 2. Illustrated
in Figure A1.3 are the DC0 and DC1 noise margins. For the TTL family, typically
DC0 = 0.8 -0.4 = 0.4 V, and DC1 = 2.4 -2.0 = 0.4 V. (The values for VOL, VOH, VIL,
and VIH were obtained from the specification sheet of the 7400 NAND gate.) Any
disturbance with a
negative peak of up to DC1 could appear superimposed on the worst case HIGH
voltage level, VOH ,on an input without disturbing the gate output. A similar statement
can be made for DC0.
The propagation delay time for a gate is the time required for the output to respond to a
change in an input. In all practical gates, a time lag exists between an input change and
the corresponding output response. The time interval between the instants when the
input and output change states is not a satisfactory measure of the delay time of a
logical device for two reasons.
First, the input signals to gates and the output signals produced by gates are not the
idealized pulses studied in theory.
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Figure A1.4 illustrates the nonideal input and output signals to a NAND gate. The
transitions between HIGH and LOW voltage levels have nonzero rise and fall times.
The time required for a signal to rise from 10% to 90% of its final value is called the
rise time, tr The fall time, tf, is the time required for the signal to fall from 90% to 10%
of its initial value. Secondly, the input voltage to a gate has only to reach the threshold
voltage level before the device begins to change state. For these reasons, the delay time
is measured with respect to a reference voltage level
Vref, or the threshold voltage. Consider the NAND gate in Figure 3.4, connected as a
NOT gate. The input waveform, Vin, is a non-ideal pulse. When the input signal goes
HIGH, the output will go LOW after the turn-on delay time tPHL. The figure illustrates
the turn-on delay for a non-ideal output pulse. The typical turn-on delay for a standard
series TTL NAND gate is 7 ns. When the input signal goes LOW again, the output of
the NAND gate goes HIGH after the turn – off delay time tPLH. The typical turn-off
delay time for a standard series TTL NAND gate is 11 ns. The average propagation
delay time tp is then defined by: tp= (tPHL+ tPLH) / 2. The maximum value for both
tPHL and tPLH is 15 ns

Fig A1.4 Propagation Delay Times

A phenomenon associated with TTL devices is current spiking. When the output of a
TTL device is HIGH, a constant supply current ICCH is drawn from the power supply
by the IC. When the output is LOW, a constant supply current ICCL is drawn from the
power supply. For a 7400 NAND gate, ICCH= 4 mA and ICCL= 12 mA per IC.
Another important characteristic of digital IC's is their power dissipation. As the power
dissipation in a system increases, more heat must be dissipated from the system and
larger, more costly power supplies are required. The static power dissipation PDP of an
IC is the product of the supply voltage VCC and the static power supply current ICC.
If, on the average, the output of a device is HIGH half the time and LOW the other half,
then the average power supply current is ICC= (ICCH+ ICCL)/2.
An unconnected input to a gate is called a floating input, because it floats at the
threshold voltage for the device. A floating TTL input usually acts as a HIGH input.

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However, open inputs are susceptible to noise which can be received by an input via the
package leads, which act as antennae for noise. Even a few hundred millivolts of
negative noise voltage is sufficient to drive a floating input to the LOW state.
Therefore, it is advisable to tie all unused inputs of any gate (when the gate has more
inputs than required) to HIGH or LOW voltage. In addition, the outputs of unused gates
in an IC package should be forced HIGH by appropriate connection of the inputs. This
provides a convenient HIGH, reduces the power dissipation (ICCH< ICCL),

CONCLUSION:…………………………………………………………………………
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ASSIGNMENT NO: A2

PROBLEM STATEMENT:
Code converters e.g. Excess-3 to BCD and vice versa

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires, IC 7486 etc

THEORY:

Gray To Binary Code Converter:

Code is a symbolic representation of discrete information. Codes are of different types.
Gray Code is one of the most important codes. It is a non-weighted code which
belongs to a class of codes called minimum change codes. In this codes while
traversing from one step to another step only one bit in the code group changes. In case
of Gray Code two adjacent code numbers differs from each other by only one bit. The
idea of it can be cleared from the table given below.
As this code it is not applicable in any types of arithmetical operations but it has some
applications in analog to digital converters and in some input/output devices. Now let
us concentrate on the table of Gray Code given below where we can find the difference
of binary code from gray code while traversing through the table for their respective
decimal numbers.

Gray code to binary conversion is again very simple and easy process. Following
steps can make your idea clear on this type of conversions.
(1) The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
(2) Now if the second gray bit is 0 the second binary bit will be same as the previous or
the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and
if it was 0 it will be 1.
(3) This step is continued for all the bits to do Gray code to binary conversion.
One example given below will make your idea clear.
Let the gray code be 01101

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Fig A2.1 Gray to Binary Code Conversion

Fig A2.2 Circuit Diagram of Gray to Binary Code Conversion

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Fig A2.3 Binary to Gray Code Conversion

Binary to gray code conversion: is a very simple process. There are several steps to
do this types of conversions. Steps given below elaborate on the idea on this type of
conversion.
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given binary
number.
(2) Now the second bit of the code will be exclusive-or of the first and second bit of the
given binary number, i.e if both the bits are same the result will be 0 and if they are
different the result will be 1.
(3)The third bit of gray code will be equal to the exclusive-or of the second and third bit
of the given binary number. Thus the Binary to gray code conversion goes on. One
example given below can make your idea clear on this type of conversion.
Let (01001) be the given binary number

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Fig A2.4 Binary to Gray code conversion

Fig A2.5 Circuit Diagram of Bin to Gray Conversion

Thus the equivalent gray code is 01101.

Now concentrate on the example where the M.S.B. of the binary is 0 so for it will be 0
for the most significant gray bit. Next, the XOR of the first and the second bit is done.
The bits are different so the resultant gray bit will be 1. Again move to the next step,
XOR of second and third bit is again 1 as they are different. Next, XOR of third and
fourth bit is 0 as both the bits are same. Lastly the XOR of fourth and fifth bit is 1 as
they are different. That is how the result of binary to gray code conversion of 01001 is
done whose equivalent gray code is 01101.
Procedure: -

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.

3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3
are given at respective pins and outputs G0, G1, G2, G3 are taken for all
the 16 combinations of the input.

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4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3
are given at respective pins and outputs B0, B1, B2, and B3 are taken for
all the 16 combinations of inputs.

5. The values of the outputs are tabulated.

THE BCD TO EXCESS 3 CODE CONVERTER:

• It is a non weighted code.

• In XS-3, numbers are represented as decimal digits, and each digit is

represented by four bits as the digit value plus 3 (the "excess" amount).

• The primary advantage of XS-3 coding over non-biased coding is that a decimal
number can be nines' complemented as easily as a binary number can be ones'
complemented . In addition, when the sum of two XS-3 digits is greater than 9,
the carry bit of a four bit adder will be set high.

The Excess-3 BCD system is formed by adding 0011 to each BCD value as in Table 2.
For example, the decimal number 7, which is coded as 0111 in BCD, is coded as
0111+0011=1010 in Excess-3 BCD.

• BCD Excess-3 circuit will convert numbers from their binary representation to
their excess-3 representation. Hence our truth table is as below:

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

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1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

Solution: E3=B3+B2(B1+B0)

E2=B2^(B1+B0)

E1=(B1^B0)’

E0=B0’

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Fig A2.6 Circuit Diagram of BCD to Excess-3

Applications:

• Excess-3 was used on some older computers

• Cash registers

• Hand held portable electronic calculators

CONCLUSION:…………………………………………………………………………
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ASSIGNMENT NO: A3

PROBLEM STATEMENT:
Multiplexers: Application like Realization of Boolean expression using Multiplexer.

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

Multiplexers are very useful components in digital systems. They transfer a large number
of information units over a smaller number of channels, (usually one channel) under the
control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with
many inputs but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the output bit
depends on the input data bit that is selected. The general multiplexer circuit has 2 n input
signals, n control/select signals and 1 output signal.
i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

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REALIZATION USING NAND GATES TRUTH TABLE

Select Enable Out

Inputs
Inputs Input puts

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

HALF ADDER USING MUX:

DESIGN: TRUTH TABLE

SUM CARRY
I0 I1 I0 I1 Inputs Outputs
0 1 0 1 A B S C
2 3 2 3 0 0 0 0
A A’ 0 A
0 1 1 0
CIRCUIT: 1 0 1 0
1 1 0 1

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FULL ADDER CIRCUIT

TRUTH TABLE
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

HALF SUBTRACTOR USING MUX:

DESIGN:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

CIRCUIT: TRUTH TABLE

Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Questions:

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1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?
7) In 2n to 1 multiplexer how many selection lines are there?
8) How to get higher order multiplexers?
9) Implement an 8:1 mux using 4:1 muxes?

CONCLUSION:…………………………………………………………………………………
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ASSIGNMENT NO: A4

PROBLEM STATEMENT:
Demultiplexers: Applications like Realization of ROM using Demultiplexer

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of selection
signals. The general de-multiplexer circuit has 1 input signal, n control/select signals and 2 n output
signals. De-multiplexer circuit can also be realized using a decoder circuit with enable.
ii) DE-MUX USING NAND GATES
Enable Data Select
Outputs
Inputs Input Inputs

E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

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A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).

CIRCUIT DIAGRAM:

2:4 DECODER (MIN TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

BOOLAEN EXPRESSIONS:
Y 0  AB
Y1  AB
Y 2  AB
Y 3  AB

CIRCUIT DIAGRAM:

2:4 DECODER (MAX TERM GENERATOR):

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TRUTH TABLE:
CIRCUIT DIAGRAM:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

Questions:

1. What are the applications of decoder?

2. What is the difference between decoder & encoder?
3. For n- 2n decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. Using 3:8 decoder and associated logic, implement a full adder?
7. Implement a full subtractor using IC 74138?
8. What is the difference between decoder and de-mux?

CONCLUSION:…………………………………………………………………………
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ASSIGNMENT NO: A5

PROBLEM STATEMENT:
BCD adder/Subtractor using 4 bit binary adder 7483.

PLATFORM: Windows XP

PREREQUISIT : IC 7483, IC 7486, Digital trainer Kit, Connecting Wires etc.

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are
connected in chain through the full adder. The input carry to the adder is C 0 and it
ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry
C0 must be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output
sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two
decimal digits must be represented in BCD and should appear in the form listed in the
columns.

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ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the
binary sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:

4-BIT BINARY ADDER

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LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR

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TRUTH TABLE:

LOGIC DIAGRAM:

BCD ADDER

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K MAP

Y = S4 (S3 + S2)

TRUTH TABLE:

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PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

CONCLUSION:…………………………………………………………………………
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ASSIGNMENT NO: A6

PROBLEM STATEMENT:
Design & Implement Parity generator using EX-OR

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the
number of 1’s either odd or even. The message including the parity bit is transmitted
and then checked at the receiving end for errors. An error is detected if the checked
parity does not correspond with the one transmitted. The circuit that generates the parity
bit in the transmitter is called a parity generator and the circuit that checks the parity in
the receiver is called a parity checker. In even parity the added parity bit will make the
total number of 1’s an even amount and in odd parity the added parity bit will make the
total number of 1’s an odd amount. In a three bit odd parity generator the three bits in
the message together with the parity bit are transmitted to their destination, where they
are applied to the parity checker circuit. The parity checker circuit checks for possible
errors in the transmission. Since the information was transmitted with odd parity the
four bits received must have an odd number of 1’s. An error occurs during the
transmission if the four bits received have an even number of 1’s, indicating that one bit
has changed during transmission. The output of the parity checker is denoted by PEC
(parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits
received has an even number of 1’s.

From the truth table the expression for the output parity bit is, P (A, B, C) = Σ m (0, 3,
5, 6) Also written as,

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CIRCUIT DIAGRAM:

ODD PARITY GENERATOR ODD PARITY CHECKER

ODD PARITY GENERATOR

From the truth table the expression for the output parity checker bit is, X (A, B, C, P) =
Σ (0, 3, 5, 6, 9, 10, 12, 15) The above expression is reduced as,

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CIRCUIT DIAGRAM: ODD PARITY CHECKER

PROCEDURE: 1. Connections are given as per the circuit diagrams.

2. for all the ICs 7th pin is grounded and 14th pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the Parity generator and checker.

Questions:

1. Design 2-bit odd parity generator and checker

2. Need of parity generator and checker

3. Difference between odd parity and even parity

CONCLUSION:…………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………

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ASSIGNMENT NO: B1

PROBLEM STATEMENT:
Flip flops, Registers and Counters (Study and Write up only).

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

Logic circuits that incorporate memory cells are called sequential logic circuits; their
output depends not only upon the present value of the input but also upon the previous
values. Sequential logic circuits often require a timing generator (a clock) for their
operation.
The latch (flip-flop) is a basic bi-stable memory element widely used in sequential
logic circuits. Usually there are two outputs, Q and its complementary value.
Some of the most widely used latches are listed below.

SR LATCH:
An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be
design using cross-coupled NAND gates as shown. The truth tables of the circuits are
shown below.
A clocked S-R flip-flop has an additional clock input so that the S and R inputs
are active only when the clock is high. When the clock goes low, the state of flip-flop is
latched and cannot change until the clock goes high again. Therefore, the clocked S-R
flip-flop is also called “enabled” S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding
an inverter. When the clock is high, the output follows the D input, and when the clock
Goes low, the state is latched. A S-R flip-flop can be converted to T-flip flop by
connecting S input to Qb and R to Q.

1) S-R LATCH:

(A) LOGIC DIAGRAM (B) SYMBOL

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TRUTH TABLE
S R Q+ Q b+
Q
0 0 Q b
0 1 0 1
1 0 1 0
1 1 0* 0*

S R LATCH: TRUTH TABLE

S R Q+ Q b+
0 0 1* 1*
0 1 1 0
1 0 0 1
1 1 Q Qb

2) SR FLIP FLOP:
CIRCUIT DIAGRAM:

(A) LOGIC DIAGRAM (B) SYMBOL

TRUTH TABLE
S R Q+ Q b+
Q
0 0 Q b
0 1 0 1
1 0 1 0
1 1 0* 0*

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3) CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)

LOGIC DIAGRAM SYMBOL

T FLIP FLOP USING IC 7476 TRUTH TABLE

T Qn + 1

0 Qn

1 Qn

4) CONVERSION OF SR-FLIP FLOP TO D-FLIP FLOP :

LOGIC DIAGRAM SYMBOL

D FLIP FLOP USING IC 7476 TRUTH TABLE

CLOCK D Q+ Q+
0 X Q Q
1 0 0 1
1 1 1 0

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5. CONVERSION OF SR-FLIP FLOP TO JK-FLIP FLOP

LOGIC DIAGRAM TRUTH TABLE

Clock J K Q+ Q’+ Comment

No
1 0 0 Q Q’
Change
1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 Q’ Q Toggle

LOGIC DIAGRAM TRUTH TABLE

SD RD Clock J K Q Q’ Comment

0 0 Not Allowed

0 1 X X X 1 0 Set

1 0 X X X 0 1 Reset

1 1 1 0 0 NC NC Memory

1 1 1 0 1 0 1 Reset

1 1 1 1 0 1 0 Set

1 1 1 1 1 Q’ Q Toggle

6. JK MASTER SLAVE FLIP FLOP

LOGIC DIAGRAM

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TRUTH TABLE

PRE = CLR = 1

Clock J K Q+ Q’+ Comment

No
1 0 0 Q Q’
Change

1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 Race Around

VIVA QUESTIONS:
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?
7. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
8. List the functions of asynchronous inputs?

SHIFT REGISTERS:

1) SERIAL IN SERIAL OUT (SISO) (Right Shift)

Serial
Shift
i/p Pulses QA QB QC QD
data
- - X X X X
0 t1 0 X X X
1 t2 1 0 X X
0 t3 0 1 0 X
1 t4 1 0 1 0
X t5 X 1 0 1
X t6 X X 1 0
X t7 X X X 1
X t8 X X X X

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2) SERIAL IN PARALLEL OUT (SIPO)

Serial Shift
QA QB QC QD
i/p data Pulses
- - X X X X
0 t1 0 X X X
1 t2 1 0 X X
0 t3 0 1 0 X
1 t4 1 0 1 0

3) PARALLEL IN PARALLEL OUT (PIPO)

Clock
Shift
Input Pulses QA QB QC QD
Terminal
- - X X X X
CLK2 t1 1 0 1 0
4) PARALLEL IN SERIAL OUT (PISO)

Clock
Shift
Input Pulses QA QB QC QD
Terminal
- - X X X X
CLK2 t1 1 0 1 0
CLK2 t2 X 1 0 1
0 t3 X X 1 0
1 t4 X X X 1
X t5 X X X X

VCC QA QB QC QD CLK1 CLK2

14 13 12 11 10 9 8

IC 7495

1 2 3 4 5 6 7

SERIAL A B C D MODE GND

INPUT
(Right
CONTROL
PARALLEL
Shift) INPUTS

RESULT: The various operations of a shift register is verified

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ASSIGNMENT NO: B2

PROBLEM STATEMENT:
4-bit Multiplier / Divider (Study and Write up only).

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

Multiplication is a very common operation in digital systems. For that reason, custom
designed multipliers are often used. The goal of this lab is to make you familiar with
the design and implementation of such a multiplier. Multiplication of a 3-bit number
B(2:0) by a 4-bit number A(3:0) can be illustrated as follows.

The implementation below follows a one-to-one topological correspondence with the

manual multiplication shown above. This gives rise to a very regular structure that is
easily implemented. Figure 2 shows an implementation for a 4-bit x 3-bit multiplier
using two 4-bit adders. Another important part of this lab is binary-to-BCD conversion.
We want to display the final output on 7-segment displays, but since the output of the
multiplier is in binary, we have to convert it before we can display it. Although it is
possible to build a decoder using the same method as in previous labs (i.e. enumerating
all the possible outputs using the with-select command), the code would be enormous
considering the number of possible combinations.

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We would rather have a more efficient method. Once such implementation is called the
"shift-add-3" algorithm. Here is the concept:

Suppose we have a four-bit binary number that we want to convert to BCD. If it is less
than 10, we don't need to change anything. If it is larger than 10, however, we need to
do a conversion. We can subtract 10 from the original number to get the ones digit.
Then, putting a 1 in the tens digit in BCD can be thought of as adding 0001
00002=1610 to the original number. For example, Start with 12=11002 0000 11002
Subtract 10=10102 0000 0010 Add 16=100002 0001 0010BCD

If we combine these operations into one, we see that to convert a four-digit number
from binary to BCD, just add 6 or 01102 if the number is greater than or equal to 10.
This works well for four digit numbers, but what if we have more than that? In this

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case, we can shift the input, one bit at a time, through sets of four bits, and at each step
add 01102 to a digit if the number is 10 or greater. Here is 22=101102 as an example:
Table I: Illustration of converting a 5-bit binary number into a BCD number

After each shift, one needs to check if the number in the “Ones” column is equal or
greater than 1010. If it is, one add 6 to it before shifting again. Notice that when we
added 01102, the carry bit was carried into the next digit. This means we would need
five output bits at each step rather than four. However, there is a shortcut we can use to
avoid this. What does shifting a binary number one spot to the left do to the number
mathematically? It has the effect of doubling a number (try it out!). If we switch the
order of the operations, we only need four bits of output. Specifically, we can add 3 and
double instead of doubling and adding 6, because both give the same result in the end.
This is where the algorithm gets its name. The new rule then is to shift the input, one bit
at a time, through sets of four bits, and if a digit is five or greater, then we add 3 before
shifting again. Here is the same example again, using the "shift-add-3" algorithm: Table
II: Conversion of a 5-bit number into a BCD number using the shift-add-3 algorithm

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CONCLUSION:…………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………

ASSIGNMENT NO: B3
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PROBLEM STATEMENT:
Ripple counter using flip-flops.

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

When output of flip-flop as a clock output for next flip-flop, we call the counter as an
Asynchronous Counter or Ripple counter. An asynchronous (ripple) counter is a
single JK-type flip-flop, with its J (data) input fed from its own inverted output. This
circuit can store one bit, and hence can count from zero to one before it overflows
(starts over from 0). This counter will increment once for every clock cycle and takes
two clock cycles to overflow, so every cycle it will alternate between a transition from
0 to 1 and a transition from 1 to 0.
A counter in which each flip-flop is triggered by the output goes to previous flip-flop.
As all the flip-flops do not change state simultaneously spike occur at the output. To
avoid this, strobe pulse is required. Because of the propagation delay the operating
speed of asynchronous counter is low. Asynchronous counter are easy and simple to
construct.

3 BIT ASYNCHRONOUS UP COUNTER

CIRCUIT DIAGRAM:

TRUTH TABLE

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CLK QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

3 BIT ASYNCHRONOUS DOWN COUNTER

CIRCUIT DIAGRAM:

TRUTH TABLE

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CLK QC QB QA
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

Questions:

What is an asynchronous counter?

How is it different from a synchronous counter?
Realize asynchronous counter using T flip-flop

CONCLUSION:………………………………………………………………
………………………………………………………………………………
………………………………………………………………………………
………………………………………………………………………………

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ASSIGNMENT NO: B4

PROBLEM STATEMENT:
Sequence generator using JK flip-flop.

PLATFORM: Windows XP

PREREQUISIT : IC 7495, IC 7486, Digital trainer Kit, Connecting Wires etc.

THEORY:

PROCEDURE:
  Check all the components for their working.
  Insert the appropriate IC into the IC base.
  Make connections as shown in the circuit diagram.
 By Keeping mode=1. Load the input A,B,C,D as in Truth Table 1st Row and give a
 clock pulse
  For count mode make mode = 0.
 Verify the Truth Table and observe the outputs

DESIGN 1:
Sequence = 100010011010111
Sequence length S = 15 Y = QC (+) QD
QA QB QC QD Y
1 1 1 1 0
0 1 1 1 0
0 0 1 1 0
0 0 0 1 1
1 0 0 0 0
0 1 0 0 0
0 0 1 0 1
1 0 0 1 1
1 1 0 0 0
0 1 1 0 1
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1
1 1
1

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DESIGN 2:
Sequence = 1001011
Sequence length S = 7 Y = QB (+) QC

QB QC QA QB QC QD Y
1 1 1 1 0

X X 1 X
3 2

1
Y

CLK 0 1 1 1 0
0 0 1 1 1
VCC QA QD

0 X 0 X
1 0 0 1 0
14 13 12 11 10 9 8
0 1 0 0 1
1 0 1 0 1
X 1 X 0
IC 7495
1 1 0 1 1
1 1 0 X 1 X 1
1 2 3 4 5 6 7 1 1
1
Serial A B C D Mode Gnd
Input INPUTS Control

DESIGN 3:
Sequence = 1101011
Sequence length S = 7

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Y = QA + QC + QD

X X X X

X 1 1 X

X 1 0 1

X X 0 1

QA QB QC QD Y
1 1 1 1 1
1 1 1 1 0
0 1 1 1 1
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 0
1 1
1

Questions:

1) What is the necessity for sequence generation?

2) What are PISO, SIPO, and SISO with respect to shift register?
3) Differentiate between serial data & parallel data
4) What is the significance of Mode control bit?
5) What is a ring counter?
6) What is a Johnson counter?
7) How many Flip-flops are present in IC 7495?

CONCLUSION:…………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………
……………………………………………………………………………………………

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ASSIGNMENT NO: B6

PROBLEM STATEMENT:
Up-down counter using JK flip-flop.

PLATFORM: Windows XP

PREREQUISIT : IC 7476, Digital trainer Kit, Connecting Wires etc.

THEORY:

A counter in which each flip-flop is triggered by the output goes to previous

flip-flop. As all the flip-flops do not change states simultaneously in asynchronous
counter, spike occur at the output. To avoid this, strobe pulse is required. Because of
the propagation delay the operating speed of asynchronous counter is low. This
problem can be solved by triggering all the flip-flops in synchronous with the clock
signal and such counters are called synchronous counters.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs

MOD 5 COUNTER:
TRUTH TABLE: Present count next count
QC QB QA QC QB QA QC QB QA
0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0
0 1 0 0 1 0 0 1 1
0 1 1 0 1 1 1 0 0
1 0 0 1 0 0 0 0 0
0 0 0
JK FF excitation table:

Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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DESIGN:
1 X X 1 X 1 X X
0 X X X X X X X

JA = QC KA = 1

0 1 X X X X 1 0
0 X X X X X X X

JB = QA KB = QA

0 0 1 0 X X X X
X X X X 1 X X X

J C = Q BQ A KC = 1

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ASSIGNMENT NO: B7

PROBLEM STATEMENT:
Modulo N counter using 7490 & 74190 (N>10).

PLATFORM: Windows XP

PREREQUISIT : IC 7490, Digital trainer Kit, Connecting Wires etc.

THEORY:

DECADE COUNTER:

A BCD counter is a special type of a digital counter which can count to ten on the
application of a clock signal. We saw previously that toggle T-type flip flops can be
used as individual divide-by-two counters. If we connect together several toggle flip-
flops in a series chain we can produce a digital counter which stores or display the
number of times a particular count sequence has occurred.

Clocked T-type flip-flops act as a binary divide-by-two counter and in asynchronous

counters, the output of one counting stage provides the clock pulse for the next stage.
Then a flip-flop counter has two possible output states and by adding more flip-flop
stages, we can make a divide-by-2N counter. But the problem with 4-bit binary counters
is that they count from 0000 to 1111. That is from 0 to 15 in decimal.

To make a digital counter which counts from 1 to 10, we need to have the counter count
only the binary numbers 0000 to 1001. That is from 0 to 9 in decimal and fortunately
for us, counting circuits are readily available as integrated circuits with one such circuit
being the Asynchronous 74LS90 Decade Counter. The total number of counts that a
counter can count too is called its MODULUS. A counter that returns to zero after n
counts is called a modulo-n counter, for example a modulo-8 (MOD-8), or modulo-16
(MOD-16) counter, etc, and for an “n-bit counter”, the full range of the count is from 0
to 2n-1. counter which resets after ten counts with a divide-by-10 count sequence from
binary 0000 (decimal “0”) through to 1001 (decimal “9”) is called a binary-coded-
decimal counter or BCD Counter for short and a MOD-10 counter can be constructed
using a minimum of four toggle flip-flops.

It is called a BCD counter because its ten state sequence is that of a BCD code and does
not have a regular pattern, unlike a straight binary counter. Then a single stage BCD

counter such as the 74LS90 counts from decimal 0 to decimal 9 and is therefore capable
of counting up to a maximum of nine pulses. Note also that a digital counter may count
up or count down or count up and down (bidirectional) depending on an input control
signal

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TRUTH TABLE:
QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0

PROCEDURE:
  Check all the components for their working.
  Insert the appropriate IC into the IC base.
  Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.


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7490 AS A DIVIDE BY N COUNTER (N=7):

TRUTH TABLE:

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 0 0 0

DIVIDE BY 5 COUNTER:

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TRUTH TABLE:
QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0

2-digit BCD Counter from 00 to 99

Questions:

What is a decade counter?

What do you mean by a ripple counter?
Explain the design of Modulo-N counter (N ≤ 9) using IC 7490

CONCLUSION:………………………………………………………………………………………
…………………………………………………………………………………………………………
…………………………………………………………………………………………………………
……………………………………………………………………………………………

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ASSIGNMENT NO: B8

PROBLEM STATEMENT:
Pseudo random number generator.

PLATFORM: Windows XP

PREREQUISIT : Digital trainer Kit, Connecting Wires etc.

THEORY:

A pseudorandom number generator (PRNG), also known as a deterministic random bit

generator (DRBG),[1] is an algorithm for generating a sequence of numbers whose properties
approximate the properties of sequences of random numbers. The PRNG-generated sequence is not
truly random, because it is completely determined by a relatively small set of initial values, called
the PRNG's seed (which may include truly random values). Although sequences that are closer to
truly random can be generated using hardware random number generators, pseudorandom number
generators are important in practice for their speed in number generation and their reproducibility.[2]
PRNGs are central in applications such as simulations (e.g. for the Monte Carlo method), electronic
games (e.g. for procedural generation), and cryptography. Cryptographic applications require the
output not to be predictable from earlier outputs, and more elaborate algorithms, which do not
inherit the linearity of simpler PRNGs, are needed.
Good statistical properties are a central requirement for the output of a PRNG. In general, careful
mathematical analysis is required to have any confidence that a PRNG generates numbers that are
sufficiently close to random to suit the intended use. John von Neumann cautioned about the
misinterpretation of a PRNG as a truly random generator, and joked that "Anyone who considers
arithmetical methods of producing random digits is, of course, in a state of sin."[3]

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ASSIGNMENT NO: B9

PROBLEM STATEMENT:
Design of a barrel shifter.

PLATFORM: Windows XP

PREREQUISIT : -

THEORY:

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in
one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an
implementation the output of one mux is connected to the input of the next mux in a way that
depends on the shift distance.
For example, take a four-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order
of the bits ABCD as DABC,CDAB, or BCDA; in this case, no bits are lost. That is, it can shift all of
the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and
D). The barrel shifter has a variety of applications, including being a useful component in
microprocessors (alongside the ALU).
A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one
clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an
implementation the output of one mux is connected to the input of the next mux in a way that
depends on the shift distance. For example, take a 4-bit barrel shifter, with inputs A, B, C and D.
The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits
are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any
cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including
being a useful component in microprocessors (alongside the ALU).
A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic.
For a floating-point add or subtract operation, the significance of the two numbers must be aligned,
which requires shifting the smaller number to the right, increasing its exponent, until it matches the
exponent of the larger number. This is done by subtracting the exponents, and using the barrel
shifter to shift the smaller number to the right by the difference, in one cycle. If a simple shifter were
used, shifting by n bit positions would require n clock cycles.

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ASSIGNMENT NO: C1

PROBLEM STATEMENT:
Study /Implement of VHDL and examples of Combinational and sequential
circuits
1. Combinational Circuits: Adder, MUX

PLATFORM: Windows XP

PREREQUISIT : Xillinx, Modelsim

THEORY:

Full adder

A full adder is a logical circuit that performs an addition operation on three one-bit binary
numbers often written as A, B, and Cin. The full adder produces a two-bit output sum
typically represented with the signals Cout and S where
The full adder's truth table is:

Truth Table:

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Program:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fa is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end fa;

architecture Behavioral of fa is

begin
s <= (a xor b) xor cin;
cout <= (a and b) or (b and cin) or (a and cin);

end Behavioral;

OUTPUT:

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RTL View

Simulation Waveform

Questions
1. What is a test bench in vhdl?
2. How many inputs and output are used in Full adder?
3. What are the advantages of designing?
4. Why HDL is used?
5. How many types of architecture in VHDL?
6. What is the difference between sequential and combinational ckts.?
7. Is it possible to construct full adder using half adder?
8. How many i/ps required for half subtractor?
9. Is it possible to construct full subtractor using half subtractor?

MULTIPLEXER:

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1
multiplexer, a logic value of 0 would connect to the output while a logic value of 1 would
connect to the output. In larger multiplexers, the number of selector pins is equal to where is
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the number of inputs. A 4-to-1 multiplexer has a boolean equation where A, B, C and D
are the two inputs, 1and S0 are the select lines, and Y is the output:

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity abcd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end abcd;

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architecture Behavioral of abcd is

begin
y <= a when s0 ='0' and s1 = '0' else
b when s0 ='0' and s1 = '1' else
c when s0 ='1' and s1 = '0' else
d;

end Behavioral;

OUTPUT:

RTL View

Simulation Waveform

CONCLUSION:………………………………………………………………………………………
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Digital Electronics Lab SE Computer

ASSIGNMENT NO: C2

PROBLEM STATEMENT:
Study /Implement of VHDL and examples of Combinational and sequential
circuits
1. Sequential Circuits: Asynchronous & Synchronous Counter

PLATFORM: Windows XP

PREREQUISIT : Xillinx, Modelsim

THEORY:

Down Counter:

In a binary up counter, a particular bit, except for the first bit, toggles if all the
lower-order bits are 1's. The opposite is true for binary down counters. That is, a
particular bit toggles if all the lower-order bits are 0's and the first bit toggles on
every pulse.

Taking an example, A4 A3 A2 A1 = 0100. On the next count, A4 A3 A2 A1 = 0011.

A1, the lowest-order bit, is always complemented. A2 is complemented because
all the lower-order positions (A1 only in this case) are 0's. A3 is also complemented
because all the lower-order positions, A2 and A1 are 0's. But A4 is not
complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 0
condition.

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Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity up_counter is
Port ( clk : in STD_LOGIC;
sload : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end up_counter;

architecture Behavioral of up_counter is

signal tmp : std_logic_vector(3downto 0);
begin
process(clk)
begin
if(clk' event and clk = '1') then
if sload = '0' then
tmp <= "1111";
else
tmp <= tmp -1;

end if;
end if;
end process;
q <= tmp;

end Behavioral;

OUTPUT:

RTL View

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Simulation Waveform

Questions

1. What is sequential logic?

2. How many Flip-Flops are required for mod–16 counter?
3. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns
each. How much maximum possible time required for change of state?
4. How many flip flops are required to construct a decade counter?
5. How many flip-flops are required to construct mod 30 counter?
6. What is a flip flop?
7. What is the function of clock in counter ckt?
8. What is the maximum count for decade counter?
9. What is down counter?
10. What is the count for decade down counter?

CONCLUSION:………………………………………………………………………………………
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64 DYPIEMR, Akurdi
Digital Electronics Lab SE Computer

ASSIGNMENT NO: D3

PROBLEM STATEMENT:
Study of FPGA devices (Study and Write up only).

PLATFORM: Windows XP

PREREQUISIT : -

THEORY:

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by

a customer or a designer after manufacturing – hence "field-programmable". The FPGA
configuration is generally specified using a hardware description language(HDL), similar to that
used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously
used to specify the configuration, as they were for ASICs, but this is increasingly rare.)

A Spartan FPGA from Xilinx

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable

interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-
wired in different configurations. Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic
blocks also include memory elements, which may be simple flip-flops or more complete blocks
of memory.
Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and
RAM blocks to implement complex digital computations. As FPGA designs employ very fast
I/Os and bidirectional data buses it becomes a challenge to verify correct timing of valid data
within setup time and hold time. Floor planning enables resources allocation within FPGAs to
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meet these time constraints. FPGAs can be used to implement any logical function that an ASIC
could perform. The ability to update the functionality after shipping, partial re-configuration of a
portion of the design and the low non-recurring engineering costs relative to an ASIC design
(notwithstanding the generally higher unit cost), offer advantages for many applications.
Some FPGAs have analog features in addition to digital functions. The most common analog
feature is programmable slew rate and drive strength on each output pin, allowing the engineer to
set slow rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set
stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too
slowly. Another relatively common analog feature is differential comparators on input pins
designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have
integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters
(DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-
chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its
internal programmable interconnect fabric, and field-programmable analog array (FPAA), which
carries analog values on its internal programmable interconnect fabric.

FPGA comparisons
Historically, FPGAs have been slower, less energy efficient and generally achieved less
functionality than their fixed ASIC counterparts. An older study had shown that designs
implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic
power, and run at one third the speed of corresponding ASIC implementations. More recently,
FPGAs such as the Xilinx Virtex-7 or the Altera Stratix 5 have come to rival corresponding
ASIC and ASSP solutions by providing significantly reduced power, increased speed, lower
materials cost, minimal implementation real-estate, and increased possibilities for re-
configuration 'on-the-fly'. Where previously a design may have included 6 to 10 ASICs, the same
design can now be achieved using only one FPGA.

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A Xilinx Zynq-7000 All Programmable System on a Chip.

Advantages of FPGAs include the ability to re-program in the field to fix bugs, and may include
a shorter time to market and lower non-recurring engineering costs. Vendors can also take a
middle road by developing their hardware on ordinary FPGAs, but manufacture their final
version as an ASIC so that it can no longer be modified after the design has been committed.
Xilinx claims that several market and technology dynamics are changing the ASIC/FPGA
paradigm:[24]

 Integrated circuit costs are rising aggressively

 ASIC complexity has lengthened development time
 R&D resources and headcount are decreasing
 Revenue losses for slow time-to-market are increasing
 Financial constraints in a poor economy are driving low-cost technologies
These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume
applications than they have been historically used for, to which the company attributes the
growing number of FPGA design starts (see History).
Some FPGAs have the capability of partial re-configuration that lets one portion of the device be
re-programmed while other portions continue running.
Field-Programmable Device (FPD) — a general term that refers to any type of integrated circuit
used for implementing digital hardware, where the chip can be configured by the end user to
realize different designs. Programming of such a device often involves placing the chip into a
special programming unit, but some chips can also be configured “in-system”. Another name for
FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of chips
as FPDs, we prefer the term FPD because historically the word PLD has referred to relatively
simple types of devices.
• PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels
of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although
PLA structures are sometimes embedded into full-custom chips, we refer here only to those
PLAs that are provided as separate integrated circuits and are user-programmable).
• PAL* — a Programmable Array Logic (PAL) is a relatively small FPD that has a
programmable AND-plane followed by a fixed OR-plane
• SPLD — refers to any type of Simple PLD, usually either a PLA or PAL
• CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks
on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for
this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others.
• FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows
very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs

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(AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of
flip-flops to logic resources than do CPLDs.
• HCPLDs — high-capacity PLDs: a single acronym that refers to both CPLDs and FPGAs.
This term has been coined in trade literature for providing an easy way to refer to both types of
devices. We do not use this term in the paper.
Interconnect — the wiring resources in an FPD
• Programmable Switch — a user-programmable switch that can connect a logic element to an
interconnect wire, or one interconnect wire to another
• Logic Block — a relatively small circuit blocks that is replicated in an array in an FPD. When
a circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits that can each
be mapped into a logic block. The term logic block is mostly used in the context of FPGAs, but it
could also refer to a block of circuitry in a CPLD.
• Logic Capacity — the amount of digital logic that can be mapped into a single FPD. This is
usually measured in units of “equivalent number of gates in a traditional gate array”. In other
words, the capacity of an FPD is measured by the size of gate array that it is comparable to. In
simpler terms, logic capacity can be thought of as “number of 2-input NAND gates”.
• Logic Density — the amount of logic per unit area in an FPD.
• Speed-Performance — measures the maximum operable speed of a circuit when implemented
in an FPD. For combinational circuits, it is set by the longest delay through any path, and for
sequential circuits it is the maximum clock frequency for which the circuit functions properly.
Complex programmable logic devices (CPLD)
The primary differences between CPLDs (complex programmable logic devices) and FPGAs are
architectural. A CPLD has a somewhat restrictive structure consisting of one or more
programmable sum-of-products logic arrays feeding a relatively small number of clocked
registers. The result of this is less flexibility, with the advantage of more predictable timing
delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are
dominated by interconnect. This makes them far more flexible (in terms of the range of designs
that are practical for implementation within them) but also far more complex to design for.
In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually
much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex
embedded functions such as adders, multipliers, memory, and serdes. Another common
distinction is that CPLDs contain embedded flash to store their configuration while FPGAs
usually, but not always, require external nonvolatile memory.
CONCLUSION:…………………………………………………………………………………
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68 DYPIEMR, Akurdi