Data Sheet

AD9214
10-Bit, 65 MSPS/80 MSPS/105 MSPS 3 V Analog-to-Digital Converter

FEATURES FUNCTIONAL BLOCK DIAGRAM

► SNR = 57 dB at 39 MHz Analog input (–0.5 dBFS)
► Low power
► 190 mW at 65 MSPS
► 285 mW at 105 MSPS
► 30 mW power-down mode
► 300 MHz analog bandwidth
► On-chip reference and track/hold
► 1 V p-p or 2 V p-p Analog input range option
► Single 3.3 V supply operation (2.7 V to 3.6 V)
► Twos complement or offset binary data format option Figure 1.

APPLICATIONS
► Battery-powered instruments
► Hand-held scopemeters
► Low-cost digital oscilloscopes
► Ultrasound equipment
► Cable reverse path
► Broadband wireless
► Residential power line networks
GENERAL DESCRIPTION
The AD9214 is a 10-bit monolithic sampling analog-to-digital con- PRODUCT HIGHLIGHTS
verter (ADC) with an on-chip track-and-hold circuit, and is optimized
for low cost, low power, small size, and ease of use. The product 1. High Performance.
operates up to 105 MSPS conversion rate with outstanding dynam- Outstanding ac performance from 65 MSPS to 105 MSPS. SNR
ic performance over its full operating range. greater than 55 dB typical and as high as 58 dB.
2. Low Power.
The ADC requires only a single 3.3 V (2.7 V to 3.6 V) power supply The AD9214 at 285 mW consumes a fraction of the power
and an encode clock for full performance operation. No external available in existing high-speed monolithic solutions. In sleep
reference or driver components are required for many applications. mode, power is reduced to 30 mW.
The digital outputs are TTL/CMOS compatible and a separate
3. Single Supply.
output power supply pin supports interfacing with 3.3 V or 2.5 V
The AD9214 uses a single 3 V supply, simplifying system power
logic.
supply design. It also features a separate digital output driver
The clock input is TTL/CMOS compatible. In the power-down state, supply line to accommodate 2.5 V logic families.
the power is reduced to 30 mW. A gain option allows support for 4. Small Package.
either 1 V p-p or 2 V p-p analog signal input swing. The AD9214 is packaged in a small 28-lead surface-mount
plastic package (28-SSOP).
Fabricated on an advanced CMOS process, the AD9214 is avail-
able in a 28-lead surface-mount plastic package (28-SSOP) speci-
fied over the industrial temperature range −40°C to +85°C).

Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
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Data Sheet AD9214
TABLE OF CONTENTS

Features................................................................ 1 Pin Configuration and Function Descriptions........ 8

Applications........................................................... 1 Typical Performance Characteristics..................... 9
Functional Block Diagram......................................1 Equivalent Circuits...............................................12
General Description...............................................1 Terminology......................................................... 13
Product Highlights................................................. 1 Theory of Operation.............................................15
Specifications........................................................ 3 Applying the AD9214........................................15
DC Specifications............................................... 3 Power Supplies................................................ 16
Digital Specifications.......................................... 4 Layout Information............................................16
AC Specifications............................................... 4 Evaluation Board.............................................. 16
Switching Specifications.....................................5 Schematic............................................................18
Absolute Maximum Ratings...................................7 Outline Dimensions............................................. 21
Explanation of Test Levels..................................7 Ordering Guide.................................................21
ESD Caution.......................................................7

REVISION HISTORY

4/2022—Rev. D to Rev. E
Updated Format (Universal).............................................................................................................................1
Changes to Figure 29.................................................................................................................................... 15
Changes to Ordering Guide........................................................................................................................... 21

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Data Sheet AD9214
SPECIFICATIONS

DC SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; TMIN = –40°C, TMAX = +85°C; external 1.25 V voltage reference and rated encode frequency used, unless otherwise
noted.

Table 1.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 10 10 10 Bits
ACCURACY
No Missing Codes 25°C VI Guaranteed Guaranteed Guaranteed
Full VI Guaranteed Guaranteed
Offset Error Full VI −18 0 +18 −18 +18 −18 0 +18 LSB
Gain Error1 25°C I −2 +8 −2 +8 −2 +8 %FS
Differential Nonlinearity2 25°C I −1.0 ±0.5 +1.0 −1.0 ±0.5 +1.2 −1.0 ±0.08 +1.5 LSB
(DNL) Full V −1.0 +1.2 −1.0 +1.4 +1.7 LSB
Integral Nonlinearity2 25°C I −1.35 ±0.75 +1.35 −1.5 ±0.75 +1.5 −2.2 ±1.5 +2.2 LSB
(INL) Full V −1.9 +1.9 −1.8 +1.8 −2.5 +2.5 LSB
TEMPERATURE DRIFT
Offset Error Full V 16 16 16 ppm/°C
Gain Error1 Full V 150 150 150 ppm/°C
Reference Voltage Full V 80 80 80 ppm/°C
REFERENCE (REF)
Internal Reference Voltage 25°C VI 1.18 1.23 1.28 1.18 1.23 1.28 1.18 1.23 1.28 V
Output Current3 Full V 200 200 200 µA
Input Current4 Full V 123 123 123 µA
Input Resistance Full V 10 10 10 kΩ
ANALOG INPUTS (AIN, AIN)
Differential Input Range Full V 1 or 2 V p-p
Common-Mode Voltage Full V AVDD/3 AVDD/3 AVDD/3 V
Differential Input Resistance5 Full V 20 20 20 kΩ
Differential Input Capacitance Full V 5 5 5 pF
POWER SUPPLY
Supply Voltages
AVDD Full IV 2.7 3.6 2.7 3.6 2.7 3.6 V
DrVDD Full IV 2.7 3.6 2.7 3.6 2.7 3.6 V
Supply Current
IAVDD (AVDD = 3.0 V)6 Full VI 64 75 90 105 95 110 mA
Power-Down Current7
IAVDD (AVDD = 3.0 V) Full VI 10 15 10 15 10 15 mA
Power Consumption8 Full VI 190 220 250 300 285 325 mW
PSRR 25°C I ±0.5 ±1 ±1 LSB/V
Full V ±2 ±2 ±2 mV/V
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2 Measured with 1 V AIN range for AD9214-80 and AD9214-105. Measured with 2 V AIN range for AD9214-65.
3 REFSENSE externally connected to AGND, REF is configured as an output for the internal reference voltage.
4 REFSENSE externally connected to AVDD, REF is configured as an input for the external reference voltage.
5 I0 kΩ to AVDD/3 on each input.

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Data Sheet AD9214
SPECIFICATIONS

Table 1.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
6 IAVDD is measured with an analog input of 10.3 MHz, 0.5 dBFS, sine wave, rated encode rate, and PWRDN = 0. See the Typical Performance Characteristics section and
Applying the AD9214 section for IDrVDD.
7 Power-down supply currents measured with PWRDN = 1; rated encode rate, AIN = full-scale dc input.
8 Power consumption measured with AIN = full-scale dc input.

DIGITAL SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; TMIN = –40°C, TMAX = +85°C.

Table 2.
AD9214-65 AD9214-80 AD9214-105
Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
DIGITAL INPUTS1
Logic “1” Voltage Full IV 2.0 2.0 2.0 V
Logic “0” Voltage Full IV 0.8 0.8 0.8 V
Input Capacitance Full V 2.0 2.0 2.0 pF
DIGITAL OUTPUTS2
Logic Compatibility CMOS/T CMOS/T CMOS/T V
TL TL TL
Logic “1” Voltage Full VI DrVDD – DrVDD – DrVDD – V
50 mV 50 mV 50 mV
Logic “0” Voltage Full VI 50 50 50 mV
1 Digital Inputs include ENCODE and PWRDN.
2 Digital Outputs include D0–D9 and OR.

AC SPECIFICATIONS
AC specifications based on a 1.0 V p-p full-scale input range for the AD9214-80 and AD9214-105, and a 2.0 V p-p full-scale input range for
the AD9214-65. An external reference is used. AVDD = 3 V, DrVDD = 3 V; ENCODE = maximum conversion rate; TMIN = –40°C, TMAX = +85°C;
external 1.25 V voltage reference used, unless otherwise noted.

Table 3.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SNR
Analog Input @ –0.5 dBFS
10 MHz 25°C I 55.5 58.3 56.0 58.1 51.0 53.0 dB
39 MHz 25°C I 57.1 55.0 57.1 50.5 53.0 dB
51 MHz 25°C V 55.0 53.0 dB
70 MHz 25°C V 54.0 52.6 dB
SINAD
Analog Input @ –0.5 dBFS
10 MHz 25°C I 55.0 57.8 55.5 57.6 50.0 52.0 dB
39 MHz 25°C I 56.7 54.5 56.7 50.0 52.0 dB
51 MHz 25°C V 54.5 52.0 dB
70 MHz 25°C V 52.0 dB
EFFECTIVE NUMBER OF BITS

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Data Sheet AD9214
SPECIFICATIONS

Table 3.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
Analog Input @ –0.5 dBFS
10 MHz 25°C I 8.9 9.3 9.0 9.3 8.4 Bit
39 MHz 25°C I 9.2 8.8 9.2 8.4 Bit
51 MHz 25°C V 8.8 8.4 Bit
70 MHz 25°C V 8.5 8.4 Bit
SECOND HARMONIC DISTORTION
Analog Input @ –0.5 dBFS
10 MHz 25°C I –66 –79 –64 –74 –62 –68 dBc
39 MHz 25°C I –75 –63 –76 –62 –71 dBc
51 MHz 25°C V –72 –64 dBc
70 MHz 25°C V –65 –62 dBc
THIRD HARMONIC DISTORTION
Analog Input @ –0.5 dBFS
10 MHz 25°C I –63.5 –71 –63 –72 –59 –64 dBc
39 MHz 25°C I –70 –63 –74 –59 –67 dBc
51 MHz 25°C V –78 –71 dBc
70 MHz 25°C V –65 dBc
SFDR
Analog Input @ –0.5 dBFS
10 MHz 25°C I 63.5 71 63 71 57 62 dBc
39 MHz 25°C I 70 63 71 57 62 dBc
51 MHz 25°C V 67 62 dBc
70 MHz 25°C V 64 62 dBc
TWO-TONE INTERMOD DISTORTION1
Analog Input @ –0.5 dBFS 25°C V 76 74 72 dBFS
ANALOG INPUT BANDWIDTH 25°C V 300 300 300 MHz
1 F1 = 29.3 MHz, F2 = 30.3 MHz.

SWITCHING SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; ENCODE = maximum conversion rate; TMIN = –40°C, TMAX = +85°C; external 1.25 V voltage reference used, unless
otherwise noted.

Table 4.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
ENCODE INPUT PARAMETERS1
Maximum Conversion Rate Full VI 65 80 105 MSPS
Minimum Conversion Rate Full IV 20 20 20 MSPS
Encode Pulse Width High (tEH) Full IV 6.0 5.0 3.8 ns
Encode Pulse Width Low (tEL) Full IV 6.0 5.0 3.8 ns
Aperture Delay (tA) 25°C V 2.0 2.0 2.0 ns
Aperture Uncertainty (Jitter) 25°C V 3 3 3 ps rms
DATA OUTPUT PARAMETERS
Pipeline Delays Full IV 5 5 5 Clock
Cycle
Output Valid Time (tV)1 Full V 3.0 4.5 3.0 4.5 3.0 4.5 ns

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Data Sheet AD9214
SPECIFICATIONS

Table 4.
Test AD9214-65 AD9214-80 AD9214-105
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
Output Propagation Delay1 (tPD) Full V 4.5 6.0 4.5 6.0 4.5 6.0 ns
TRANSIENT RESPONSE TIME 25°C V 5 5 5 ns
OUT-OF-RANGE RECOVERY TIME 25°C V 5 5 5 ns
1 tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50% levels of the digital output swing. The digital output load during test is not to exceed an ac
load of 5 pF or a dc current of ±40 µA.

Figure 2. Timing Diagram

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Data Sheet AD9214
ABSOLUTE MAXIMUM RATINGS

Table 5. EXPLANATION OF TEST LEVELS

Parameter Rating
Table 6.
Electrical
Level Description
AVDD Voltage 4 V max
I 100% production tested.
DrVDD Voltage 4 V max
II 100% production tested at 25°C and guaranteed by design and
Analog Input Voltage −0.5 V to AVDD + 0.5 V
characterization at specified temperatures.
Analog Input Current 0.4 mA
III Sample tested only.
Digital Input Voltage −0.5 V to AVDD + 0.5 V
IV Parameter is guaranteed by design and characterization testing.
Digital Output Current 20 mA max
V Parameter is a typical value only.
REF Input Voltage −0.5 V to AVDD + 0.5 V
VI 100% production tested at 25°C and guaranteed by design and
Environmental1 characterization for industrial temperature range.
Operating Temperature Range (Ambient) −40°C to +125°C
Maximum Junction Temperature 150°C ESD CAUTION
Lead Temperature (Soldering, 10 sec) 150°C ESD (electrostatic discharge) sensitive device. Charged devi-
Storage Temperature Range (Ambient) −65°C to +150°C ces and circuit boards can discharge without detection. Although
1 this product features patented or proprietary protection circuitry,
Typical thermal impedances (package = 28 SSOP); θJA = 49°C/W. These
damage may occur on devices subjected to high energy ESD.
measurements were taken on a six-layer board in still air with a solid ground
Therefore, proper ESD precautions should be taken to avoid
plane.
performance degradation or loss of functionality.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.

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Data Sheet AD9214
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description
1 OR CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was outside the converter’s range for the current
output data.
2 DFS/GAIN Data Format Select and Gain Mode Select. Connect externally to AVDD for twos complement data format and 1 V p-p analog input range.
Connect externally to AGND for Offset Binary data format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for twos
complement data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset Binary data format and a 2 V
p-p analog input range.
3 REFSENSE Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND, which enables the internal 1.25 V reference,
and configures REF (Pin 4) as an analog reference output pin. Connecting REFSENSE externally to AVDD disables the internal reference,
and configures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean and accurate 1.25 V (± 5%)
reference input.
4 REF Reference input or output as configured by REFSENSE (Pin 3). When configured as an output (REFSENSE = AGND), the internal
reference (nominally 1.25 V) is enabled and is available to the user on this pin. When configured as an input (REFSENSE = AVDD), the
user must drive REF with a clean and accurate 1.25 V (± 5%) reference. This pin should be bypassed to AGND with an external 0.1 µF
capacitor, whether it is configured as an input or output.
5, 8, 11 AGND Analog Ground.
6, 7, 12 AVDD Analog Power Supply, Nominally 3 V.
9 AIN Positive terminal of the differential analog input for the ADC.
10 AIN Negative terminal of the differential analog input for the ADC. This pin can be left open if operating in single-ended mode, but it is preferable
to match the impedance seen at the positive terminal (see Driving the Analog Inputs).
13 ENCODE Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.
14 PWRDN CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH for power-down mode (digital outputs in high
impedance state). PWRDN has an internal 10 kΩ pull-down resistor to ground.
15, 23 DGND Digital Output Ground.
16, 24 DrVDD Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V.
17 to 22, 25 D0 (LSB) to D5, CMOS Digital Outputs of ADC.
to 28 D6 to D9 (MSB)

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Data Sheet AD9214
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. FFT: fS = 105 MSPS, fIN = ~50.3 MHz; AIN = –0.5 dBFS Differential, 1 Figure 7. FFT: fS = 65 MSPS, fIN = 15.3 MHz (2 V p-p) with AD8138 Driving AIN
V p-p Analog Input Range

Figure 8. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Figure 5. FFT: fS = 80 MSPS, fIN = 70 MHz; AIN = –0.5 dBFS, 1 V p-p Analog Frequency (1 V p-p, fS = 105 MSPS)
Input Range

Figure 9. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Figure 6. FFT: fS = 105 MSPS; fIN = 70 MHz (1 V p-p) Frequency (1 V p-p, fS = 80 MSPS)

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Data Sheet AD9214
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. Harmonic Distortion (Second and Third) and SFDR vs. AIN Figure 13. SINAD and SFDR vs. Encode Rate (fIN = 10.3 MHz; 1 V p-p and 2 V
Frequency (1 V p-p and 2 V p-p, fS = 65 MSPS) p-p)

Figure 11. Two-Tone Intermodulation Distortion (29.3 MHz, 30.3 MHz; 1 V p-p, Figure 14. SINAD and SFDR vs. Encode Pulse Width High (1 V p-p)
fS = 80 MSPS)

Figure 15. IAVDD and IDrVDD vs. Encode Rate (fAIN = 10.3 MHz, –0.5 dBFS, and
–3 dBFS) CLOAD on Digital Outputs ~7 pF
Figure 12. Two-Tone Intermodulation Distortion (30 MHz and 31 MHz; 1 V p-p,
fS = 105 MSPS)

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Data Sheet AD9214
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16. SINAD/SNR vs. Temperature (fAIN = 10.3 MHz, fENCODE = 105 MSPS, Figure 19. ADC Reference vs. Current Load
1 V p-p)

Figure 20. INL @ 80 MSPS

Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)

Figure 21. DNL @ 80 MSPS

Figure 18. ADC Reference vs. Temperature (with 200 µA Load)

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Data Sheet AD9214
EQUIVALENT CIRCUITS

Figure 22. Analog Input Stage

Figure 26. REF Configured as an Input

Figure 23. Encode Inputs

Figure 24. Digital Output Stage

Figure 25. REF Configured as an Output

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Data Sheet AD9214
TERMINOLOGY

Analog Bandwidth Gain Error

The analog input frequency at which the spectral power of the Gain error is the difference between the measured and ideal full
fundamental frequency (as determined by the FFT analysis) is scale input voltage range of the ADC.
reduced by 3 dB.
Harmonic Distortion, Second
Aperture Delay
The ratio of the rms signal amplitude to the rms value of the second
The delay between the 50% point of the rising edge of the EN- harmonic component, reported in dBc.
CODE command and the instant at which the analog input is
sampled. Harmonic Distortion, Third

Aperture Uncertainty (Jitter) The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
The sample-to-sample variation in aperture delay.
Integral Nonlinearity
Differential Analog Input Resistance,
The deviation of the transfer function from a reference line meas-
Differential Analog Input Capacitance, and
ured in fractions of 1 LSB using a “best straight line” determined by
Differential Analog Input Impedance a least square curve fit.
The real and complex impedances measured at each analog input Minimum Conversion Rate
port. The resistance is measured statically and the capacitance
and differential input impedances are measured with a network The encode rate at which the SNR of the lowest analog signal
analyzer. frequency drops by no more than 3 dB below the guaranteed limit.
Differential Analog Input Voltage Range Maximum Conversion Rate
The peak-to-peak differential voltage that must be applied to the The encode rate at which parametric testing is performed.
converter to generate a full-scale response. Peak differential volt-
age is computed by observing the voltage on a single pin and sub- Output Propagation Delay
tracting the voltage from the other pin, which is 180 degrees out of The delay between a differential crossing of ENCODE and EN-
phase. Peak-to-peak differential is computed by rotating the inputs CODE and the time when all output data bits are within valid logic
phase 180 degrees and taking the peak measurement again. Then levels.
the difference is computed between both peak measurements.
Noise (for any range within the ADC):
Differential Nonlinearity
FSdBm − SNRdBc − SignaldBFS
The deviation of any code width from an ideal 1 LSB step. VNOISE = Z × 0 . 001 × 10 10

Effective Number of Bits where:

Z is the input impedance.
The effective number of bits (ENOB) is calculated FS is the full-scale of the device for the frequency in question.
from the measured SNR based on the equation: SNR is the value for the particular input level.
SINADMEASURED − 1.76 dB + 20 log Full Scale Signal is the signal level within the ADC reported in dB below
Actual
ENOB = 6 . 02 full-scale. This value includes both thermal and quantization noise.
Encode Pulse Width/Duty Cycle Power Supply Rejection Ratio (PSRR)
Pulse width high is the minimum amount of time that the ENCODE The ratio of a change in input offset voltage to a change in power
pulse should be left in Logic "1" state to achieve rated performance; supply voltage.
pulse width low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing tENCH in text. At Signal-to-Noise-and-Distortion (SINAD)
a given clock rate, these specs define an acceptable Encode duty The ratio of the rms signal amplitude (set 0.5 dB below full scale) to
cycle. the rms value of the sum of all other spectral components, including
Full-Scale Input Power harmonics but excluding dc.

Expressed in dBm. Computed using the following equation:

V2FULLSCALE rms
ZINPUT
PowerFULLSCALE = 10 log 0 . 001

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Data Sheet AD9214
TERMINOLOGY

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (that is,
degrades as signal level is lowered), or dBFS (always related back
to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May be
reported in dBc (that is, degrades as signal level is lowered), or in
dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the second and third harmonic)
reported in dBc.
Transient Response Time
Transient response is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above positive
full scale to 10% above negative full scale, or from 10% below
negative full scale to 10% below positive full scale.

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Data Sheet AD9214
THEORY OF OPERATION

The AD9214 architecture is a bit-per-stage pipeline converter utiliz- DFS/GAIN

ing switch capacitor techniques. These stages determine the 7
MSBs and drive a 3-bit flash. Each stage provides sufficient overlap The DFS/GAIN (Data Format Select/Gain) input (Pin 2) controls
and error correction allowing optimization of comparator accuracy. both the output data format and gain (analog input voltage range) of
The input buffer is differential and both inputs are internally biased. the ADC. The table below describes its operation.
This allows the most flexible use of ac or dc and differential or Table 8. Data Format and Gain Configuration
single-ended input modes. The output staging block aligns the data, External DFS/GAIN Differential Analog Input
carries out the error correction and feeds the data to output buffers. Connection Voltage Range Output Data Format
The output buffers are powered from a separate supply, allowing AGND 1 V p-p Offset Binary
support of different logic families. During power-down, the outputs AVDD 1 V p-p Twos Complement
go to a high impedance state.
REF 2 V p-p Twos Complement
APPLYING THE AD9214 Floating 2 V p-p Offset Binary

Encoding the AD9214 Driving the Analog Inputs

Any high-speed A/D converter is extremely sensitive to the quality The analog input to the AD9214 is a differential buffer. As shown in
of the sampling clock provided by the user. A Track/ Hold circuit the equivalent circuits, each of the differential inputs is internally dc
is essentially a mixer. Any noise, distortion, or timing jitter on the biased at ~AVDD/3 to allow ac-coupling of the analog input signal.
clock will be combined with the desired signal at the A/D output. The analog signal may be dc-coupled as well. In this case, the
For that reason, considerable care has been taken in the design of dc load will be equivalent to ~10 kΩ to AVDD/3, and the dc common-
the ENCODE input of the AD9214, and the user is advised to give mode level of the analog signals should be within the range of
commensurate thought to the clock source. The ENCODE input is AVDD/3 ±200 mV. For best dynamic performance, impedances at
fully TTL/CMOS compatible, and should normally be driven directly AIN and AIN should match.
from a low jitter, crystal-controlled TTL/CMOS oscillator.
Driving the analog input differentially optimizes ac performance,
The ENCODE input is internally biased, allowing the user to ac-cou- minimizing even order harmonics and taking advantage of com-
ple in the clock signal. The cleanest clock source is often a crystal mon-mode rejection of noise. A differential signal may be transform-
oscillator producing a pure sine wave. Figure 27 illustrates ac er-coupled, as illustrated in Figure 28, or driven from a high-per-
coupling such a source to the ENCODE input. formance differential amplifier such as the AD8138 illustrated in
Figure 29.

Figure 27. AC-Coupled Encode Circuit

Figure 28. Single-Ended-to-Differential Conversion Using a Transformer

Reference Circuit
The reference circuit of the AD9214 is configured by REFSENSE Special care was taken in the design of the analog input section
(Pin 3). By externally connecting REFSENSE to AGND, the ADC of the AD9214 to prevent damage and corruption of data when the
is configured to use the internal reference (~1.25 V), and the REF input is overdriven. The optimal input range is 1.0 V p-p, but the
pin connection (Pin 4) is configured as an output for the internal AD9214 can support a 2.0 V p-p input range with some degradation
reference voltage. in performance (see Table 8).
If REFSENSE is externally connected to AVDD, the ADC is config-
ured to use an external reference. In this mode, the REF pin is
configured as a reference input, and must be driven by an external
1.25 V reference.
In either configuration, the analog input voltage range (either 1
V p-p or 2 V p-p as determined by DFS/Gain) will track the
reference voltage linearly, and an external bypass capacitor should Figure 29. DC-Coupled Analog Input Circuit
be connected between REF and AGND to reduce noise on the
reference. In practice, no appreciable degradation in performance
occurs when an external reference is adjusted ±5%.

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Data Sheet AD9214
THEORY OF OPERATION

POWER SUPPLIES LAYOUT INFORMATION

The AD9214 has two power supplies, AVDD and DrVDD. AVDD and The schematic of the evaluation board (Figure 30) represents a
AGND supply power to all the analog circuitry, the inputs and the typical implementation of the AD9214. A multilayer board is recom-
internal timing and digital error correction circuits. AVDD supply mended to achieve best results. It is highly recommended that high
current will vary slightly with encode rate, as noted in the Typical quality, ceramic chip capacitors be used to decouple each supply
Performance Characteristics section. pin to ground directly at the device. The pinout of the AD9214
facilitates ease of use in the implementation of high frequency,
DrVDD and DGND supply only the CMOS digital outputs, allowing high resolution design practices. All of the digital outputs and their
the user to adjust the voltage level to match downstream logic. supply and ground pin connections are segregated to one side
DrVDD current will vary depending on the voltage level, external of the package, with the inputs on the opposite side for isolation
loading capacitance, and the encode frequency. Designs that min- purposes.
imize external load capacitance will reduce power consumption Care should be taken when routing the digital output traces. To
and reduce supply noise that may affect ADC performance. The prevent coupling through the digital outputs into the analog portion
maximum DrVDD current can be calculated as of the AD9214, minimal capacitive loading should be placed on
IDrVDD = VDrVDD × CLOAD × fencode × N these outputs. It is recommended that a fan-out of only one gate
should be used for all AD9214 digital outputs.
where N is the number of output bits, 10 in the case of the AD9214.
The layout of the encode circuit is equally critical. Any noise
This maximum current is for the condition of every output bit received on this circuitry will result in corruption in the digitization
switching on every clock cycle, which can only occur for a full-scale process and lower overall performance. The Encode clock must be
square wave at the Nyquist frequency, fENCODE /2. In practice, isolated from the digital outputs and the analog inputs.
IDrVDD will be the average number of output bits switching, which
will be determined by the encode rate and the characteristics of EVALUATION BOARD
the analog input signal. The performance curves section provides The AD9214 evaluation board offers designers an easy way to eval-
a reference of IDrVDD versus encode rate for a 10.3 MHz sine wave uate device performance. The user must supply an analog input
driving the analog input. signal, encode clock reference, and power supplies. The digital
Both power supply connections should be decoupled to ground at outputs of the AD9214 are latched on the evaluation board, and are
or near the package connections, using high quality, ceramic chip available with a data ready signal at a 40-pin edge connector. Refer
capacitors. A single ground plane is recommended for all ground to the evaluation board and Schematic sections, and Table 11.
(AGND and DGND) connections.
Power Connections
The PWRDN control pin configures the AD9214 for a sleep mode
when it is logic HIGH. PWRDN floats logic LOW for normal opera- Power to the board is supplied via three detachable, 4-pin power
tion. In sleep mode, the ADC is not active, and will consume less strips (U4, U9, and U10). These 12 pins should be driven as
power. When switching from sleep mode to normal operation, the outlined in the Table 9.
ADC will need ~15 clock cycles to recover to valid output data. Table 9. Power Supply Connections for AD9214
Pin Designator External Supply Required
Digital Outputs
1 LVC 3V
Care must be taken when designing the data receivers for the 3 5V 5 V (optional Z1 supply)
AD9214. It is recommended that the digital outputs drive a series 5 –5 V –5 V (optional Z1 supply)
resistor (for example, 100 Ω) followed by a gate like the 74LCX821.
To minimize capacitive loading, there should be only one gate on 7 VCC 3V
each output pin. An example of this is shown in the evaluation 9 VDD 3V
board schematic in Figure 30. The series resistors should be placed 11 DAC 5V
as close to the AD9214 as possible to limit the amount of current 2, 4, 6, 8, 10, 12 GND Ground
that can flow into the output stage. These switching currents are
Note that the +5 V and –5 V supplies are optional, and only
confined between ground (DGND) and the DrVDD pins. Standard
required if the user adds differential op amp Z1 to the board.
TTL gates should be avoided since they can appreciably add to
the dynamic switching currents of the AD9214. It should also be Reference Circuit
noted that extra capacitive loading will increase output timing and
invalidate timing specifications. Digital output timing is guaranteed The evaluation board is configured at assembly to use the
with 10 pF loads. AD9214's on-board reference. To supply an external reference,
the user must connect the REFSENSE pin to VCC by removing the

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Data Sheet AD9214
THEORY OF OPERATION

jumper block connecting E25 to E26, and placing it between E19 replacing it between E3 and E2. In this configuration, capacitor C2
and E24. In this configuration, an external 1.25 V reference must be stabilizes the self-bias of AIN, and resistor R2 provides a matched
connected to jumper connection E23. Jumper connections E19 to impedance for a 50 Ω source at J1.
E21, E24, and resistors R13 to R14 are omitted at assembly, and
not used in the evaluation of the AD9214. Transformer T1 can be bypassed by moving the jumper normally
between E40 and E38 to connect E40 to E37, and moving the
Gain/Data Format jumper normally between E39 and E10 to connect E7 to E10.
In this configuration, the analog input of the AD9214 is driven
The evaluation board is assembled with the DFS/GAIN pin connect- single ended, directly from J1; and R3 (normally omitted) should be
ed to ground; this configures the AD9214 for a 1 V p-p analog input installed to terminate any cable connected to J1.
range, and offset binary data format. The user may remove this
jumper and replace it to make one of the connections described Using the AD8138
in the table below to configure the AD9214 for different gain and
output data format options. An optional driver circuit for the analog input, based on the AD8138
differential amplifier, is included in the layout of the AD9214 evalua-
Table 10. Data Format and Gain Configuration for Evaluation Board tion board. This portion of the evaluation circuit is not populated
DFS/GAIN Jumper DFS/GAIN Differential Output Data when the board is manufactured, but can be easily be added by the
Placement Connection AINRange Format user. Resistors R5, R16, R18, and R25 are the feedback network
E18 to E12 AGND 1 V p-p Offset Binary that sets the gain of the AD8138. Resistors R23 and R24 set the
E16 to E11 AVDD 1 V p-p Twos Complement common-mode voltage at the output of the op amp. Resistors R27
E15 to E14 REF 2 V p-p Twos Complement and R28, and capacitor C15, form a low-pass filter at the output of
E17 to E13 Floating 2 V p-p Offset Binary
the AD8138, limiting its noise contribution into the AD9214.
Once the drive circuit is populated, the user should remove the
Power-Down jumper block normally between E40 and E38, and place it between
The evaluation board is configured at assembly so that the PWRDN E40 and E41. This will ac-couple the analog input signal from SMB
input floats low for normal operating condition. The user may add connector J1 to the AD8138 drive circuit. The user will also need to
a jumper between option holes E5 and E6 to connect PWRDN to remove the jumper blocks that normally connect E39 to E10 and E1
AVCC, configuring the AD9214 for power-down mode. to E3 to remove transformer T1 from the circuit.

Encode Signal and Distribution DAC Reconstruction Circuit

The encode input signal should drive SMB connector J5, which The data available at output connector U2 is also reconstructed
has an on-board 50 Ω termination. A standard CMOS compatible by DAC U11, the AD9752. This 12-bit, high-speed digital-to-analog
pulse source is recommended. Alternatively, the user can adjust converter is included as a tool in setting up and debugging the eval-
the dc level of an ac-coupled clock source by adding resistor R11, uation board. It should not be used to measure the performance
normally omitted. J5 drives the AD9214 ENCODE input and one of the AD9214, as its performance will not accurately reflect the
gate of U12, which buffers and distributes the clock signal to the performance of the ADC. The DAC’s output, available at J2, will
on-board latch (U3), the reconstruction DAC (U11), and the output drive 50 Ω. The user can add a jumper block between E8 and E9 to
data connector (U2). The board comes assembled with timing activate the SLEEP function of the DAC.
options optimized for the DAC and latch; the user may invert the
DR signal at Pin 37 of edge connector U2 by removing the jumper
block between E34 and E35, and reinstalling it between E35 and
E36.

Analog Input
The analog input signal is connected to the evaluation board by
SMB connector J1. As configured at assembly, the signal is ac
coupled by capacitor C10 to transformer T1. This 1:1 transformer
provides a 50 Ω termination for connector J1 via 25 Ω resistors R1
and R4. T1 also converts the signal at J1 into a differential signal
for the analog inputs of the AD9214. Resistor R3, normally omitted,
can be used to terminate J1 if the transformer is removed.
The user can reconfigure the board to drive the AD9214 single-
endedly by removing the jumper block between E1 and E3, and
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Data Sheet AD9214
SCHEMATIC

Figure 30. PCB Schematic

Figure 31. PCB Top Side Silkscreen Figure 32. PCB Top Side Copper

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Data Sheet AD9214
SCHEMATIC

Figure 33. PCB Bottom Side Silkscreen Figure 36. PCB Power Layers—Layers 3 and 4

Figure 34. PCB Bottom Side Copper

Figure 35. PCB Ground Layer—Layer TBD

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Data Sheet AD9214
SCHEMATIC

Table 11. AD9214/PCB Bill of Material

Number Quantity Reference Designator Device Package Value
1 1 N/A PCB
2 19 C1 to C3, C5 to C14, C16 to C20, C25 to C28 Capacitor 603 0.1 µF
3 4 C21 to C24 Capacitor CAPTAJD 10 µF
4 11 C4 Capacitor 603 0.01 µF
5 4 R1, R2, R4, R8 Resistor 1206 25 Ω
6 4 R7, R10, R12, R17 Resistor 1206 50 Ω
7 4 U5 to U8 Resistor RPAK_742 100 Ω
8 1 R21 Resistor 1206 0Ω
9 2 R6, R9 Resistor 1206 2000 Ω
10 37 E1 to E6, E8 to E9, E11 to E27, E29, E31 to E41 Test Points TSW-120-07-G-S
Jumper Connections SMT-100-BK-G
11 3 J1, J2, J5 Connector SMB 51-52-220
12 1 U12 Clock Chip SOIC SN74LVC86
13 1 U11 DAC SOIC AD9752
14 1 U3 Latch SOIC 74LCX821
15 1 U1 ADC/DUT SOIC AD9214
16 1 U2 40-Pin Header Samtec TSW-120-07-G-D
17 1 T1 Transformer Mini Circuits ADT1-1WT
18 3 U4, U9, U10 Power Strip Newark 95F5966
Power Connector 25.602.5453.0
191 3 C1, C20, C28 Capacitor 603 0.1 µF
201 2 C30, C29 Capacitor CAPTAJD 10 µF
211 1 C15 Capacitor 603 15 pF
221 4 R5, R18, R25, R26 Resistor 1206 500 Ω
231 1 R23 Resistor 1206 1 kΩ
241 1 R24 Resistor 1206 4 kΩ
251 3 R11, R15, R16 Resistor 1206 User Select
261 2 R13, R14 Resistor 1206 N/A
271 3 R27, R28, R3 Resistor 1206 50 Ω
281 1 R19 Resistor 1206 0Ω
291 1 Z1 Op Amp SOIC AD8138
1 This item is included in the PCB design, but is omitted at assembly.

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Data Sheet AD9214
OUTLINE DIMENSIONS

Figure 37. 28-Lead Shrink Small Outline Package

(RS-28)
Dimensions shown in inches and millimeters

Updated: April 05, 2022

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
AD9214BRSZ-105 -40°C to +85°C 28-Lead SSOP Tube RS-28
AD9214BRSZ-65 -40°C to +85°C 28-Lead SSOP Tube RS-28
AD9214BRSZ-80 -40°C to +85°C 28-Lead SSOP Tube RS-28
AD9214BRSZ-RL105 -40°C to +85°C 28-Lead SSOP Reel, 1500 RS-28
AD9214BRSZ-RL65 -40°C to +85°C 28-Lead SSOP Reel, 1500 RS-28
AD9214BRSZ-RL80 -40°C to +85°C 28-Lead SSOP Reel, 1500 RS-28
1 Z = RoHS Compliant Part.

©2001-2022 Analog Devices, Inc. All rights reserved. Trademarks and Rev. E | 21 of 21
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.