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Published in IET Power Electronics

Received on 3rd March 2009
Revised on 29th November 2009
doi: 10.1049/iet-pel.2009.0184

ISSN 1755-4535

Modular multilevel inverter: pulse width

modulation and capacitor balancing technique
G.P. Adam1 O. Anaya-Lara1 G.M. Burt1 D. Telford2
B.W. Williams1 J.R. McDonald1
1
Department of Electronic and Electrical Engineering, Strathclyde University, Royal College Building, 204 George Street,
Glasgow, G1 1XW, UK
2
PWM Drives Ltd, 55 Woodhall Road, Edinburgh, EH13 0HD, UK
E-mail: grain.adam@eee.strath.ac.uk

Abstract: Modular multilevel inverters have been proposed as a potential replacement for diode-clamped
inverters in high-voltage, high-power applications as they can be extended to any number of levels without
introducing significantly more complexity to the control system. This study discusses in detail the principle of
operation, carrier-based pulse width modulation and a capacitors voltage balancing technique for three-level
and five-level modular inverters. The modulation and balancing strategy presented are confirmed by
simulations and the results are discussed.

1 Introduction the switching frequency) and low common mode voltage

[2 – 12]. Nevertheless, diode-clamped inverters suffer from
Multilevel inverters have drawn interest in the electrical the problem of voltage imbalance of the dc link capacitors;
power industry in recent years. They offer a set of features this problem increases complexity with an increasing
that are well suited to high-voltage drive systems and power number of levels [2, 3]. The effect of stray inductance in
system applications such as high voltage dc (HVDC) the clamping paths is a problem.
transmission, reactive power compensation equipment, power
conditioning, active power filtering and so on. The unique The two-switch based modular multilevel inverters,
structure of multilevel voltage source inverters allow them to proposed in [13], is simpler than the cascaded four-switch
operate at high voltages with low harmonic content without H-bridge-based converter and has several advantages, such
the use of transformers and filter circuits, and without the as modular extension to any number of levels and
need to increase the switching frequency [1–3]. redundancy.

For ac/dc/ac conversion, which is a common requirement The operating principle of the modular multilevel inverter
in many high-voltage high-power applications, the diode- is discussed in [13– 15] with respect to only one two-level cell
clamped converter topology is preferred, because it inherits all and space vector pulse width modulation (PWM) is used
the features of two-level inverters such as ease of regeneration with the multilevel inverter. The use of space vector
and interconnection of the two ac ends via a common dc link. modulation with the modular multilevel converter is vague,
It also allows the number of ac input and output phases to be because the converter depends on phase voltage redundancy
different. However, the proper use of this topology requires in balancing the capacitor voltages rather than line-to-line
balancing of the dc link capacitor voltages when non-zero real voltage as in case of the diode-clamped inverter. However,
power is exchanged between the two ac sides [1–9]. detailed discussion of the principle of operation, multilevel
PWM and cell capacitor balancing methods has not been
Some attractive features of diode-clamped multilevel given. Classification of modular multilevel converters,
inverters are low dv/dt compare to two-level inverters (at capacitor voltage balancing methods and its control systems

702 IET Power Electron., 2010, Vol. 3, Iss. 5, pp. 702– 715
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-pel.2009.0184
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have been discussed [16]; however, detailed explanation of 2 Modular multilevel inverter
the necessary capacitor balancing method, modulation and
power paths are vague. Additionally, the capacitor voltage 2.1 Basic operating principle
balancing method proposed has several drawbacks, mainly
Fig. 1a shows one cell of a modular multilevel converter.
it requires external capacitor voltage references and does not
When the switching device Sm is on and Sc is off, output
withstand unbalanced operation or severe transients such as
voltage Vo ¼ 0; when the switching device Sm is off and Sc
three-phase and asymmetrical faults. The aim of this paper
is on, voltage Vo ¼ Vdc . Table 1 summarises the switch
is to consider these outstanding issues, extending the study
states of a cell and their resultant influence on associated
to three- and five-level modular inverters. The modulation
technique is based on sinusoidal pulse width modulation
(SPWM), and the dc link capacitor balancing method is
Table 1 Switching states of a cell
discussed in detail and verified by Simulink simulations.
The capacitor voltage balancing method proposed in this Sm Sc V0 Current Power Capacitor
paper does not require the specification of an external direction path state
reference; instead it distributes the dc link voltage equally
between the bridge capacitors. This allows the dc link on off 0 i0 . 0 Sm unchanged
voltage to be ramped up from 0 to reduce the inrush on off 0 i0 , 0 Dm unchanged
current during starting and the method is capable of
maintaining voltage balance of the dc link capacitors during off on Vdc i0 . 0 Dc charging
unbalanced operation and any faults. off on Vdc i0 , 0 Sc discharging

Figure 1 Modular multilevel inverters using half-bridge cells

a Structure of one cell
b and c One phase of a three-level and five-level modular inverters

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capacitor voltages. No Vo ¼ 2Vdc state is possible, as with H- (i) Turn on Sa1 , Sa3 , Sx2 and Sx4 .
bridge cells.
(ii) Turn on Sa2 , Sa3 , Sx1 and Sx4 .
In Fig. 1b each voltage level can be synthesised by
simultaneously turning on four switching devices. At any (iii) Turn on Sa2 , Sa4 , Sx1 and Sx3 .
instant two switches must belong to (Sa1 , Sa2 , Sa3 and Sa4)
and the remaining two must be auxiliary switches (Sx1 , Sx2 , (iv) Turn on Sa1 , Sa4 , Sx2 and Sx3 .
Sx3 and Sx4).
3. For voltage level Va0 = −1/2Vdc , turn on all upper
There are four complementary switch pairs in each phase; auxiliary switches (Sx1 and Sx2) and all lower main switches
turning on one switch in the pair will preclude the other from (Sa3 and Sa4).
being turned on. The four complementary switches are (Sa1 ,
Sx1), (Sa2 , Sx2), (Sa3 , Sx3) and (Sa4 , Sx4). The voltage across Table 2 lists the voltage levels and their corresponding
each cell capacitor is 1/2Vdc and the switching device switch states. State condition 1 means the switch is on, and
voltage stress is limited to one capacitor voltage. For an 0 means the switch is off. In order to maintain equal
n-level inverter, the voltage across each capacitor and voltage stress on the switching devices, the voltage across
switching device is limited to Vdc/(n 2 1) whereas the each cell capacitor must be maintained at 1/2Vdc . The
number of switching devices (e.g. insulated gate bipolar resultant phase voltage referred to the supply mid-point is
transistor (IGBT) plus free wheel diode) required per phase shown in Fig. 2a.
is double that for the diode-clamped converter. The
number of capacitors required for a three-phase modular
multilevel converter is 6n 2 6 (2n 2 2 per phase), while no
clamping diodes are required. Table 2 Switch combinations for a three-level modular
converter
To explain how the multilevel waveform voltage is Output Switch states
synthesised, the dc source midpoint is used as the output voltage
voltage reference. Using the three-level converter circuit shown Sa1 Sa2 Sa3 Sa4 Sx1 Sx2 Sx3 Sx4
Vao
in Fig. 1b as an example, there are six switch combinations to
synthesise a three-level voltage between nodes a and 0: 1/2Vdc 1 1 0 0 0 0 1 1
0 1 0 1 0 0 1 0 1 (i)
1. For voltage level Va0 = 1/2Vdc , turn on all upper main
0 1 1 0 1 0 0 1 (ii)
switches (Sa1 and Sa2) and all lower auxiliary switches (Sx3
and Sx4). 0 1 0 1 1 0 1 0 (iii)
1 0 0 1 0 1 1 0 (iv)
2. For voltage level Va0 ¼ 0, there are four switch
combinations: −1/2Vdc 0 0 1 1 1 1 0 0

Figure 2 Phase voltage and gate signals generation using phase disposition (PD) level shifted carriers
a Phase voltage referred to supply mid point
b Carrier and reference waveforms for a three-level modular multilevel inverter

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2.2 PWM charge. Fig. 3 shows capacitor loading when pole a is

attached to the zero voltage level, with all possible switch
In the studies conducted, carrier-based PWM is used to combinations. The load connection in Fig. 3a represents
separately control each phase leg of the modular multilevel the switch combination (1010/0101) which can cause
inverter and to allow the line-to-line voltage to be voltage imbalance because of the connection of one output
developed implicitly. These carrier-based PWM schemes phase to the point between capacitors C2 and C4 . If the
are derived from the carrier disposition strategy [17, 18]. current direction indicated in Fig. 3 is assumed to be
For an n-level modular multilevel inverter, this strategy positive, for ia . 0 the lower capacitor C4 discharges and
arranges n 2 1 triangular carriers with the same frequency upper capacitor C2 charges, whereas the upper capacitor
and amplitude so that they occupy a contiguous band over discharges and the lower charges for ia , 0.
the range +1/2Vdc to −1/2Vdc . A reference waveform for
each phase is then compared against the carriers to The load connections shown in Figs. 3a – d represent the
determine how the phase leg should be switched (Fig. 2b). redundant switch states (1010/0101, 0110/1001, 0101/1010
If the reference is greater than a carrier signal, then the and 1001/0110) which are effective for balancing purposes
active device corresponding to that carrier is switched on, because the upper and lower capacitors are alternatively
and if the reference is less than the carrier signal, then the used as energy sources to supply power to the load. Any
active device corresponding to that carrier is switched off. capacitor voltage balancing strategies using carrier-based or
space vector modulation must use these switch
From Table 2 and Fig. 2b, when the reference signal is less combinations periodically and for a relatively short duration
than the upper carrier yc1 and greater than lower carrier yc2 in order to compensate for the capacitor voltage error.
there are four possible switch combinations [(i) – (iv)], all Table 2 summarises all the switch combinations and their
connecting pole a to the 0 level. Any of these switch effect on each capacitor voltage.
combinations produce a zero voltage level and can be
selected in order to maintain voltage balance among the Based on Fig. 3 and Table 3, for the three-level modular
cell capacitors. inverter, when pole a is connected to the zero level, the cell
capacitors behave as follows: during the positive half cycle
For modular multilevel inverters, the modulation index, m, of the load current ia . 0 the upper capacitors charge and
and the frequency ratio, mf , are defined as for conventional lower capacitors discharge; and vice versa during the
multilevel PWM [19– 21] negative half of the load current, ia , 0.
2Am
m= (1) Based on these observations, the developed capacitor
(n − 1)Ac voltage balancing method for a three-level inverter can be
fc summarised as follows:
mf = (2)
fm (i) Sort the upper and lower capacitors according to their
voltage magnitudes using
where Am and Ac denote the amplitude of modulating and
carrier signals; and fm and fc denote their respective Kupper_max ¼ max(Vc1 ,Vc2),
frequencies.
Kupper_min ¼ min(Vc1 ,Vc2),
2.3 Three-level capacitor voltage
balancing method KLower_max ¼ max(Vc3 ,Vc4) and

There are four switch combinations to synthesise the zero KLower_min ¼ min(Vc3 ,Vc4).
voltage level in a three-level modular inverter; these
combinations are referred to as redundant switch states. In (ii) During the load current positive half cycle, select a switch
a modular multilevel inverter, the redundant switch states state that charges the upper capacitor retaining the minimum
are groups of switch states that produce the same phase voltage and discharges the lower capacitor retaining the
voltage rather than the line-to-line voltage as in the diode- maximum voltage.
clamped multilevel inverters case. If pole a is attached to
either the positive or negative dc rails to synthesise voltage (iii) During the load current negative half cycle, select a
levels 1/2Vdc or −1/2Vdc , the load connection has no switch state that discharges the upper capacitor with the
effect on the capacitor voltages. maximum voltage and charges the lower capacitor with the
minimum voltage.
When pole a is attached to the zero level, the upper
capacitors always charge during the positive half of the load The voltage balancing strategy based on (i)–(iii) is
current (ia . 0), whereas the lower capacitors discharge. implemented within the modulator; the instants at which
During the negative half of the load current (ia , 0) the the switching from one combination to another occurs is
upper capacitors discharge whereas the lower capacitors based on the voltage level across each capacitor in the structure.

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Figure 3 Possible load connection to zero voltage level in a three-level modular inverter
a 1010
b 0110
c 0101
d 1001

2.4 Five-level capacitor voltage balancing These two switch states have no influence on the capacitor
method voltages.

In the five-level modular inverter shown in Fig. 1c, there are 70

switch states for each phase. These can be used collectively to The voltage levels +1/4Vdc can be produced by 32
generate a five-level waveform in each phase of the inverter. different switch combinations, whereas the zero
The voltage levels 1/2Vdc and −1/2Vdc can be synthesised by voltage level can be synthesised by 36 different switch
switch combinations 11110000 and 00001111, respectively. combinations.

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Table 3 Effect of redundant switch states of three-level to sort the capacitors according to their voltage magnitudes
modular inverter on capacitor voltage and to determine which switch combination is to be selected.

Switch Load current Effect on The five-level capacitor voltage balancing strategy is as
states capacitors voltages follows: The switch combinations that produce voltage
Direction Path
levels +1/4Vdc , 0 and −1/4Vdc affect capacitor voltage
(A) 1010 ia . 0 Sa1Dx2 and C2  and C4  balance. Therefore any capacitor voltage balancing strategy
Sx4Da3 must utilise these switch states to balance the capacitors.
ia , 0 Sx2Da1 and C4  and C2  The capacitor voltage balancing strategy of a five-level
Sa3Dx4 modular inverter can be divided into three parts.

(B) 0110 ia . 0 Sa2Dx1 and C1  and C4  The first part deals with the imbalance created when the
Sx4Da3 phase output is connected to voltage level +1/4Vdc . When
ia , 0 Sx2Da1 and C4  and C1  the phase current is positive, ia . 0, the switch state is
Sa3Dx4 selected that corresponds to one capacitor from the upper
group of four capacitors with the minimum voltage to be
(C) 0101 ia . 0 Sa2Dx1 and C1  and C3  charged and three capacitors from the lower group of four
Sx3Da4 capacitors with the maximum voltage to be discharged.
ia , 0 Sx1Da2 and C3  and C1  When the phase current is negative, ia , 0, the switch
Sa4Dx3 combination is selected that corresponds to one capacitor
from the upper group of four capacitors with the maximum
(D) 1001 ia . 0 Sa1Dx2 and C2  and C3  voltage to be discharged and three capacitors from the lower
Sx3Da4 group of four capacitors with minimum voltage to be charged.
ia , 0 Sx2Da1 and C3  and C2 
Sa4Dx3 The second part deals with correcting the voltage
imbalance because of the connection of the output phase to
 represents charging state and  represents discharging the zero voltage level. When ia . 0, the switch state is
state selected that corresponds to two capacitors from the upper
group of four capacitors with the minimum voltage to be
The 16 switch states that produce the +1/4Vdc voltage charged, and two capacitors from the lower group with the
level charge (or discharge) one capacitor from the four maximum voltage to be discharged. When ia , 0, two
upper capacitors and discharge (or charge) three capacitors capacitors from the upper group of four capacitors with the
from the lower four capacitors, depending on the phase maximum voltage are selected to be discharged and two
current direction. For example, when ia . 0 the switch capacitors from the lower group with the minimum voltage
state 01111000 charges C1 and discharges C6 , C7 and C8; are selected to be charged.
when ia , 0, C1 discharges and C6 , C7 and C8 charge.
The third part of the balancing strategy deals with
The 16 switch states that produce the voltage level eliminating the voltage imbalance created by connecting the
−1/4Vdc will charge (or discharge) three capacitors from output phase to the −1/4Vdc voltage level. When the phase
the four upper capacitors and discharge (or charge) one current is positive, ia . 0, the switch state is selected that
capacitor from the lower four capacitors, depending on the corresponds to three capacitors from the upper group of four
phase current direction. For example, the switch state capacitors with the minimum voltage to be charged and one
00010111 charges C1 , C2 , C3 and discharges C5 when capacitor from the lower group of four capacitors with the
ia . 0, whereas it discharges C1 , C2 , C3 and charges C5 maximum voltage to be discharged. During negative phase
when ia , 0. current, ia , 0, the switch state is selected that selects three
capacitors with the maximum voltage from the upper group
The switch combinations that produce the zero voltage level of four capacitors to be discharged and one capacitor from
charge (or discharge) two capacitors from the upper group and the lower group with the minimum voltage to be charged.
two from the lower group, depending on the phase current
direction. For example, when ia . 0 the switch state The inductances L shown in Figs. 3, 6 and 7 have the role of
11000011 charges capacitors C3 , C4 and discharges C5 , C6; limiting the inrush currents created during the balancing
when ia , 0 capacitors C3 , C4 discharge and C5 , C6 charge. process as a result of limited voltage imbalance between the
Therefore the cell capacitors can be balanced by proper cell capacitors, and the circulating currents created between
selection of the switch combinations. the phases when the converter supplies unbalanced loads and
during operation with asymmetrical faults, such as, a single-
The capacitor balancing strategy for a five-level modular phase fault and two-phase open-circuit or short-circuit
inverter is similar to that of a three-level modular inverter, faults. These inductances also limit the dc fault currents
except that more sophisticated software overhead is needed flowing in the switching devices, as in current source

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Figure 4 Phase voltage, line voltage and load current, modulation index m ¼ 0.9, load power factor 0.8 lagging
a Phase voltage referred to 0 and its spectrum
b Line-to-line voltage and its spectrum
c Load currents

converters. This means the modular converter can be made The objective is to demonstrate the performance of three-
shoot-through proof, by increasing the dc link inductances. level and five-level modular inverters for high-voltage, high-
power applications (including applications where non-zero
real power exchange is required), by simulation at different
3 Simulation results modulation indices and load power factors. The quality
of the output voltage waveform and capacitor voltage
The results presented in this section are obtained from three- balancing are evaluated.
level and five-level modular inverters simulated in Simulink.
Carrier-based sinusoidal PWM and an embedded capacitor
balancing strategy are used to control the switching devices
3.1 Case I: three-level modular inverter
of the inverter in order to generate the desired output A three-level modular inverter is considered with a dc link
phase voltage and force the capacitor voltages to maintain voltage of 2 kV and 2200 mF cell capacitors. Fig. 4 shows
their set points. The switching frequency is 2.1 kHz. the phase voltage and its spectrum, line-to-line voltage and

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& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-pel.2009.0184
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its spectrum, and three-phase currents with a modulation To evaluate the effect of load power factor on
index of m ¼ 0.9 and 0.8 lagging load power factor. The capacitor voltage balance, a modulation index of 0.9 is
placement of the carrier harmonic components and their used at different load power factors, as shown in Fig. 5a.
sidebands in the phase and line-to-line voltages are Capacitor voltage balancing in multilevel inverters is
identical to those of a three-level diode-clamped converter, usually more difficult at higher modulation indices
when both converters are controlled using phase disposition and power factors. This figure shows that voltage balance
PD carriers. of the cell capacitors of the three-level modular

Figure 5 Effect of power factor and modulation index on voltage balance of cell capacitors (voltage across the capacitors of
the phases b and c are identical to a)
a Effect of power factor on voltage balance of cell capacitors
b Effect of modulation index on voltage balance of cell capacitors

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Figure 6 Phase voltage, line-to-line voltage and load currents when modulation m ¼ 0.9 and load power factor ¼ 0.8
lagging
a Phase voltage referred to 0 and its spectrum
b Line-to-line voltage and its spectrum
c Load currents

converter can be maintained independent of the load power † The voltage stress on the switching devices can be
factor. maintained at 1/2Vdc for all power factors and over the
linear range of modulation indices, that is, regardless of
The effect of modulation index on capacitor voltage output voltage magnitude.
balance is also investigated by considering a load power
factor of 0.8 at different modulation indices. Fig. 5b shows † The quality of the output voltage waveform can be
that capacitor voltage balance of the three-level modular maintained over a wide range of operating conditions.
converter can be achieved over the entire linear range of
modulation indices, 0– 1.
3.2 Case II: five-level modular inverter
Therefore based on Figs. 5a and b, the following A five-level modular inverter with a dc link voltage of 2 kV
conclusions can be drawn for the three-level modular inverter: and 2200 mF cell capacitors is considered. Fig. 6 shows the

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Figure 7 Effect of power factor and modulation index on voltage balance of cell capacitors
a Effect of load power factor on voltage balance of the cells capacitors
b Effect of modulation index on voltage balance of cell capacitors

phase voltage and its spectrum, line-to-line voltage and its results shown in Fig. 7a demonstrate that capacitor voltage
spectrum and output currents when the five-level modular balance in a five-level modular inverter is not dependent on
inverter is operated with a modulation index of 0.9 and a the load power factor, as is the case with the five-level
load power factor of 0.8. The line-to-line voltage total diode-clamped converter.
harmonic distortion and voltage stress on switching devices
for the five-level inverter is half that of the three-level The effect of the modulation index on capacitor voltage
inverter. The harmonic distribution of the phase and line- balance in a five-level modular inverter is also investigated
to-line voltages is identical to the five-level diode-clamped by considering a load power factor of 0.8, at different
inverter with PD carriers. values of modulation indices. The objective is to examine
whether the voltage balance of the cell capacitors depends
The effects of load power factor and modulation index on on voltage magnitude, as is the case of the diode-clamped
capacitor voltage balance of a five-level modular inverter are inverter with more than three levels.
evaluated. To show the effect of load power factor on
capacitor voltage balance, a modulation index of m ¼ 0.9 at Fig. 7b shows that capacitor voltage balance of a five-level
different load power factors is considered. In the case of modular inverter can be maintained over the linear range of
zero power factor leading, small inductance is included in modulation indices (0–1), the voltage stress on each switching
the load circuit to attenuate the switching frequency device in the structure is maintained at 1/4Vdc , and low
components. That is, the load has a leading power factor at output voltage dv/dt and total harmonic distortion can be
50 Hz but is inductive at the switching frequency. The achieved regardless of the modulation index and power factor.

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Figure 8 Voltages across cell capacitors of the three phases, load current during unbalanced condition

Figure 9 Key waveforms demonstrating fault ride through capability of the modular converter during symmetrical and
asymmetrical faults
a Load currents and capacitor voltages obtained during single-phase open-circuit fault at phase c with duration of 200 ms
b Load currents and capacitor voltage obtained during solid three-phase fault with duration of 200 ms

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Figure 10 Currents and capacitor voltages during dc link voltage ramping down from 2000 to 100 V then up to 2000 V
a Load current
b Voltage across dc link capacitors

3.3 Case III: five-level modular inverter- switching devices voltage ratings, a three-phase load with
unbalanced load +40% impedance imbalance is connected to a five-level
modular inverter (Ra ¼ 10, Xa ¼ 7.5, Rb ¼ 0.6 × Ra ,
To demonstrate that modular converters are able to operate Xa ¼ 0.6 × Xa , Rc ¼ 1.4 × Ra and Xc ¼ 1.4 × Xa) while
continuously with an unbalanced load, without exceeding the modulation index is 1.0 pu.

Table 4 Comparison between methods A and B

Method A Method B
requires the reference voltage for the cell capacitors to be does not require any external reference voltage for the cell
specified externally capacitors, instead it distributes the whole dc link voltage
equally across the cell capacitors of the upper and lower
arms
requires the knowledge of the dc link voltage, cells capacitor only requires the knowledge of the cell capacitor voltages
voltages and two arms currents (magnitude and polarity) in and phase current polarity
each phase. However, the practical measurement of arm
current is increasingly difficult, especially in high voltage
applications
increases the switching frequency per cell significantly reduces the effective switching frequency per cell by factor
(switching frequency per cell is equal to the carrier frequency) of 2/M (1/4fc for five-level), whereas the overall switching
and increases overall switching frequency by factor of M frequency is equal to the assigned carrier frequency (see
(overall switching frequency ¼ Mfc), where M is the number Figs. 4a and b)
of cells per phase and fc is the carrier frequency (see Table I
in [16])
relies on complex control loops with feed-forward plus phase relies on phase voltage redundancy and polarity of the
shifted carriers PWM strategy to maintain cell capacitor phase current to maintain cell capacitor voltage balance.
voltage balance This method is independent of carrier arrangement.
However, phase disposition (PD) carrier is favoured over
others because of superior harmonic performance in terms
of harmonic placement and pulse placement within each
carrier cycle
depends on the capacitor voltages and circulating currents depends on phase voltage redundancy and phase current
loops to produce the reference modulating signals. It may polarity to maintain cell capacitor voltage balance,
survive symmetrical three-phase faults as all phases will see independent of the reference modulating signals. Capable
the same capacitor voltages and circulating currents. But its of riding through any ac faults, including symmetrical and
ability to survive asymmetrical faults is in doubt. Because it asymmetrical faults as demonstrated in Figs. 9a and b
may produce asymmetrical output voltages during
asymmetrical faults since each phase will see different values
of circulating currents and capacitor voltages over full
fundamental period

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Fig. 8 shows load currents and voltages across the 4 Conclusions

capacitors forming the three phases. The capacitor voltages
remain balanced, independent of the load, whether The operating principle, carrier-based PWM and capacitor
balanced or unbalanced. voltage balancing strategy for three-level and five-level
modular inverters have been discussed. The modular
multilevel inverter is superior to the diode-clamped multilevel
3.4 Case IV: five-level modular inverter – inverter in the following sense:
fault ride-through capability
In order to evaluate the fault ride-through capability of a five- 1. Capacitor voltage balance can be attained for any number
level modular converter, a single-phase open-circuit fault is of levels, independent of modulation index and load power
introduced on phase c, with a 200 ms duration. The results factor and unbalance.
obtained are presented in Fig. 9a, where voltage balance of
all cell dc capacitors is maintained. The capacitor voltage 2. Unlike a diode-clamped multilevel converter [22], each
deviations in the three phases are maintained within tight switching device is used for equal periods of time.
limits during the fault despite the duration of the fault.
3. In steady state each cell capacitor is operated for T/
The results in Fig. 9b are obtained when the five-level (n 2 1), where T is the fundamental period and n is the
modular converter is subjected to a solid three-phase fault number of levels. Therefore with an increased number of
at the load terminals. A resistance of 1 V and an inductive levels, each capacitor will be used for a small fraction of the
reactance of 0.75 V are introduced between the load fundamental period, which allows the use of smaller
(RL ¼ 10 V and XL ¼ 7.5 V) and converter terminals to capacitance (reducing the cost).
act as a filter to attenuate the switching frequency
components. The capacitor voltage deviations in the three 4. In the modular multilevel inverter, the number of switches
phases are maintained but with relatively large voltage conducting is twice that in a conventional multilevel inverter,
ripple around the desire reference voltage. This is because thus its conduction losses are higher. The switching losses are
of the large inductive voltage drop because of the large fault the same or less, because of the low effective switching
current. This case demonstrates the resilience of the frequency, fc/2(n 2 1), where fc is the carrier frequency.
modular converter under such an extreme case and reflects
a real fault scenario. In a practical system, the modular 5. Extremely low total harmonic distortion can be achieved,
converter current controller will limit the converter switch if a large number of levels are used.
currents to an acceptable level.
6. It has fault tolerance and ride through capability. For a
The ability of the modular converter to maintain cell large number of levels, failure of one or a few switching
capacitor voltage balancing during unbalanced operation devices will not significantly affect circuit operation, unless
and faults (including symmetrical and asymmetrical faults) operated at a higher modulation index. In this case, one
arises from the existence of circulating currents between the voltage level is lost per lost cell, but the system can be shut
phases. These currents accelerate capacitor voltage recovery. down safely. The modular multilevel converter is capable of
riding through faults and capacitor voltage balance is able
3.5 Case V: five-level modular inverter – to recover before the fault is cleared. Neither approach
startup/shutdown offers dc fault protection in an ac/dc mode.

Fig. 10 shows the case when the dc link voltage is ramped 7. It has phase voltage redundancy, which makes the
up and down in order to demonstrate the ability of the capacitor balancing strategy simpler than for the diode-
proposed balancing method to operate without external clamped converter, which has only line-to-line redundancy.
dc voltage references during converter startup and shut
down. The results presented confirm that the modular 8. Fully modular structure.
converter does not require special circuitry to charge
and discharging the dc link capacitors before starting
in order to reduce the risk of inrush current and after 5 References
shutdown.
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doi: 10.1049/iet-pel.2009.0184 & The Institution of Engineering and Technology 2010