CHAPTER-1

INTRODUCTION
1.1 Introduction
MOST industrial processes need to increase efficiency and reduce production costs.
This is achieved by increasing the size of installations and increasing the power of all
electrical machines and equipment. This increase in power is reached in two ways: 1) by
developing high-voltage semiconductors with voltage blocking capabilities of 3300,
4500, and 6500 V and 2) by developing a multilevel inverter. The MV drives cover
power ratings from 0.4 MW to 40 MW at the medium voltage level of 2.3 kV to 13.8 kV.
However, the majority of the installed MV drives are in the 1- to 4-MW range with
voltage ratings from 3.3 kV to 6.6 kV.

For a medium voltage grid, it is troublesome to connect only one power

semiconductor switch directly. As a result, a multilevel power converter structure has
been introduced as an alternative in high power and medium voltage situations. A
multilevel converter not only achieves high power ratings, but also enables the use of
renewable energy sources. Renewable energy sources such as photovoltaic, wind, and
fuel cells can be easily interfaced to a multilevel converter system for a high power
application. Highly popular are the voltage-source multilevel inverters, which can be
divided into three categories, according to their topology: neutral point clamped (NPC),
flying capacitor (FLC), and cascade H-bridge. Their topologies are discussed in next
chapter.

Multilevel inverters generate sinusoidal voltages from discrete voltage levels, and
pulse width-modulation (PWM) strategies accomplish this task of generating sinusoids of
variable voltage and frequencies. Several techniques for the implementation of PWM for
multilevel inverters have been developed. The two main techniques of PWM generation
for multilevel inverters are sine-triangle PWM (SPWM) and space vector PWM
(SVPWM). Multilevel SPWM involves the comparison of a reference signal with a
number of level shifted carriers to generate the PWM signal [6]. SVPWM involves
synthesizing the reference voltage space vector by switching among the three nearest

1
voltage space vectors [1-5]. SVPWM is considered a better technique of PWM
implementation, owing to its associated advantages as follows: 1) better fundamental
output voltage; 2) better harmonic performance; and 3) easier implementation in digital
signal processor and microcontrollers.

In this thesis, Conventional and some advanced SVPWM techniques of a two-

level inverter were studied [9]. Carrier based PWM techniques for 3-level NPC and 5-
level CHB inverter were dealt [6]. Generalized SVPWM algorithm for multi-level
inverter was studied [1] and was implemented on 3-level NPC and 5-level CHB inverter.

1.2 Objective of the project

The main objective of the project is
1. Study and implementation of various PWM techniques on multi-level inverters
(two-level H-bridge, three-level NPC, five-level CHB configurations) using
MATLAB simulation.
2. Hard ware implementation of various PWM techniques on a two-level inverter
using D-SPACE controller.
1.3 Thesis Organisation
This thesis is comprised of seven chapters.
Chapter 1 is an introduction including the thesis outline.

Chapter 2 deals with two level voltage source inverter and multi-level inverter topologies.

Chapter 3 deals with the various Modulation techniques

Chapter 4 deals with Conventional and Advanced SVPWM techniques for a 2-level VSI.

Chapter 5 deals with Generalized SVPWM algorithm for an n-level inverter, its
implementation for three and five level inverter, and Carrier based PWM for three and
five level inverters.

Chapter 6 gives SIMULINK implementation of all the above techniques, D-SPACE

implementation of PWM techniques for a two-level inverter and conclusion.

Chapter 7 gives the conclusion of the project.

2
 CHAPTER-2
MULTI-LEVEL VOLTAGE SOURCE INVERTERS
2.1 Two level inverter
The primary function of a voltage source inverter (VSI) is to convert a fixed dc
voltage to a three-phase ac voltage with variable magnitude and frequency. But the output
voltage will not be a pure sinusoidal wave form; instead we obtain a stepped wave form.
The number of steps in the output voltage will be dependent on ‘level’ of the inverter. By
controlling the switching action of switches connected to the DC source we obtain a
stepped ac voltage from fixed DC voltage.

The basic three phase two level inverter with switches is shown in Fig. 2.1. Each
leg of the inverter consists of a single pole double throw switch. To realize such a switch
practically we connect two unipolar bi-directional switches (such as IGBT with anti-
parallel diode) in series as shown in Fig. 2.1. So final two-level VSI is composed of six
active switches, with a free-wheeling diode in parallel with each switch.

Terminal voltage measured w.r.t capacitor’s midpoint ‘O’ (VRo) is called the pole
voltage. In a two-level inverter, pole voltage takes only two values +0.5Vdc, when upper
switch is ON and -0.5Vdc, when lower switch is ON. So the level of the inverter will be
determined by the number of pole voltage levels

Fig. 2.1 Two-level inverter realization

3
2.2 Multi-level inverters
As discussed before output voltage of an inverter is not pure sinusoidal. Stepped
output voltage contains certain fixed voltage levels. So as the number of voltage levels
increases, the output voltage waveform approaches more closely to sinusoidal waveform.
So we prefer multi-level inverters which will have output voltage levels greater than 2
levels. The general concept of multi-level inverters involves utilizing a higher number of
active semiconductor switches to perform the power conversion in small voltage steps.

Major advantages of a multi-level inverter are as follows

1. Better output waveforms compared to two-level inverters.

2. For high DC bus voltages switches of normal voltage rating can be used.
3. Lower amount of harmonics

4. Stress on the load reduces.

There are also certain inherent disadvantages for multi-level converters. As the
number of switches increases, the gate drive circuits are necessary for each and every
switch. This increases the complexity and the cost of MLI despite of reduction in cost due
to usage of low voltage rating switches. The Fig. 2.2 shows output line voltages of two
and three level inverters with fundamental sinusoidal component. We can observe 3 level
output voltage is closer to sinusoidal waveform.

Fig. 2.2 Two and Three level inverters line voltage waveforms

4
 Two-level inverter uses a single pole double throw (SPDT) switch in each leg.
Similarly multi- level inverter uses single pole multiple throw switch in each leg as
shown below in Fig. 2.3 a. Three level inverter uses single pole triple throw switch (Fig.
2.3 b) where as an n-level inverter uses a single pole n-throw switch (Fig. 2.3 c).

Fig. 2.3 Multi-level inverter switches

There are various configurations of multi-level inverters of which three

configurations are mostly used. They are mentioned below.

1. Neutral point clamped multi-level inverter

2. Capacitor clamped multi-level inverter
3. Cascaded H-bridge multi-level inverter

2.2.1 Neutral point clamped MLI

Basic three level mli using a SPTT switch in each pole is shown in Fig. 2.4. It
must be realized by using 3 power electronic switches. We observe that switches between
terminals R,T1 & R,T3 should be unipolar and bidirectional switches while between
R,T2 should be bipolar bidirectional switch. So replacing SPTT with power electronic
switches with above properties, primary circuit is shown in Fig. 2.4.

5
 Fig. 2.4 Three-level NPC inverter realization

Switches at T1 & T3 blocks voltage Vdc while switch at T2 blocks voltage

0.5Vdc. so during designing all switches are designed with blocking voltage of 0.5V dc. so
at terminals at T1 & T3 two switches will be connected in series. Also at T2 voltage will
be blocked by diodes only. So the two transistors can be removed and the diodes will be
connected at the junctions of S1 & S2, S3 & S4 as shown in Fig. 2.21c which is the final 3
level NPC multi- level inverter. The various switching states of 3 level NPC MLI are
given in table 2.1

Table 2.1 Three-level NPC inverter switching states

Pole voltage(VUO) Switches ON(remaining OFF)

0.5VDC S1U , S2U
0 S3U , S2U
-0.5VDC S3U , S4U

In 3 level inverter switches S1 & S3, S2 & S4 are always complementary to each
other. As the number of levels increases, number of clamping diodes also increases. An
n-level inverter needs (n-1)*(n-2) clamping diodes. So this becomes a disadvantage as the
number of levels increases. Also switches S3, S2 conduct for more time than S1, S4 which
results in unequal switching losses which is also a disadvantage.

6
 Fig. 2.5 Three-level NPC inverter

2.2.2 Capacitor clamped MLI

The 3 level MLI can also be realized using another circuit which includes 3
capacitors and 3 switches as shown below in Fig. 2.6. From Fig. if S1 & T1 are ON pole
voltage is 0.5Vdc. If S2 & T2 are ON pole voltage is -0.5Vdc. If either S1 & T2 or S2 & T1
are ON then pole voltage becomes zero. Also switches S1 & S2 are unipolar bidirectional
switches and switch T is a single pole double throw switch. So mechanical switches are
replaced with power electronic switches of above mentioned characters and are shown in
Fig. 2.6.

Fig. 2.6 Capacitor clamped inverter realization

7
 Table 2.2 Capacitor clamped inverter switching states

Pole voltage(VRO) Switches ON

0.5VDC S1 , S3
-0.5VDC S4 , S2
Zero S2, S3 or
S1 , S4

Here capacitor is clamped to a point whose voltage is not fixed. So capacitor is

called as a flying capacitor and inverter is also called as flying capacitor clamped
inverter. As the number of levels increases the number of clamped capacitors and the DC
capacitors also increases. For an m-level inverter (m−1)*(m−2)/2, (m−1) clamped
capacitors and DC capacitors are required. Charging of all capacitors to the same voltage
leads to complex start up. Cost and space required increases with increase of levels.
Voltage unbalance problem causes distortion in load current and it must be tackled with
proper use of redundant states.

2.2.3 Cascaded H Bridge MLI

Single phase H-bridge is shown in Fig. 2.7. Various line voltages possible by
different switching actions are also shown in table 2.3. We observe that zero voltage is
caused by two different switching states. Such states which cause the same output voltage
are called Redundant states. Proper selection of such redundant states helps to get a better
quality waveform and also lower switching losses.

In cascaded H- Bridge MLI, several of such H bridges will be cascaded to form a

single leg of a three phase MLI. The pole voltage then equals the sum of the voltages of
individual H bridges. If n- bridges are cascaded in a leg then it forms a (2n+1) level
inverter. A five level CHB multi-level inverter is shown in Fig. 2.8. It contains 2 H-
Bridges. The five voltage levels possible by different switching states are shown in table
2.4.

8
 Table 2.3 Single H-Bridge switching states

VAB Switches ON
Vdc S1, S2
- Vdc S3, S4
Zero S1, S3 or
S2, S4

Fig. 2.7 Single H-Bridge

Fig. 2.8 Five-level CHB inverter

9
 Table 2.4 Five-level CHB inverter switching states

VAN S11 S31 S12 S32 VH1 VH2

(VH1+VH2)
2E 1 0 1 0 E E
E 1 0 1 1 E 0
1 0 0 0 E 0
1 1 1 0 0 E
0 0 1 0 0 E
0 0 0 0 0 0 0
1 1 1 1 0 0
0 0 1 1 0 0
1 1 0 0 0 0
1 0 0 1 E -E
0 1 1 0 -E E
-E 0 1 1 1 -E 0
0 1 0 0 -E 0
0 0 0 1 0 -E
1 1 0 1 0 -E
-2E 0 1 0 1 -E -E

The CHB MLI is very simple in its operation. But the disadvantage is that it
requires separate DC sources for every H Bridge. As the levels increase harmonics
decreases. But it is observed that the harmonic reduction is prominent only up to 7 levels.
For higher level CHB inverters harmonic reduction became less observable. There have
been studies showing that the cascaded multi-level inverter is most efficient for low
voltage renewable energy sources.

10
 CHAPTER-3
MODULATION TECHNIQUES

3.1 Classification

Inverter control involves controlling the magnitude and the frequency of the
output voltage according to our purpose. This is achieved by controlling the switching
action of the inverter switches. These techniques which are used to regulate the output
voltage are called as modulation techniques. Various types of modulation techniques are
in existence. Among them the most commonly used ones are mentioned below.

modulation
techniques

staircase carrier based pulse space vector pulse

modulation width modulation width modulation

3.2 Staircase modulation

This type of modulation technique [8] is generally used for cascaded H bridge
MLI. This can be termed as a normal modulation technique and is similar to the square
wave operation of two-level inverter. In this technique switches will be fired at some
pre calculated angles. Angles will be calculated based on some criteria like
minimization of THD or complete elimination of some lower order harmonics.

11
 Consider a seven level inverter made of 3 H-bridges as shown in Fig. 3.1. Vh1,
Vh2, Vh3, are the output voltages of individual bridges and are shown in Fig. 3.1. So
pole voltage will be a seven level wave form as shown in Fig. 3.1

Fig 3.1 Pole of Seven level CHB and pole voltage waveform

Consider bridge-1. It should be operated in such a way that its output is E from
to ( − ). In the similar way other bridges should also be operated. Fourier series
expansion for above pole voltage is given by

= ∑ , , {(cos n + cos n + cos n ) sin nωt} (3.1)

Here in angle calculation we take complete elimination of lower order harmonics in

to account. For a CHB MLI with n-bridges n-angles must be calculated to eliminate (n-1)
lower order harmonics. So for 7-level inverter above , , must be calculated to
eliminate two lower order harmonics i.e. 5th, 7th harmonics. From eq. 3.1 we can write

Cos + cos + cos =ℎ (3.2)

12
 Cos 5 + cos 5 + cos 5 =0 (3.3)

Cos 7 + cos 7 + cos 7 =0 (3.4)

= is called modulation index

4
ℎ∗

VAN1 – Peak value of required fundamental voltage

h - Number of cascaded bridges in each leg

E - Each bridge DC voltage

The above 3 equations will be solved used some optimization techniques or NR method
and the values of angles can be obtained.

3.3 Carrier based PWM techniques

This is the most commonly used modulation technique for all types of multi-
level inverters. Width of the pulse generated in normal operation will be controlled in
this technique, and hence called as pulse width modulation. This technique involves
the comparison of a reference wave with that of a carrier wave. Reference wave should
be similar to our desired output waveform. Generally reference wave will be a
sinusoidal wave and carrier waves will be triangular waves. So this is also called as
sine – triangular PWM .

For a 2-level inverter only one carrier wave is required, while for MLIs more
than one carrier wave is required. An n-level MLI needs (n-1) carrier waves. Two
parameters amplitude modulation index (ma) and frequency modulation index (mf) are
defined here which control the magnitude and frequency of the output voltage.

peak to peak value of the refernce wave

Ma = (3.5)
(n−1)∗peak value of carrier wave

Mf = (3.6)

13
 For multi-level inverters carrier waves can be phase shifted or level shifted. In
level shifted PWM carriers will be level shifted by a certain level [6,8]. Based on the
phase difference between adjacent carrier waveforms these are mainly classified into 3
types. They are

1. In phase disposition(IPD)
2. Phase opposite disposition(POD)
3. Alternate phase opposite disposition(APOD)

In IPD all the level shifted carrier waves will be in phase. In POD carriers
below zero level will be in out of phase with carriers above the zero level. In APOD
adjacent carrier waves will be out of phase. Carrier waves in all the three types are
shown in below Fig. 3.2 for a five level inverter.

Fig. 3.2 Various level shifting PWM techniques

14
 For normal modulation, generally 0 < ≤ 1. In order to increase the voltage
further we go to over modulation mode where ma >1. But harmonics will be increased
in over modulation. So in order to get higher output voltages compared to normal
modulation we go to third harmonic injection.

Third harmonic injection

The inverter fundamental voltage can be increased by adding third harmonic

component to the three phase sinusoidal modulating wave without causing over
modulation. As a result peak of the fundamental component can be higher than the
peak of the triangular carrier which boosts the fundamental output voltage and at the
same time peak of the modulating wave will be kept lower than the peak of the
triangular carrier which prevents over modulation [6]. The fundamental output voltage
can be increased by a maximum of 15.5% by adding (1/6)th of the third harmonic to the
three phase sinusoidal modulating wave. The modulating wave after third harmonic
injection is shown in Fig. 3.3.

Fig 3.3 Third harmonic injection reference wave

3.4 Space vector PWM

In sine triangular PWM as number carrier waves increases with levels, its
practical implementation becomes difficult. So SVPWM technique became more
popular now a days, because of its following features. i) it directly uses the control

15
variable given by the control system, and identifies each switching vector as a point in
complex (α, β) space; ii) it is useful in improving dc link voltage utilization, reducing
commutation losses and THD; and iii) it is suitable for digital signal processing (DSP)
implementation and optimization of switching patterns as well.

SVPWM technique involves representation of three phase quantities as a

rotating reference vector in – plane. So a three phase sinusoidal wave will be
represented as a reference vector which traces a circular locus in – plane. Fig. 3.4
shows three phase vectors and – plane.

Fig 3.4 – plane

Consider balanced system. Then

v +v +v =0

v = v sin

2
v = v sin( − )
3

4
v = v sin( − )
3

v =v + v =v +v +v

2 −2
1 cos cos v
v 3 3
= v
v 2 −2
0 sin sin v
3 3

16
 v = v − (v +v ) ( 3.8)

√
v = (v −v ) (3.9)

= tan v = v +v (3.10)

The position of this reference vector in the – plane determines the

switching states. So the principle of this SVPWM is to generate a rotating reference
vector in the – plane which means that a three phase sinusoidal wave is produced.
In order to implement the SVPWM for multi-level inverters many number of
algorithms are present. In this project, an easy algorithm was used which is based on
two-level implementation of SVPWM. This is discussed in detail in later chapters.

17
 CHAPTER-4
PWM TECHNIQUES FOR TWO-LEVEL INVERTER

A two-level inverter without any PWM control will operate in square wave
mode. But lower order harmonics will be high in this mode of operation. So normal
techniques used to control a two-level inverter are 1. Sine triangle PWM and
2.Specific harmonic elimination (SHE), 3. SVPWM. In this chapter we mainly
concentrate on SVPWM for a two-level inverter.

4.1 Conventional SVPWM for two-level inverter

A two- level VSI is shown in Fig. 4.1. When the upper switch in a leg is ON
pole voltage is 0.5Vdc and when lower switch is ON it will be -0.5Vdc. Lower switch
always will be complimentary of upper switch. So now considering all the three legs
in the inverter, the state when all the upper switches are ON will be indicated by
( PPP ) . The total number of such combinations possible will be 8. Each of such state
gives 8 different values of v , v which can be mapped on a – plane. Such a

diagram which shows all the possible states of an inverter in the – plane can be
called as a state space diagram.

4.1.1 Two-level inverter state space diagram

Eight possible states of a two-level inverter are ( NNN ), ( PPP ), ( PNN ), (

PPN ), (NPN ), ( NPP ), ( NNP ), ( PNP ). v , v in terms of pole voltages is given

by equations

V = (2V −V −V ) (4.1)

√
V = (V −V ) (4.2)

Substituting the pole voltages in eq. 4.1 and 4.2 we observe first 2 states ( NNN ),
( PPP ) gives Vref = 0 and remaining 6 states gives Vref = Vdc. So first 2 states are
called ZERO state vectors and remaining states are called ACTIVE state vectors. For

18
an n-level inverter total number of states possible is given by n3. The state space
diagram for a two level inverter is shown in Fig.4.1. We observe that the space
diagram is divided in to six sectors.

Fig 4.1 Two-level inverter and it’s Space vector diagram

4.1.2 Reference vector generation and dwell times calculation

The eight vectors shown in Fig. 4.1 are stationary. So they are also called
stationary vectors. But we have seen in chapter 3 that the concept of SVPWM is to
generate rotating reference vector. So the reference vector (Vref) we will be
synthesized by using the three nearest stationary vectors. Vref rotates in space with
some angular frequency. The inverter output frequency depends on the speed of
rotation of Vref , and output voltage magnitude depends on the magnitude of Vref.

Let the reference vector V ∠ should be applied for a sampling time Ts. This
is done by applying 3 nearest vectors (2 active vectors and 1 zero vector) for different
times Ta, Tb, T0 such that Ts = Ta+Tb+T0. These time periods are called as DWELL
times. The dwell time calculation is based on ‘volt-second balancing’ principle, that
is, the product of the reference voltage Vref and sampling period Ts equals the sum of
the voltage multiplied by the time interval of chosen space vectors. If Vref is in sector
- 1 then we apply zero vectors for time T0 , POO for Ta and PPO for Tb as shown in

19
 Fig. 4.2. The zero vector has two switching states [PPP] and [OOO], one of which
seems redundant. The redundant switching states can be utilized to minimize the
switching frequency of the inverter or perform other useful functions.

PPO

PPP
POO
OOO

Fig 4.2 Reference vector generation

By volt-balance equation we can write Vref Ts = V1Ta+V2Tb+V0T0 and

V = V ∠0 V = V ∠60 = + +
Solving all these equations we finally get

( )
= (4.3)
√

( )
= (4.4)
√

= − − (4.5)

For all the other sectors generalized formula can be obtained by replacing

→ = − ( − 1)60 ‘K’-sector number

20
Mapping of times Ta , Tb to active vectors in other sectors can be known by rotating the
sector-1 in Fig. 4.3 in anti-clockwise direction by 60 degrees. Active vectors mapped to
Ta, Tb in all sectors is shown in Fig. 4.3.

Fig. 4.3 0, a, b, vectors assignment

4.1.3 Switching sequence design

With the space vectors selected and their dwell times calculated, the next step
is to arrange switching sequence. In general, the switching sequence design for a
given Vvref is not unique, but it should satisfy the following two requirements for the
minimization of the device switching frequency. They are

1. The transition from one switching state to the next should involve only two
switches in the same inverter leg, one being switched on and the other switched
off.
2. The transition for Vref moving from one sector in the space vector diagram to the
next requires no or minimum number of switchings.

21
 The conventional SVPWM uses a SEVEN SEGMENT operation in which the
sampling time TS is divided into 7 parts and three nearest vectors are applied in these
7 time intervals in sequence that satisfies the above two conditions. The Fig. 4.4
shows the seven segment switching sequence and output pole voltage waveforms for
a sampling time period Ts when the reference vector is in sector-1. From the Fig.
following deductions can be made

1. The dwell times for the seven segments add up to the sampling period ( T s =
Ta+Tb+Tc )
2. First design requirement is satisfied. For instance, the transition from [OOO]
to[POO] is accomplished by turning S1 on and S4 off, which involves only two
switches.
3. The redundant switching sates for V0 are utilized to reduce the number of
switchings per sampling period. For the T0/2 segment in the center of the
sampling period, the switching state [PPP] is selected, whereas for the T0/4
segments on both sides, the state [OOO] is used.
4. Each of the switches in the inverter turns on and off once per sampling period.
The switching frequency fsw of the devices is thus equal to the sampling

frequency fsp, that is, fsw = fsp = 1/Ts. Top of the Fig. shows whether the state is a
or b or zero(0) vector.

Fig 4.4 Seven segment operation

22
The table 4.1 shows the switching sequence of seven segment SVPWM for a 2-level
inverter in all the six sectors

Table 4.1 Seven segment switching sequence

Switching segment
Sector 1 2 3 4 5 6 7

1 OOO POO PPO PPP PPO POO OOO

0 a B 0 B A 0
2 OOO OPO PPO PPP PPO OPO OOO
0 b A 0 A B 0
3 OOO OPO OPP PPP OPP OPO OOO
0 a b 0 B A 0
4 OOO OOP OPP PPP OPP OOP OOO
0 b a 0 A B 0
5 OOO OOP POP PPP POP OOP OOO
0 a b 0 B A 0
6 OOO POO POP PPP POP POO OOO
0 b a 0 A B 0
Observation:

It’s not actually necessary to determine the switching states in each sector. It’s
sufficient if we know the sequence and switching states of first two sectors. By
rearranging the states of first two sectors we obtain states of other four sectors as
mentioned in below table 4.2. States of sectors 3, 5 are obtained by rearranging states of
sector 1 and states of sectors 4, 6 are obtained by rearranging states of sector-2 as shown
in table 4.2
Table-4.2 Mapping of sectors-1, 2 states to other sectors

Sector Switching state sector Switching state

1 ABC 2 ABC
3 CAB 4 CAB
5 BCA 6 BCA

23
 4.1.4 Even order harmonic elimination

The output voltage waveform obtained from above SVPWM contains some
amount of even order harmonics. Let’s call the sequence of state vectors followed
above as TYPE-A sequence. Fig.4.5 below shows the pole voltage waveforms for a
sampling time period in sector -4. Sector -4 is exactly 1800 shifted from sector-1. But
the line voltage in Fig.-4.6 is not exactly the mirror image of the line voltage of
sector-1 in Fig.-4.4. So we can say that the line voltage wave form generated by
following above sequence is not HALF WAVE SYMMETRICAL. So it contains
even order harmonics.

Fig. 4.5

TYPE-A sequence begins and ends with [OOO]. Now consider second sequence
called TYPE-B sequence which begins and ends with [PPP] as shown in Fig. 4.6. The
sequence shown in Fig. 4.6 is for sector -4 and we observe that the line voltage wave
form is exactly the mirror image to that of waveform of sector -1 in Fig. 4.4. So in order
to eliminate the even order harmonics, each sector will be sub divided into 2 sectors.
Then TYPE- A&B sequences will be used alternatively as shown in Fig. 4.7.

24
 Fig 4.6

Fig 4.7 ESVPWM sequence selection

So now for even order harmonic elimination 6 sectors are divided totally into
12 subsectors. So from the observation mentioned before its sufficient to determine
the switching states for first 4 sub sectors and by rearranging their switching states we
will know the states of remaining 8 sub sectors. These states and rearrangements are
given tables 4.3 and 4.4

25
 Table 4.3 ESVPWM switching sequence

Sub Segment
sector 1 2 3 4 5 6 7
1 OOO POO PPO PPP PPO POO OOO
0 a B 0 B a 0
2 PPP PPO POO OOO POO PPO PPP
0 b a 0 A b 0
3 PPP PPO OPO OOO OPO PPO PPP
0 a B 0 B a 0
4 OOO OPO PPO PPP PPO OPO OOO
0 b a 0 A b 0

Table 4.4 Subsectors mapping

Sub State Sub State Sub State Sub State
sector sector sector sector
1 RYB 2 RYB 3 RYB 4 RYB
5 BRY 6 BRY 7 BRY 8 BRY
9 YBR 10 YBR 11 YBR 12 YBR

4.1.5 Modulation index

Magnitude of the output voltage depends on the length of the reference

vector. The state space diagram of the inverter is a hexagon. Under normal operation
the locus of the reference vector is a circle which should be lying within the
boundaries hexagon as shown in Fig. 4.8. If the locus crosses the hexagon then it is
termed as over modulation operation. So here we define a term MODULATION
INDEX (mi) which can determine the operation region.

= (4.6)

V1 -peak value of the phase fundamental voltage

26
 = ( − 1) (4.7)

n- Levels of the inverter vdc = DC link voltage on each H-bridge

if mi = 1, then then output voltage will be a six-step waveform and locus of the
reference vector will be circumscribing the hexagon as shown in Fig. 4.8. The
boundary between normal and over modulation will be the circle inscribing the
hexagon as shown in Fig. 4.8. So the region inside the inscribed circle is region of
normal modulation and region between the inscribed and the circumscribed circle is
the region of over modulation.

Fig. 4.8 SVPWM operating modes

At boundary condition length of the reference vector equals the radius if inscribed circle
√
and is given by = = (4.8)

If vm is the peak value of the three phase reference wave, then we know that

= (4.9)

√
From eq. 4.8 & 4.9 =

27
 = (4.10)
√

From eq. 4.6, 4.7 , 4.10 = (4.11)

From 4.10 & 4.11 we get = 0.907 (4.12)

so we say that ≤ 0.907 →

> 0.907 →

=1 →

4.2 Discontinuous SVPWM

In conventional SVPWM discussed before the switching takes place

continuously without being clamped. So CONVENTIONAL SVPWM is also called
CONTINUOUS SVPWM. By changing the switching sequence of conventional
SVPWM, one of the three inverter poles can be clamped to either the positive or
negative dc bus without any switching during the sampling period, Ts. Furthermore,
the switching sequence can be arranged such that the switching in an inverter leg is
continuously suppressed for a period of 1200 or 600 or 300 per cycle of the
fundamental frequency. Due to the switching discontinuity, this type of SVPWM is
also known as DISCONTINUOUS SPACE VECTOR MODULATION. As the
pole voltage will be continuously clamped to a particular DC bus, these techniques
are also called as BUS CLAMPING techniques[9]. Various types of DSVPWM
techniques are shown in Fig. 4.9

28
 DSVPWM

Advanced bus
Bus clamping
clamping

1200 clamp 600 clamp

600 clamp 300 clamp

300 clamp

Fig. 4.9 DSVPWM classification

4.2.1 Bus clamping SVPWM

In the bus clamping SVPWM we use a 5 segment switching sequence. Based

on the period for which pole voltage gets clamped to a particular DC bus, this is
subdivided into 3 types as mentioned above.

4.2.1.1- 1200 clamping

In this type of clamping only one zero state will be used in all the sectors. Two
types of five segment switching sequences used in this type of clamping are shown in
Fig. 4.10. If [OOO] zero state is only used, then each phase gets clamped to negative
DC bus for a period of 1200 per cycle. If only [PPP] zero state is used, then each
phase gets clamped to positive DC bus for a period of 120 o per cycle. So this is called
120o bus clamping SVPWM. The Fig. 4.11 shows states applied in sector 1. Table 4.5
shows switching states in sectors 1&2 and states in sectors 4 to 6 can be known by
mapping given in previous table -4.2

29
 Fig 4.10 Positive and negative bus clamping

Table 4.5 120o clamping sequence

Negative bus clamping sequence

Sector Segments
1 2 3 4 5
1 OOO POO PPO POO OOO
0 A b a 0
2 OOO OPO PPO OPO OOO
0 B A b 0
Positive bus clamping sequence

Sector Segments
1 2 3 4 5
1 PPP PPO POO PPO PPP
0 B a B 0
2 PPP PPO OPO PPO PPP
0 A b A 0

If TYPE-A sequence given above is applied in all sectors, then each sector will
be characterized by clamping of a pole to the negative DC bus as shown in below Fig.
4.12. In the state space diagram given below the states are numbered 0 to 7 for ease of
understanding and the state number is used to denote that particular state. In Fig. 4.12
30
(R-) in sector-1 indicates that R- phase is clamped to negative DC bus. Similarly with the
other sectors also. If TYPE-B sequence given above is applied in all sectors, then each
sector will be characterized by clamping of a pole to the positive DC bus as shown in
below Fig. 4.12.

Fig. 4.12 Positive and Negative bus clamping

If above TYPE-A sequence is used, it causes lower switch to operate for more time
than upper switch. If TYPE-B sequence is used upper switch operates for more time. So
120o clamping results in unequal loading of switches. To operate under equal loading of
switches we must go to 60o or 300 clamping.

4.2.1.2- 600 clamping

In this type of clamping, each sector will be sub divided into 2 sub sectors and
above 2 sequences will be used alternatively in each sub sector. As result of this, each
pole gets clamped to positive DC bus for period of 60 o duration and negative DC bus for
a Period of 60o duration per cycle. So it’s called 60 o clamping. The state sequence applied
in first four sub sectors are given in table 4.7. The state sequences of remaining 8 sub
sectors can be obtained by mapping given in table 4.4. Fig. 4.13 shows how the buses are
clamped for a 60o period by using below given state sequences in all 6 sectors.

31
 Table 4.7 60o Bus clamping sequence

Sub sector Segments

1 2 3 4 5
1 PPP PPO POO PPO PPP
0 B a b 0
2 OOO POO PPO POO OOO
0 A b a 0
3 OOO OPO PPO OPO OOO
0 B a b 0
4 PPP PPO OPO PPO PPP
0 A b a 0

4.2.1.3- 300 clamping

If the switching sequences of the sub sectors in each sector are interchanged, then
we obtain 30o clamping i.e. each pole gets continuously clamped for 300 with both
positive and negative DC buses. But here clamping takes place two times per cycle. The
600 clamping of the previous sequence is now split into two 300 intervals. So this
clamping is also called as SPLIT CLAMPING. Fig. 4.14 shows space vector diagram of
SPLIT clamping sequence. State vector sequence of first 4 sub sectors is shown in table
4.9. switching states of other sectors are obtained by mapping given in before table 4.4

In the BUS CLAMPING since poles gets clamped to one of the DC buses, we can
say that the major advantage of these bus clamping techniques is that there will be
considerable reduction in the switching losses compared to that of conventional SVPWM

32
 Fig. 4.13 60o Bus clamp Fig. 4.14 30o Bus clamp

Table 4.9 30o Bus clamping sequence

Sub sector Segments

1 2 3 4 5
1 OOO POO PPO POO OOO
0 A B a 0
2 PPP PPO POO PPO PPP
0 B A b 0
3 PPP PPO OPO PPO PPP
0 A B a 0
4 OOO OPO PPO OPO OOO
0 B A b 0
.

4.2.2 Advanced bus clamping SVPWM

In conventional SVPWM each pole switches only once during a sub cycle. In this
ADVANCED BUS CLAMPING one pole gets clamped to DC bus, one pole switches
normally once per sub cycle and the other pole switches twice per sub cycle. In this
switching sequence follows again seven segment operation. Advanced bus clamp reduces

33
current harmonics to a high extent at high modulation indices. Two types of sequences
are possible for sector-1, each type of sequence using only one zero state at a time. Two
sequences TYPE-A & TYPE-B are shown in Fig. 4.15 & 4.16 for sector-1.

Fig 4.15
This TYPE-A sequence uses only one zero state [OOO]. We see that B- phase is clamped
to negative DC bus while Y-phase is switched twice per sub cycle.

Fig 4.16

This TYPE-B sequence used only [PPP] zero state. We can see that R–phase clamped to
positive DC bus while Y-phase switched twice per sub cycle.

34
 Table 4.10 Advanced bus clamp 600 sequence

Sub Segment
sector 1 2 3 4 5 6 7
1 PPP PPO POO PPO POO PPO PPP
0.5T0 0.25Tb 0.5Ta 0.5Tb 0.5Ta 0.25Tb 0.5T0
2 OOO POO PPO POO PPO POO OOO
0.5T0 0.25Ta 0.5Tb 0.5Ta 0.5Tb 0.25Ta 0.5T0
3 OOO OPO PPO OPO PPO OPO OOO
0.5T0 0.25Tb 0.5Ta 0.5Tb 0.5Ta 0.25Tb 0.5T0
4 PPP PPO OPO PPO OPO PPO PPP
0.5T0 0.25Ta 0.5Tb 0.5Ta 0.5Tb 0.25Ta 0.5T0

4.2.2.1 60o clamp

Dividing the each sector into 2 sub sectors and using the above 2 types of sequences
in each subsector as given table 4.10, we can clamp a phase to a fixed DC bus for a
period of 60o and at the same time one phase switches twice. Clamped phases and double
switching phase in each sector can be seen in Fig. 4.17. in the Fig. sub sector-1 marked as
R+,Y2 which means in that sub sector-1 R-phase clamped to POSITIVE DC bus and Y-
phase switches twice. Similarly with the other sectors also.

Fig. 4.17 Advanced bus clamp 60o

35
4.2.2.2 -30o clamp

By interchanging the sequences of sub sectors of each sector in 60 o clamp, we

obtain the 300 advance bus clamp. As mentioned before it is also called as SPLIT
clamping. The switching state sequences of first 4 sub sectors are given in table 4.11 and
by rearrangement as per table 4.4, we can get other sub sector’s switching state sequence.
Space vector diagram of this clamping is shown in Fig. 4.18 with clamped and double
switching phases indicated in each sector.

Table 4.11 Advanced bus clamp 300 sequence

Sub Segment
sector 1 2 3 4 5 6 7
1 OOO POO PPO POO PPO POO OOO
0.5T0 0.25Ta 0.5Tb 0.5Ta 0.5Tb 0.25Ta 0.5T0
2 PPP PPO POO PPO POO PPO PPP
0.5T0 0.25Tb 0.5Ta 0.5Tb 0.5Ta 0.25Tb 0.5T0
3 PPP PPO OPO PPO OPO PPO PPP
0.5T0 0.25Ta 0.5Tb 0.5Ta 0.5Tb 0.25Ta 0.5T0
4 OOO OPO PPO OPO PPO OPO OOO
0.5T0 0.25Tb 0.5Ta 0.5Tb 0.5Ta 0.25Tb 0.5T0

Fig. 4.18 Advanced bus clamp 30o

36
 CHAPTER-5

MULTI-LEVEL INVERTERS CONTROL

5.1 SVPWM generalized algorithm for an n-level inverter

Implementation of SVPWM for a 2-level inverter is easy due to small number of

switching states (8). As the number of levels increases, each sector will be again sub
divided into a number of triangles and the number of states in the space vector diagram
also increases. For an n-level inverter each sector contains (n-1)2 triangles and space
vector diagram contains n3 switching states. So as the levels increases SVPWM
implementation becomes complex. Here in this chapter we will discuss a generalized
algorithm based on a 2-level inverter SVPWM. The implementation of this algorithm is
easy compared to other algorithms because of the following salient features.

1. Simple on-time calculation due to the use of a two-level geometry based on-time
equations. The on-time calculation equations for linear and over modulation mode
do not change with the position of reference vector
2. Normally to model the nonlinearity of the over modulation region, the solution to
nonlinear equations or lookup tables are required. But this algorithm doesn’t
require any such solving of nonlinear equations which leads to the simplicity in
the algorithm implementation.
3. All the (n-1)2 triangles in a sector are indicated by a triangle number ∆j which will
be calculated by using a simple algebraic expression. The triangle ∆j makes the
selection of the nearer switching vectors easy.
4. The algorithm can be used for any level (n≥3) without any significant increase in
computations.

5.1.1 Switching states determination in space vector diagram

A simple method to determine the switching states in space vector diagram for inverter of
any level is discussed here [5]. For the explanation purpose, we used sector-1 of five-
level inverter. First each and every vertex of all the triangles should be indicated with 60 o

37
co-ordinates (m,n) . m = 1,2,3…..2p n = 1,2,3…2p where = ‘n’ is the level of

the inverter. Five level inverter space vector diagram with all co-ordinates indicated is
shown in below Fig. 5.1

Fig. 5.1 600 co-ordinates of space vector diagram

Each state vector may contain more than one redundant state. Let the states of three poles
may be denoted by Sa, Sb, Sc. They can take values −( ) …..,-2-1,0,1,2……( )

.For five-level inverter n=5. so switching states can take values -2, -1, 0, 1,2. Switching
states of the secor-1 can be found using m,n,p as given below.

Sa = (m+n-p), (m+n-p+1), (m+n-p+2)……….p (5.1)

Sb= (n-p), (n-p+1), (n-p+2)……….(p-m) (5.2)

Sc= (-p), (-p+1), (-p+2)……….(p-m-n) (5.3)

For eg. Consider zero vector co-ordinates (0,0)and for five-level p = 2.

So we get Sa = -2, -1, 0 , 1, 2 Sb = -2, -1, 0 , 1, 2 Sc = -2, -1, 0 , 1, 2

38
Redundant states of zero vector for a five level inverter are [ -2 -2 -2 ] [ -1 -1 -1] [0 0 0 ]
[1 1 1 ] [ 2 2 2 ]

Similarly consider co-ordinate ( 1,0) . we get

Sa = -1, 0 , 1, 2 Sb = -2, -1, 0, 1 Sc = -2, -1 , 0, 1

So all the redundant states at (1,0) are [ -1 -2 -2] [ 0 -1 -1 ] [ 1 0 0 ] [2 1 1]

Likewise we can get states at all the co-ordinates in the state space diagram. But it’s not
necessary to perform the above calculations in all the 6 sectors. Calculate the states in the
first sector and by performing a simple mapping as shown in table 5.1 we can get states
of other 5 sectors.

Table 5.1 Switching states mapping

Sector Pole –a Pole- b Pole-c

1 Sa Sb Sc
2 -Sb - Sc -Sa
3 Sc Sa Sb
4 -Sa -Sb -Sc
5 Sb Sc Sa
6 -Sc -Sa -Sb

5.1.2 Proposed idea of ON-time calculation for a multi-level inverter

ON-time calculation is based on the two-level inverter calculation [1-2]. Fig. 5.2
shows space vector diagram for sector -1 of a two level inverter.

Fig. 5.2 Two-level space vector diagram sector-1 39

From the Fig. 5.1 ON-times are calculated as

= − (5.4)
√

= (5.5)
√

= − − (5.6)

Fig. 5.3 shows the space vector diagram sector-1 of a five level inverter. Each
sector can be split into 16 triangles ∆j, where j= 0 →15. In this Fig. 5.2, v* is the
reference vector of magnitude |v*| at an angle of with α axis. We now define a small
vector vs , which describes the same point in shifted system ( , ) as shown in Fig. 5.4.
It makes angle with the axis. The volt-seconds required to approximate the small
vector vs in the shifted system should be equal to those required for actual vector v* in
the original system . Hence, we can obtain the on-times for any reference vector by
finding the on-times of respective small vector vs .

Fig. 5.2 Five-level space vector diagram sector-1

40
 Reference taken for new small vector vs depends on the type of triangle. For ease
of calculation, all triangles in the space vector diagram will be categorized as TYPE-A &
TYPE-B triangles. Triangles with base down will come under TYPE-A and those with
base up comes under TYPE-B. The way in which the new small vector vs will be defined
in above two types of triangles is shown in Fig. 5.4 below.

Fig. 5.4 New small reference vector

So for a multi-level inverter we first identify the triangle in which reference vector
is located and then obtain the co-ordinates of small vector , . Since every
triangle of an n-level inverter is analogous to a sector of two-level inverter, ON-time
equations of two-level inverter (5.4-5.6) can be used for an n-level inverter by placing
co-ordinates in equation as , .

5.1.3 Algorithm for sinusoidal modulation mode

As discussed in before chapter if 0 ≤ < 0.907, it is called normal or sinusoidal

modulation mode. In this section we will describe the algorithm for sinusoidal
modulation mode. For a given position of the reference vector, the sector of operation Si
(1 ≤ ≤ 6) and its angle (0 ≤ < 60) within the sector is determined by using (5.7)
and (5.8) respectively

= +1 (5.7)

41
 = (5.8)

Where, (0 ≤ < 360) is the angle of the reference vector with respect to α axis,
‘int’ is standard math function “integer” and ‘rem’ is standard math function
“remainder.”

In sinusoidal mode, the reference vector v* , moves on a circular trajectory with

the tip P of the reference vector located in any of the 16 triangles; △ −△ as shown in
Fig. 5.5. So we must determine the triangle where reference vector is located. The search
for the triangle that has point P can be narrowed down by using two integers k1 and k2 ,
which are dependent on the coordinates , of point P as

= + = (5.9)
√ √

Fig 5.5
K1 signifies part of the sector between lines
+ √3 = √3 + √3 = √3( + 1)

√ √
K2 signifies part of the sector between lines = = ( + 1)

42
 In Fig. 5.5 k1 = 2, signifies the part of the sector between line segments A3A5 and
A6 A9. Similarly k2 =1, signifies the part the sector between line segments A2 A11 and
A5 A12. These two regions are inclined at 120o. Geometrically, the values of k1 and k2,
signify the intersection of these two regions. This intersection can be either a triangle or
rhombus. For the reference vector in Fig. 5.5, the intersection is Rhombus A4 A7 A8A5
where tip of reference is located. This rhombus is made of two triangles ∆ ∆ ,
TYPE-A and TYPE-B triangles. To determine in which triangle reference vector is
located , we calculate new co-ordinates of P , w.r.t. point A4 given by

√
= − + 0.5 = − (5.10)

Comparing the slopes of A4P, i.e ⁄ with the slope of diagonal A4A8 i.e. √3, we can
determine weather the tip of reference vector is in TYPE-A (∆ ) or TYPE-B (∆ )
triangle.

Case -1 ≤ √ , then point P is with in TYPE-A triangle i.e. (∆ ) in Fig. 5.5

and small vector vs is represented by A4P. So we can get

, = , = + (5.11)

Case -2 > √ , then point P is with in TYPE-B triangle i.e. (∆ ) in Fig. 5.5 and
small vector vs is represented by A8P. So we get

√
, = . − , − = + + (5.12)

So having determining the small vector vs , for the reference vector, ON-times

are calculated using equations 5.4 to 5.6

43
5.1.4 Algorithm for over modulation mode

Over modulation mode-1

This region of operation takes place when (0.907≤ mi < 0.9535).This region is
marked by nonlinearity i.e. output voltage doesn’t increase in proportional to mi. In Fig.
5.6, the thick dotted circle shows the desired trajectory of the reference vector v*, which
crossed the hexagonal boundary. Traditionally, depending on the mi, the trajectory is
modified and the tip P of the actual vector moves on trajectory TSA12RQ shown in thick
solid line in Fig. 5.6. First it moves along the circular track TS, then along the linear
track SA12R on the side A10 A14 of the sector-1 and finally along the circular track RQ .
This modification in trajectory is intended to compensate for the loss in volt-secs. The
linear movement along A10 A14 is called hexagonal track.

Let be the angle where the reference vector crosses the hexagon track, shown by the
dotted arrow in Fig. 5.6. For ≤ < − , vector moves on hexagonal track and for

remaining part of sector, on circular track. Using Cartesian geometry, angle is obtained as

.
= − cos (5.13)

Fig 5.6 Over modulation-1

44
Hexagonal portion( ≤ < − )

Co-ordinates of the tip of the vector P in terms of and inverter level ‘n’ is given by

√ ( ) √ ( )
, = , (5.14)
√ √

Like in linear modulation, we define 2 integers k1, k2 as

= − 2, = (5.15)
√

Tip of the vector resides on one of the 4 triangles ∆9, ∆11, ∆13, ∆15. All are of TYPE-A
triangles. So slope comparison is not required here. We can get directly small vector
coordinates as

√
, = − + 0.5 , − (5.16)

get Ta from equation 5.4 and on hexagonal track T0 =0 . so we get Tb = Ts-Ta

Circular portion 0≤ < − ≤ <

Here, on-times are obtained using (5.4)–(5.6) as described before for the linear
mode. However, on-times are modified to compensate for the loss of volt-sec during the
linear trajectory. We calculate a compensating factor and use it for the modification of
ON- times as given below.

. .
= = (5.17)
. . .

Modification for TYPE-A triangles:

= + 0.5 = + 0.5 = − − (5.18)

Modification for TYPE-B triangles:

= − 0.5 = − 0.5 = − − (5.19)

45
For mi = 0.907 , = 0 and no compensation. For mi = 0.9535 , =1 =0
compensation is maximum which corresponds to complete movement along hexagonal
track. Above 0.9535, the circular part of the trajectory vanishes and the on-time t0
obtained from (5.18) or (5.19) is negative which is meaningless. Above 0.9035 we use
another mode called Over-modulation-2

Over modulation mode-2

For (0.9535≤ mi<1), the operation is called as over modulation mode-2. Switching in
over modulation II is characterized by a hold angle , shown by the dotted arrow in Fig.
5.7.

Fig. 5.7 Overmodulation-2

For ≤ < − , the tip P of the vector vp moves on hexagonal track. In

Fig. 5.7, vectors at vertices A10 and A14 are addressed as large vectors. There are a total
of six large vectors for the complete space vector diagram.

For 0 ≤ < − ≤ < , the vector vp is held at one of the large

vectors. Holding angle is given by equation

46
 = 11.26 − 10.74/ (5.20)

For ≤ < − the on-time calculation is same as that during the hexagonal

trajectory in over modulation mode I. For 0 ≤ < − ≤ < , the vector

is held at one of the six large vectors. At mi=1.0, hexagonal track vanishes and vector is
only held at the six large vectors sequentially. This is six-step operation similar to two-
level inverter. Therefore, a multilevel inverter when operated at mi = 1.0, loses its
multilevel characteristics.

The flow chart of the entire algorithm for all modes of the operation is shown in below
Fig. 5.8

47
 Fig. 5.8 Flow chart of MLI SVPWM algorithm

5.1.5 Switching states selection and sequence design

Once the triangle and ON- times ta, tb, t0 are calculated by using the above
algorithm, the next task is to select the switching states and the sequence in which the
states are to be applied [4]. Each vertex of the triangles contain more than one switching
states, and are called as REDUNDANT states. Suitable state from these redundant states
should be selected at each vertex. Also the three nearest selected vectors of the triangle
can be named as 0-vector, a-vector, b-vector. Sequence design here means, to determine
which vector to be applied first and the sequence the 3 vectors 0, a, b should be applied
i.e. 0ab or 0ba or ab0 or ba0 etc.

Triangle vertices designation:

First the three vertices of every triangle should be indicated as 0, a, b vectors. It is

sufficient to indicate for only sector-1 triangles. By rotating the sector-1 about the origin,
we can obtain sectors- 2 to 6. So we can use the designation given to each vertex of
triangles in sector -1 in other sectors also, but the only thing is that sector-1 must be
rotated by 600 about origin in anticlockwise direction to get sector-2 and further rotating

48
sector-2 again by 600 about origin in same anticlockwise direction, we get sector-3.
Likewise we get even other sectors also.

All the triangles can be generalized into two types as described in algorithm
above, TYPE-A and TYPE-B. The below Fig. 5.9 shows how the vertices of both types
of triangles are designated with 0, a, b vectors in sector-1.

Fig 5.9 Vectors designation for triangles in sector-1

So vertices of all the triangles in sector -1 will be designated with 0.a,b vectors
based on their type. Then the states should be applied in anticlockwise direction for
TYPE-A and clockwise direction for TYPE-B triangles. It means if 0-vector is applied
first in sub cycle, then the next vector to be applied should be a-vector and then b-vector
for TYPE-A ( anticlockwise direction application), b-vector and then a-vector for TYPE-
B (clockwise direction application) as shown in Fig. 5.9.

Vector sequence determination:

After designating the vertices of triangles with 0, a, b vectors as described above,

we must determine the vector that must be applied first in a sub cycle and from the
direction rule mentioned above we can easily get the next vectors to be applied. Actually
the sequence applied depends on the type of triangle and the sum of total number of
switching states at the three vertices of a triangle. This sum can be even or odd. For eg.
take the triangle in Fig. 5.10

49
 Fig 5.10

In the above triangle total number of redundant states at all the 3 vertices of
triangle equals to 3+2+2 = 7. So the total number of redundant states is ODD for above
triangle and it is of TYPE-A triangle. So we call the above triangle as TYPE- A odd.
Triangles of this type follow a predefined sequence ‘ab0’ in sub sector-1. We knew that
conventional SVPWM follows 7- segment operation. Sequence ‘ab0’ means that vector-
a1 applied in segment-1 for time 0.25ta , vector-b in segment-2 for 0.5tb time, Vector-0 in
segment 3 for time 0.5t 0, vector a2 for time 0.5ta, and it follows same reverse sequence.
For the vector applied first in the sub cycle, we will use two redundant states of that
vector in 7-segment operation. The above description of sequence ’abo’ is shown in table
5.2 which included time of application of each state. The other sequences also will be
defined in the same manner.
Table 5.2 Sequence ‘abo’ meaning

segment 1 2 3 4 5 6 7
vector a1 B 0 a2 0 B a1
time 0.25ta 0.5tb 0.5t0 0.5ta 0.5t0 0.5tb 0.25ta

So as described above, all the triangles in any sector will be categorized in to four
types based on type of triangle and total number of redundant states. They are

1. TYPE-A EVEN
2. TYPE-A ODD
3. TYPE-B EVEN
4. TYPE-B ODD

50
For conventional SVPWM implementation in MLI each sector will be divided into 2 sub
sectors. So there will be total 12 sub sectors. It’s sufficient to determine the switching
sequence for first four sub sectors and remaining 8 sub sectors (SS) follows the first four
i.e.

Sequence of ( SS- 1 = SS-5 = SS- 9) Sequence of ( SS- 2 = SS- 6 = SS- 10)

Sequence of ( SS- 3 = SS-7 = SS- 11) Sequence of ( SS- 4 = SS- 8 = SS- 12)

So the sequence finally depends on category of triangle and the sub sector. So
the sequence design can be determined from the below table 5.3. The table is framed
based on a rule that ‘the sequence should always start and end at a vertex of the triangle
that contains even number of redundant states’. So sequence in Fig. 5.10 can start from
vector-a or vector-b and it is of TYPE-A triangle. So sequence must be anti-clock. So
triangle in Fig. 5.10 can take ‘ab0’ or ‘b0a’ sequence, which depends on sub sector where
reference vector is present.

Table 5.3 Sequence for various categories of triangles

Sequence
Triangle category Sub sector Normal SVPWM Even harmonic
elimination
1 0ab 0ba
TYPE-A EVEN 2 0ab 0ab
3 0ab 0ab
4 0ab 0ba
1 ab0 a0b
TYPE-A ODD 2 b0a b0a
3 b0a b0a
4 ab0 a0b
1 0ba 0ab
TYPE-B EVEN 2 0ba 0ba
3 0ba 0ba

51
 4 0ba 0ab
1 ba0 b0a
TYPE-B ODD 2 a0b a0b
3 a0b a0b
4 ba0 b0a

Redundant states selection

Proper selection of redundant states at a vertex of triangle reduces the harmonics and
switching losses. This selection is based on the number of redundant states at the vertex
as given below [3-4].

1. If the number of redundancies at a vertex is even, then use two middle

redundancies
2. If the number of redundancies at a vertex is odd, then use the middle one
redundancy

5.2 Three-level inverter control

A three-level NPC inverter is shown in Fig. 5.11. As already discussed in chapter-
2, each pole of the bridge contains 4 IGBTs with antiparallel diodes and the neutral point
will be clamped through 2 other diodes. The 3 states possible are +Vdc, 0, -Vdc.

Fig. 5.11 Three-level NPC

52
5.2.1 Staircase modulation
As described in chapter-3, three-level staircase modulation involves calculation of
only single angle. Harmonic elimination will not be possible in this technique for three-
level, and calculation of angle will be based only on modulation index. The pole voltage
waveform and the pulses to be given to upper two switches of a pole S 1U, S2U are shown
in Fig. 5.12

Fig. 5.12 Pole voltage and gate pulses

From eq. 3.2, described in chapter-3, for 3-level inverter we get

cos = (5.21)

For = 0.9 we get = .

Pulses to S3, S4 will be complementary of S1, S2. Pulses to remaining poles will be phase
shifted by 1200 & 2400.

5.2.2 Carrier based modulation

As described in chapter-3, three-level inverter requires 2 triangular carriers. Only 2

level shifting techniques will be possible for 3-level inverter. They are IPD and POD.
Carriers for both techniques are shown in Fig. 5.13.

53
 Fig. 5.13 IPD & POD carriers

The 2 carrier waves control the switching of upper 2 switches in a pole. The conditions
for switching action are ≥ & ≥ .

In order to further increase the voltage without going into over modulation and for
optimizing the switching action, third harmonic will be introduced into reference signal,
and such techniques are called as switching frequency optimization (SFO) techniques.
The reference signal for SFO techniques is shown in Fig. 5.14.

Fig. 5.14 SFO reference signal

54
So totally 4 different techniques will be possible in carrier based modulation for a 3-level
inverter. They are 1. IPD, 2. POD, 3. SFOIPD, 4. SFOPOD.

5.2.2 SVPWM implementation for three –level NPC inverter

. Voltage levels possible in a 3-level inverter are normalized and represented in

space vector diagram as +1,0,-1. Fig. 5.15 shows the space vector diagram of a 3-level
inverter. As mentioned in before chapter, each sector of a 3-level inverter contains (3-1)2
= 4 triangles each. The total number of states are (n)3 = 33 = 27. All the states are shown
in Fig. 5.15. Of these, 3 states are ZERO states (111, 000, -1-1-1). Remaining 24 are
active states. Of these 6 vectors are long vectors of length 2 PU, 6 vectors are medium
vectors of length √3 PU and 12 vectors are small vectors of length 1 PU.

Using the algorithm described in chapter-5, we can calculate the triangle number
and the ON-times of 3 vctors-0, a, b which will be the vertices of the triangle. Fig. 5.16
shows the designation of vectors 0, a, b to all vertices of 4 triangles as mentioned in
chapter-5.

Fig 5.15 Three-level space vector

55
 Fig. 5.16 0, a, b vectors designation

Switching states and sequence design

Total number of reduntant states of triangle ∆0 = 3+2+2= 7

Total number of reduntant states of triangle ∆1 = 2+1+1 = 4

Total number of reduntant states of triangle ∆2 = 2+2+1 =5

Total number of reduntant states of triangle ∆3 = 2+1+1=4

So in sub sector-1→ TYPE-A even→ ∆1 sub sector-2 → TYPE-A even→ ∆3

TYPE-A odd→ ∆0 TYPE-A odd→ ∆0

TYPE-B odd→ ∆2 TYPE-B odd→ ∆2

So in sub sector-3→ TYPE-A odd → ∆2 sub sector-2 → TYPE-A odd → ∆2

TYPE-B even → ∆1 TYPE-B even → ∆3

TYPE-B odd → ∆0 TYPE-B odd → ∆0

From the table 5.3 switching states applied for every triangle in seven segment
SVPWM is indicated in below table- 5.4

56
Table 5.4 Switching states applied for Seven segment SVPWM

Sub triangle Segments

sector
1 2 3 4 5 6 7
∆0 0-1-1 00-1 000 100 000 00-1 0-1-1
1 0.25ta 0.5tb 0.5t0 0.5ta 0.5t0 0.5tb 0.25ta
∆1 0-1-1 1-1-1 10-1 100 10-1 1-1-1 0-1-1
0.25t0 0.5ta 0.5tb 0.5t0 0.5tb 0.5ta 0.25t0
∆2 0-1-1 00-1 10-1 100 10-1 00-1 0-1-1
0.25tb 0.5ta 0.5t0 0.5tb 0.5t0 0.5ta 0.25tb
∆0 00-1 000 100 110 100 000 00-1
2 0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆2 00-1 10-1 100 110 100 10-1 00-1
0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆3 00-1 10-1 11-1 110 11-1 10-1 00-1
0.25t0 0.5ta 0.5tb 0.5t0 0.5tb 0.5ta 0.25t0
∆0 00-1 000 010 110 010 000 00-1
3 0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆1 00-1 01-1 11-1 110 11-1 01-1 00-1
0.25t0 0.5tb 0.5ta 0.5t0 0.5ta 0.5tb 0.25t0
∆2 00-1 01-1 010 110 010 01-1 00-1
0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆0 -10-1 00-1 000 010 000 00-1 -10-1
4 0.25tb 0.5ta 0.5t0 0.5tb 0.5t0 0.5ta 0.25tb
∆2 -10-1 00-1 01-1 010 01-1 00-1 -10-1
0.25ta 0.5tb 0.5t0 0.5ta 0.5t0 0.5tb 0.25ta
∆3 -10-1 -11-1 01-1 010 01-1 -11-1 -10-1
0.25t0 0.5tb 0.5ta 0.5t0 0.5ta 0.5tb 0.25t0

57
Even order harmonic elimination

In the even order harmonic elimination, we use two types of sequences TYPE-A
and TYPE-B, and use the two sequences alternatively in the sub sectors. TYPE-A
sequence is the normal sequence defined above. Second sequence is obtained by
reversing the direction of above sequence.

TYPE – A – normal above sequence- 01 a b 02 b a 01

In normal sequence we started at 01 vector and then applied a, b vectors. In TYPE-B

sequence we will start at 02 then apply b, a vectors consecutively. So we can say

TYPE – A - 01 a b 02 b a 01

TYPE – B – 02 b a 01 a b 02

Consider triangle shown in Fig. 5.17. TYPE-A and TYPE-B sequence for 7 segment
operation will be as shown in table 5.5. Consider sequence starts at vector –a.

Fig 5.17

Table 5.5 TYPE-B sequence from TYPE-A

Sequence Segments
type 1 2 3 4 5 6 7
TYPE-A 1-2-2 1-1-2 1-1-1 2-1-1 1-1-1 1-1-2 1-2-2
TYPE-B 2-1-1 1-1-1 1-1-2 1-2-2 1-1-2 1-1-1 2-1-1

58
 Fig. 5.18 ESVPWM sequence application in sectors

So the Fig. 5.18 shows how above 2 sequences should be used alternatively in
subsectors for even harmonic elimination. Applying this, the sequence for even
harmonic elimination in first 4 subsectors of 3-level inverter is given in table 5.6

Table 5.6 ESVPWM switching states

Sub triangle Segments

sector 1 2 3 4 5 6 7
∆0 100 000 00-1 0-1-1 00-1 00-0 100
1 0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆1 100 10-1 1-1-1 0-1-1 1-1-1 10-1 100
0.25t0 0.5tb 0.5ta 0.5t0 0.5ta 0.5tb 0.25t0
∆2 100 10-1 00-1 0-1-1 00-1 10-1 100
0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆0 00-1 000 100 110 100 000 00-1
2 0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆2 00-1 10-1 100 110 100 10-1 00-1
0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆3 00-1 10-1 11-1 110 11-1 10-1 00-1

59
 0.25t0 0.5ta 0.5tb 0.5t0 0.5tb 0.5ta 0.25t0
∆0 00-1 000 010 110 010 000 00-1
3 0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆1 00-1 01-1 11-1 110 11-1 01-1 00-1
0.25t0 0.5tb 0.5ta 0.5t0 0.5ta 0.5tb 0.25t0
∆2 00-1 01-1 010 110 010 01-1 00-1
0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆0 010 000 00-1 -10-1 00-1 000 010
4 0.25tb 0.5t0 0.5ta 0.5tb 0.5ta 0.5t0 0.25tb
∆2 010 01-1 00-1 -10-1 00-1 01-1 010
0.25ta 0.5t0 0.5tb 0.5ta 0.5tb 0.5t0 0.25ta
∆3 010 01-1 -11-1 -10-1 -11-1 01-1 010
0.25t0 0.5ta 0.5tb 0.5t0 0.5tb 0.5ta 0.25t0

5.3 Five-level CHB inverter control

A five-level CHB inverter and its possible switching states are already discussed and
tabulated in chapter-2. A 5-level CHB inverter is shown in Fig. 5.19. Here we discuss 3
modulating techniques of 5-level CHB inverter. They are

1. Staircase modulation
2. Sine triangle PWM
3. Space vector PWM

5.3.1 Staircase modulation

The output pole voltage resembles a 5 step staircase. As discussed in chapter-2,

switches of bridge-1 should be fired in such a way that vH1 = +E for period 180 −
and vH1 = -E for period 180 + 360 − and vH1 =0 for remaining cycle. In the
same way bridge-2 must be operated at an angle α2. Switches of the bridge that are ON
for various voltages are given in table 5.7 and pole voltage output wave forms are shown

60
in Fig. 5.20, and the pulses to be given to switches S11, S31, S12, S32 of pole –a or shown in
Fig. 5.21

Fig 5.19 Five-level CHB inverter

Table-5.7 single H-bridge switching states

Voltage (vHn) Switches ON

+E S1n, S2n
-E S3n, S4n
0 S1n, S3n

‘n’- bridge number.

61
Fig. 5.20 Five-level CHB stair case modulation pole voltage

Fig. 5.21 Staircase modulation Gate pulses

62
 Pulses given to lower switches of bridges will be complementary of above pulses.
Pulses given to remaining poles will be phase shifted by 120 o from above pulses.

Calculation of , : from equations of chapter 3, taking mi = 0.9 , we get

Cos + cos =2 = 2 ∗ 0.9 (5.22)

Cos 5 + cos 5 =0 (5.23)

Solving the above 2 equations using Newton Raphson’s method we get

= . = .

Using these 2 values, pulses will be generated and given to switches of the CHB inverter

5.3.2 Sine triangle PWM

To implement SPWM for a 5-level inverter, it requires a three-phase sinusoidal

modulating wave and 4 triangular carrier waves. As already discussed in chapter-2,
carrier waves are generally level shifted. Based on the phase difference between 2
adjacent carrier waves, these are classified into IPD, POD, APOD types. They are shown
in below Fig. 5.22

Fig. 5.22 Carriers of Various SPWMs

63
 The four carrier waves are vcr1, vcr2, vcr2-, vcr1-. Carrier waves vcr1, vcr1- controls

the switching of upper H-bridge and vcr2, vcr2- controls the switching of lower H-bridge.
The conditions for the generation of switching pulses are given below. Let Vm is the
modulating wave.

> → < →

> → < →

In order to further increase the voltage without going into over modulation and for
optimizing the switching action, third harmonic will be introduced into reference signal,
and such techniques are called as switching frequency optimization (SFO) techniques.
The reference signal for SFO techniques is shown in Fig. 5.14. So totally 6 different
techniques will be possible in carrier based modulation for a 5-level inverter. They are
1. IPD, 2. POD, 3.APOD, 4. SFOIPD, 5. SFOPOD.

5.3.3 Space vector PWM

The state of space vector diagram of 5- level inverter contains levels 2, 1, 0, -1, -2.
As it’s a 5-level inverter, each sector contains (5-1)2 = 16 triangles. The total number of
states equal to 53 = 125. There are 5 zero states. The long vectors will be of length 4 PU.
According to the algorithm discussed in chapter-5, triangles will be indicated by ∆0 - ∆15.
Sector-1 of 5-level inverter with all the redundant states is given in Fig. 5.23

States of sector-2 can be obtained by using the mapping table given in chapter-
5. Sector-1 states are [ u v w] , sector-2 states becomes [-v –w –u ]. By applying this
sector-2 states obtained are shown in Fig. 5.24 . Using the algorithm described in chapter-
5, we calcultae the ON-times t0, ta, tb. similarly each vertex of the triangle will be
designated 0, a, b vectors which is useful in switching sequence design.

64
 Fig. 5.23 Five-level space vector diagram sector-1

Fig. 5.24 Five-level space vector diagram sector-2

Switching states and sequence design

Using the procedure described in chapter-5, calculating the total number of

redundant states of each triangle in sectors-1, 2, we decide the category of triangle. From

65
table 5.3 sequences are determined and given in below table 5.8. ESVPWM is for even
harmonic elimination.

Table-5.8 Switching sequences of all triangles for SVPWM and ESVPWM

Sub sector Triangle triangles

category Sequence
SVPWM ESVPWM
TYPE-A even 1,9,11 0ab 0ba

1 TYPE-A odd 0.4,6 Ab0 A0b

TYPE-B even 5 0ba 0ab
TYPE-B odd 2,10,12 Ba0 B0a
TYPE-A even 3,13,15 0ab 0ab
TYPE-A odd 0,6,8 B0a B0a
2 TYPE-B even 7 0ba 0ba
TYPE-B odd 2,12,14 A0b A0b
TYPE-A even 5 0ab 0ab
TYPE-A odd 2,10,12 B0a B0a
3 TYPE-B even 1,9,11 0ba 0ba
TYPE-B odd 0,4,6 A0b A0b
TYPE-A even 7 0ab 0ba
TYPE-A odd 2,12,14 Ab0 A0b
TYPE-B even 3,13,15 0ba 0ab

4 TYPE-B odd 0,6,8 Ba0 B0a

Using the sequence described above, and selecting the correct states along the
various redundant states using the 2 rules mentioned in chapter -5, switching states
applied in first 4 sub sectors for a conventional 7 segment operation is given in table 5.9
and for even harmonic elimination is given in table 5.10

66
 Table 5.9 Switching states used for 7-segment operation

Sub Triangle Segments

sector number
1 2 3 4 5 6 7
0 0-1-1 00-1 000 100 000 00-1 0-1-1
1 0-1-1 1-1-1 10-1 100 10-1 1-1-1 0-1-1
2 0-1-1 00-1 10-1 100 10-1 00-1 0-1-1
4 1-2-2 1-1-2 1-1-1 2-1-1 1-1-1 1-1-2 1-2-2

1 5 1-1-2 1-1-1 10-1 20-1 10-1 1-1-1 1-1-2

6 1-1-2 10-2 10-1 20-1 10-1 10-2 1-1-2
9 1-2-2 2-2-2 2-1-2 2-1-1 2-1-2 2-2-2 1-2-2
10 1-2-2 1-1-2 2-1-2 2-1-1 2-1-2 1-1-2 1-2-2
11 1-1-2 2-1-2 20-2 20-1 20-2 2-1-2 1-1-2
12 1-1-2 10-2 20-2 20-1 20-2 10-2 1-1-2
0 00-1 000 100 110 1-1-2 000 00-1
2 00-1 10-1 100 110 100 10-1 00-1
3 00-1 10-1 11-1 110 11-1 10-1 00-1
6 10-2 10-1 20-1 21-1 20-1 10-1 10-2
7 10-2 10-1 11-1 21-1 11-1 10-1 10-2

2 8 11-2 11-1 21-1 22-1 21-1 11-1 11-2

12 10-2 20-2 20-1 21-1 20-1 20-2 10-2
13 10-2 20-2 21-2 21-1 21-2 20-2 10-2
14 11-2 21-2 21-1 22-1 21-1 21-2 11-2
15 11-2 21-2 22-2 22-1 22-2 21-2 11-2
0 00-1 000 010 110 010 000 00-1
1 00-1 01-1 11-1 110 11-1 01-1 00-1
2 00-1 01-1 010 110 010 01-1 00-1
4 01-2 11-2 11-1 12-1 11-1 11-2 01-2
5 01-2 01-1 11-1 12-1 11-1 01-1 01-2
6 01-2 01-1 02-1 12-1 02-1 01-1 01-2

67
 9 11-2 12-2 22-2 22-1 22-2 12-2 11-2
3
10 11-2 12-2 12-1 22-1 12-1 12-2 11-2
11 01-2 02-2 12-2 12-1 12-2 02-2 01-2
12 01-2 02-2 02-1 12-1 02-1 02-2 01-2
0 -10-1 00-1 000 010 000 00-1 -10-1
2 -10-1 00-1 01-1 010 01-1 00-1 -10-1
3 -10-1 -11-1 01-1 010 01-1 -11-1 -10-1
6 -11-2 01-2 01-1 02-1 01-1 01-2 -11-2

4 7 -11-2 -11-1 01-1 02-1 01-1 -11-1 -11-2

8 -11-2 -11-1 -12-1 02-1 -12-1 -11-1 -11-2
12 -11-2 1-2 02-2 02-1 02-2 01-2 -11-2
13 -11-2 -12-2 02-2 02-1 02-2 -12-2 -11-2
14 -11-2 -12-2 -12-1 02-1 -12-1 -12-2 -11-2
15 -21-2 -22-2 -12-2 -12-1 -12-2 -22-2 -21-2

By using the mapping table 4.4 in chapter-4 we get the switching states of other 8
sub sectors. In order to obtain the switching sequence for even order harmonic
elimination, the same method described in chapter-5 for a three-level inverter should be
used. By using that method, switching states for first 4 subsectors are given in table 5.10.
Remaining subsector’s states are obtained by using mapping table 4.4.

Table 5.10 Switching states used in 7-segment operation for ESVPWM

Sub Triangle Segments

sector number
1 2 3 4 5 6 7
0 100 000 00-1 0-1-1 00-1 000 100
1 100 10-1 1-1-1 0-1-1 1-1-1 10-1 100
2 100 10-1 00-1 0-1-1 00-1 10-1 100
1
4 2-1-1 1-1-1 1-1-2 1-2-2 1-1-2 1-1-1 2-1-1
5 20-1 10-1 1-1-1 1-1-2 1-1-1 10-1 20-1

68
 6 20-1 10-1 10-2 1-1-2 10-2 10-1 20-1
9 2-1-1 2-1-2 2-2-2 1-2-2 2-2-2 2-1-2 2-1-1
10 2-1-1 2-1-2 1-1-2 1-2-2 1-1-2 2-1-2 2-1-1
11 20-1 20-2 2-1-2 1-1-2 2-1-2 20-2 20-1
12 20-1 20-2 10-2 1-1-2 10-2 20-2 20-1
0 00-1 000 100 110 1-1-2 000 00-1
2 00-1 10-1 100 110 100 10-1 00-1
3 00-1 10-1 11-1 110 11-1 10-1 00-1
6 10-2 10-1 20-1 21-1 20-1 10-1 10-2
2
7 10-2 10-1 11-1 21-1 11-1 10-1 10-2
8 11-2 11-1 21-1 22-1 21-1 11-1 11-2
12 10-2 20-2 20-1 21-1 20-1 20-2 10-2
13 10-2 20-2 21-2 21-1 21-2 20-2 10-2
14 11-2 21-2 21-1 22-1 21-1 21-2 11-2
15 11-2 21-2 22-2 22-1 22-2 21-2 11-2
0 00-1 000 010 110 010 000 00-1
1 00-1 01-1 11-1 110 11-1 01-1 00-1
2 00-1 01-1 010 110 010 01-1 00-1
4 01-2 11-2 11-1 12-1 11-1 11-2 01-2
5 01-2 01-1 11-1 12-1 11-1 01-1 01-2

3 6 01-2 01-1 02-1 12-1 02-1 01-1 01-2

9 11-2 12-2 22-2 22-1 22-2 12-2 11-2
10 11-2 12-2 12-1 22-1 12-1 12-2 11-2
11 01-2 02-2 12-2 12-1 12-2 02-2 01-2
12 01-2 02-2 02-1 12-1 02-1 02-2 01-2
0 010 000 00-1 -10-1 00-1 000 010
2 010 01-1 00-1 -10-1 00-1 01-1 010
3 010 01-1 -11-1 -10-1 -11-1 01-1 010
6 02-1 01-1 01-2 -11-2 01-2 01-1 02-1
7 02-1 01-1 -11-1 -11-2 -11-1 01-1 02-1

69
 8 02-1 -12-1 -11-1 -11-2 -11-1 -12-1 02-1
4
12 02-1 02-2 01-2 -11-2 01-2 02-2 02-1
13 02-1 02-2 -12-2 -11-2 -12-2 02-2 02-1
14 02-1 -12-1 -12-2 -11-2 -12-2 -12-1 02-1
15 -12-1 -12-2 -22-2 -21-2 -22-2 -12-2 -12-1

2 & 3 –level operation in 5-level inverter

If the modulation index mi is reduced, the length of the reference vector reduces.
If the reference vector rotates only inside triangle ∆ , then it gives a 2 level operation. If
tip of reference lies only in triangles, ∆ , ∆ , ∆ , then it gives a 3 level operation. If tip
lies in other triangles, then it gives normal 5-level operation. So mi ranges which gives 2,
3 & 5-level operations are given below.

0.907 ≥ > 0.4534 → 5−

0.226 < ≤ 0.4534 → 3 −

≤ 0.226 → 2 −

When operated at low values of mi, the THD value increases. So some other method must
be employed here to reduce the THD at low values of mi .

70
 CHAPTER-6
MATLAB AND D-SPACE IMPLEMENTATION
RESULTS
6.1 Two-level inverter

The below Fig. 6.1 shows a 2-level inverter Simulink model. The pulse generator
block in the Fig. 6.1, generates pulses using various SVPWM techniques and gives it to
the switches.

Fig. 6.1 Two-level VSI Simulink model

6.1.1 Conventional SVPWM:

The Fig. 6.2 shows the pulse generator block using conventional SVPWM. In the
first block, reference sinusoidal signals are converted to co-ordinates. Second block
samples the continuous signal at a rate which determines the switching frequency. Sector
calculation block determines the sector where reference vector is present, using the
formulae given in chapter -4.

71
In the switching state selector block, ON times t0, ta, tb are calculated. These ON times
compared with a carrier triangle, that represents sampling time Ts, gives segments of 7-
segment operation as shown in Fig. 6.3

Fig. 6.2 SVPWM Simulink model

Fig. 6.3 Segment calculation block

72
 In the gate signal generator block, switching states to be given for first 2 sectors are
stored as matrices, and by using the mapping table described in chapter 4, switching
states of other 4 sectors are given from first 2 sectors itself, but by rearranging the order
of states of first 2 sectors using MUX and DMUX as shown in Fig. 6.4

Fig. 6.4 Sector’s switching state mapping

The output pole, phase, line voltages and current waveforms and FFT analysis are shown
below for mi = 0.907 and switching frequency = 42*50 Hertz.

Pole voltage

73
 Fig. 6.5 Pole voltage and it’s FFT analysis for conventional SVPWM

Line voltage

Fig. 6.6 Line voltage and it’s FFT analysis for conventional SVPWM

74
 Line current

Fig. 6.7 Line current and it’s FFT analysis for conventional SVPWM

6.1.2 Even harmonic elimination

In this Simulink model, each sector will be divided in to 2 subsectors. So there

will be 12 subsectors. We give the state sequence for first four sub sectors, and for
remaining 8 subsectors, state sequence will be obtained by changing the order by using
MUX and DMUX as shown in Fig. below. Subsector will be given by formula

+ 1 . Remaining model will be similar to conventional SVPWM before.

75
 Fig. 6.8 Sector’s switching states mapping in ESVPWM

The output pole, line voltages and current waveforms and FFT analysis are shown
below for mi = 0.907 and switching frequency = 42*50 Hertz.

Pole voltage

Fig. 6.9 Pole voltage and it’s FFT analysis for ESVPWM 76
Line voltage

Fig. 6.10 Line voltage and it’s FFT analysis for ESVPWM

Current

77
 Fig. 6.11 Line current and it’s FFT analysis for conventional SVPWM

6.1.3 Bus clamping SVPWM

This is a five segment operation. So switching state selector block in Fig. 8.2 will
be as shown in Fig. 8.10. Switching states mentioned in chapter-4 will be given for
sectors in gate signal generator block.

Fig.6.12 Segment calculation block

6.1.3.1 Positive bus clamping (120o)

The output pole, line voltages and current waveforms and FFT analysis for
positive bus clamping are shown below for mi = 0.907 and switching frequency = 42*50

78
Hertz. We can observe from pole voltage plot that the pole voltage got clamped to
positive bus for a period of 120o in a cycle.

Pole voltage

Fig. 6.13 Pole voltage and it’s FFT analysis for 1200 positive bus clamp

Line voltage

79
 Fig. 6.14 Line voltage and it’s FFT analysis for 1200 Positive bus clamp

Current

Fig. 6.15 Line current and it’s FFT analysis for 1200 Positive bus clamp

80
 6.1.3.2 Negative bus clamping (120o)

This can be obtained by changing the switching states of first 2 sectors according
to the table given in chapter-4. The output pole, phase, line voltages and current
waveforms and FFT analysis for positive bus clamping are shown below for mi = 0.907
and switching frequency = 42*50 Hertz. We can observe from pole voltage plot that the
pole voltage got clamped to negative bus for a period of 120o in a cycle.

Pole voltage

Fig. 6.16 Pole voltage and it’s FFT analysis for 1200 Negative bus clamp

81
 Line voltage

Fig. 6.17 Line voltage and it’s FFT analysis for 1200 Negative bus clamp

Current

82
 Fig. 6.18 Line current and it’s FFT analysis for 1200 Negative bus clamp

6.1.3.3 600 bus clamping

This can be obtained by changing the switching states of first 4 sub sectors according
to the table given in chapter-4.The output pole, phase, line voltages and current
waveforms and FFT analysis for positive bus clamping are shown below for mi = 0.907
and switching frequency = 42*50 Hertz. We can observe from pole voltage plot that the
pole voltage gets clamped to negative bus for a period of 600 and for positive DC bus for
another 600 in a cycle.

Pole voltage

83
 Fig. 6.19 Pole voltage and it’s FFT analysis for 600 Bus clamp

Line voltage

Fig. 6.20 Line voltage and it’s FFT analysis for 600 Bus clamp

84
 Current

Fig. 6.21 Line current and it’s FFT analysis for 600 Bus clamp

6.1.3.4 300 bus clamping

This can be obtained by changing the switching states of first 4 sub sectors
according to the table given in chapter-4.The output pole, phase, line voltages and current
waveforms and FFT analysis for positive bus clamping are shown below for mi = 0.907
and switching frequency = 42*50 Hertz. We can observe from pole voltage plot that the
pole voltage gets clamped to negative bus for a period of 300 for both positive and
negative DC buses at 2 instants in a cycle. 600 interval in previous clamping is split into
two 300 intervals in a cycle.

85
Pole voltage

Fig. 6.22 Pole voltage and it’s FFT analysis for 300 Bus clamp

Line voltage

86
 Fig. 6.23 Line voltage and it’s FFT analysis for 300 Bus clamp

Current

Fig. 6.24 Line current and it’s FFT analysis for 300 Bus clamp

87
6.1.4 Advanced bus clamping

This again involves the seven segment operation. So switching state selector will
be similar to conventional SVPWM shown in Fig. 6.4

6.1.4.1 60o clamping

This can be obtained by changing the switching states of first 4 sub sectors
according to the table given in chapter-4.The output pole, phase, line voltages and current
waveforms and FFT analysis for positive bus clamping are shown below for mi = 0.907
and switching frequency = 42*50 Hertz. We can observe from pole voltage plot that the
pole voltage gets clamped to negative bus for a period of 600 and for positive DC bus for
another 600 in a cycle.

Pole voltage

Fig. 6.25 Pole voltage and it’s FFT analysis for 600 Advanced Bus clamp

88
 Line voltage

Fig. 6.26 Line voltage and it’s FFT analysis for 600 Advanced Bus clamp

Current

89
 Fig. 6.27 Line current and it’s FFT analysis for 600 Advanced Bus clamp

6.1.4.2 300 bus clamping

This can be obtained by changing the switching states of first 4 sub sectors
according to the table given in chapter-4.The output pole, phase, line voltages and current
waveforms and FFT analysis for positive bus clamping are shown below for mi = 0.907
and switching frequency = 42*50 Hertz. We can observe from pole voltage plot that the
pole voltage gets clamped to negative bus for a period of 300 for both positive and
negative DC buses at 2 instants in a cycle. 600 interval in previous clamping is split into
two 300 intervals in a cycle.

Pole voltage

90
 Fig. 6.28 Pole voltage and it’s FFT analysis for 300 Advanced Bus clamp

Line voltage

Fig. 6.29 Line voltage and it’s FFT analysis for 300 Advanced Bus clamp

91
 Current

Fig. 6.30 Line current and it’s FFT analysis for 300 Advanced Bus clamp

6.2 Three-level NPC inverter

Simulation diagram of a 3 level NPC inverter is shown in Fig. 6.31 below. The 3
different modulation techniques described in before chapter are used to generate pulses
for the 3-level inverter. Their simulations are described below.

92
6.2.1 Staircase modulation

Using the angle discussed in chapter 5.2.1, pulses will be generated for switches
in all the 3 poles using the pulse generators, as shown in Fig. 6.32. Pole, Line voltage and
current wave forms simulated for mi = 0.9 and their FFT analysis is shown in Fig. 6.33-
6.35

Fig. 6.31 Three-level NPC inverter simulation model

Fig. 6.32 Pulse generators for RYB poles using Staircase modulation

93
Pole voltage

Fig. 6.33 Pole voltage and it’s FFT analysis

Line voltage

94
 Fig. 6.34 Line voltage and it’s FFT analysis

Current

Fig. 6.35 Line current and it’s FFT analysis

95
6.2.2 Carrier based modulation

The four types of carrier based modulation techniques, described in chapter-5.2.2 will be
applied here. Simulation model for generating pulses to a single pole in IPD and POD is
shown in Fig. 6.36.

Fig. 6.36 IPD and POD pulse generators

Line, pole voltage and current waveforms are shown in Fig. 6.37 for mi = 1.

Pole voltage

Line voltage

96
 Current

Fig. 6.37 Pole, Line voltage and current waveforms

FFT analysis for line voltage and currents in IPD, POD, are given in FIG. 6.38-6.39

IPD

Fig. 6.38 IPD line voltage and current FFT

97
 POD

Fig. 6.39 POD line voltage and current FFT

SFO carrier based PWM techniques are implemented by injecting the third harmonic
voltage into all the three phase sinusoidal signals. The resultant reference wave is shown
in Fig. 6.40

Fig. 6.40 SFO carrier based technique’s reference wave

98
Waveforms obtained in SFO techniques will be similar to normal carrier based PWM
techniques. FFT analysis of line voltage and currents of SFOIPD and SFOPOD are given
in Fig. 6.41-6.42

SFOIPD

Fig. 6.41 SFOIPD line voltage and current FFT

SFOPOD

99
 Fig. 6.42 SFOPOD line voltage and current FFT

6.2.3 SVPWM

We use conventional SVPWM to generate pulses for the 3-level NPC inverter.
The SVPWM model for 3-level inverter is shown in Fig.6.43. The first block converts 3-
phase quantities to co-ordinates. In the second block, sampling and holding takes
place which controls the switching frequency.

Fig. 6.43 Three level SVPWM pulse generator model

Magnitude of sinusoidal reference

In the algorithm described above, vector lengths are normalized by dividing with
Vdc , in the state space diagram. So reference vector v* should also be divided by Vdc. Let
Vref peak be the magnitude of sinusoidal reference. By normalizing v*, we get

∗
=

100
 = ‘n’ – level of the inverter.
( )

∗
3
= ( − 1)

Sine reference magnitude to taken in simulation should be

2
= ∗ ∗ ( − 1)

Second block also involves calculation of ON-times and triangular number calculation. It
is shown in Fig. 6.44 below.

Fig. 6.44 Triangle number calculator block

Sequences for various categories of triangles, as described in chapter-6 are designed

by comparing a triangular carrier wave with ON- times. This takes place in third block
and shown in below Fig. 6.45. Sequences are given to the multi-switch selectors, whose
control terminal will be triangle number. Last block contains the switching states of first
four subsectors and they will be mapped to other 8 sub sectors by proper rearrangement
using MUX and DEMUX and is shown in below Fig. 6.46

101
 Fig. 6.45 Sequence design block

Fig. 6.46 Switching states mapping to all sub sectors

Finally all these gate pulses are used to control the three multiport switches.
These signals will tell which voltage level (+Vdc, 0, Vdc) will appear in output voltage to

102
get approximated sinusoidal wave. Multi-port switches pass the switching states of the
multi-level inverters to the inverter switches based on the port number is shown in below
Fig. 6.47.

Fig. 6.47

The output pole, line voltages and current waveforms and FFT analysis of a 3-
level NPC are shown in below Fig. 6.47-6.50 for mi = 0.907 and switching frequency =
42*50 Hertz.

Pole voltage

103
 Fig. 6.48 Pole voltage and it’s FFT

Line voltage

Fig. 6.49 Line voltage and it’s FFT

104
 Current

Fig. 6.50 Line current and it’s FFT

6.2.3.1 Even harmonic elimination

This is done by changing the switching sequences of first 4 sub sectors as described
in chapter-6. The output pole, line voltages and current waveforms will be similar to
Conventional SVPWM and their FFT analysis are shown in below Fig. 6.51-6.53, for mi
= 0.907 and switching frequency = 42*50 Hertz.

105
 Fig. 6.51 Pole voltage FFT

Fig. 6.52 Line voltage FFT

Fig. 6.53 Line current FFT

106
6.3 Five-level CHB inverter

The below Fig. 6.54 shows the simulation diagram of a 5-level CHB inverter. Here we
used 3 modulation techniques to generate pulses to the inverter. They are 1. Staircase
modulation, 2. Carrier based PWM, 3. SVPWM.

6.3.1 Staircase modulation

It involves solving of 2 equations, 5.22 & 5.23 given in chapter-7. We use NR- method to
solve these non-linear equations. The coding used to solve the equations in MATLAB is
given below.

Fig. 6.54 Five-level CHB inverter model

NR-coding

clc
n = 2;
e = .00001;
a = [ 45 10 ];
a = degtorad(a);

for r = 1:inf
p = zeros(2,1);
p(1) = cos(a(1))+cos(a(2))-1.8;
p(2) = cos(5*a(1))+cos(5*a(2));
p = -1*p;

107
 tol = abs(max(p));
if tol<=e
break
else
j1 = -sin(a(1));
j2 = -sin(a(2));
j3 = -5*sin(5*a(1));
j4 = -5*sin(5*a(2));
j = [ j1 j2
j3 j4 ];
da = inv(j)*p;
for i = 1:n
a(i) = a(i)+da(i);
end
end
end
a = radtodeg(a);
disp(a)

Executing above we get

= . = .

Using these values, pulses shown in chapter-5.3.1 are generated and given to switches.
Simulation diagram of this is shown below. Pulse generators shown in Fig. 6.55 are
present in each block.

Fig. 6.55 Pulse generators for Staircase modulation

108
 The output pole, line voltages and current waveforms and FFT analysis of a 5-level
CHB controlled by Staircase modulation are shown in below Fig. 6.56-6.58, for mi = 0.9.
WTHD = 1.258 %. We can observe that fifth harmonic is completely eliminated in all
voltages. But THD of current is very high and current wave form is not close to
sinusoidal. Also voltage waveforms contain some high amount of lower order harmonics
like 7th, 11th etc. which should be low. So due to these drawbacks in this technique, we
use this less.
Pole voltage

Fig. 6.56 Pole voltage and it’s FFT

Line voltage

109
 Fig. 6.57 Line voltage and it’s FFT
Current

Fig. 6.58 Current and it’s FFT

6.3.2 Carrier based PWM

As discussed in chapter-5.3.2, three types triangle PWMs are generally used.
They are 1. IPD, 2. POD, 3. APOD. By injecting certain magnitude of third harmonic
into three phase reference wave, output voltage magnitude can be further increased,
without going into over modulation and it also optimizes switching frequency. So it’s

110
called switching frequency optimization (SFO) techniques, which can be classified as 3
types. They are 1. SFOIPD, 2. SFOPOD, 3. SFOAPOD. The model used to generate
carrier waves and their corresponding carrier waves in 3 types of PWMs are shown in
below Fig. 6.59-6.61.
IPD

Fig. 6.59 IPD carrier waves generator block and it’s carrier waves

111
POD

Fig. 6.60 POD carrier waves generator block and it’s carrier waves
APOD

112
 Fig. 6.61 APOD carrier waves generator block and it’s carrier waves

The waveforms of pole, line voltages and currents of 5-level CHB inverter using sine-
triangle PWM are shown in Fig. 6.62 below.

Pole voltage

Line voltage

113
 Current

Fig. 6.62 Pole, Line voltage and current waveforms

The FFT analysis of line voltages and currents of 5 – level CHB inverter, using above 3
types of SPWMs are given below in Fig. 6.63-6.65
IPD

Fig. 6.63 IPD line voltage and current FFT

114
POD

Fig. 6.64 POD line voltage and current FFT

APOD

Fig. 6.65 APOD line voltage and current FFT

115
SFO carrier based PWM techniques are implemented by injecting the third harmonic
voltage into all the three phase sinusoidal signals. The resultant reference wave is shown
in Fig. 6.66

Fig. 6.66 SFO carrier based technique’s reference wave

Waveforms obtained in SFO techniques will be similar to normal carrier based PWM
techniques. FFT analysis of line voltage and currents of SFOIPD, SFOPOD, SFOAPOD
are given in Fig. 6.67-6.69

SFO IPD

Fig. 6.67 SFOIPD line voltage and current FFT

116
SFO POD

Fig. 6.68 SFOPOD line voltage and current FFT

SFO APOD

117
 Fig. 6.69 SFOAPOD line voltage and current FFT

We can observe that voltage rise in SFO PWMs compared to normal PWMs is about 15%
at same modulation index.
6.3.3 SVPWM
Simulation diagram of SVPWM for 5-level CHB inverter is shown in below Fig.
6.70. All the blocks are similar to that of the 3-level NPC inverter SVPWM described in
section 6.2.3. Only the number of triangles in each sector increases to 15, and switching
state sequences should be designed to each triangle according to rules described in
chapter 5.

Fig. 6.70 Five-level SVPWM pulse generator

6.3.3.1 SVPWM linear modulation :
The output pole, line voltages and current waveforms of a 5-level CHB controlled by
SVPWM is shown in below Fig. 6.71 for mi = 0.907.

118
 Pole voltage

Line voltage

Current

Fig. 6.71 Pole, Line voltage and current waveforms

SVPWM involving even order harmonic elimination also produces similar wave
forms, but with different FFT results. FFT analysis of line, pole voltages and currents in
SVPWM and ESVPWM are shown below.

119
Pole voltages
SVPWM

ESVPWM

Fig. 6.72 Pole voltage FFT in SVPWM and ESVPWM

Line voltages
SVPWM

120
 ESVPWM

Fig. 6.73 Line voltage FFT in SVPWM and ESVPWM

Currents
SVPWM

ESVPWM

Fig. 6.74 Line current FFT in SVPWM and ESVPWM

121
6.3.3.2 Overmodulation-1
Algorithm for overmodulation-1 is already discussed in chapter-5. Simulation
block for this is shown in below Fig. 6.75. There are 2 blocks named hexagonal track and
circular track which calculates the ON times in 2 different cases as given in algorithm.
The output pole, line voltages and current waveforms and FFT analysis of a 5-level CHB
controlled by SVPWM operated in overmodulation-1 is shown in below Fig. 6.76-6.78
for mi = 0.94 and switching frequency = 42*50 Hz.

Fig. 6.75 Over modulation-1 pulse generator

Pole voltage

122
 Fig. 6.76 Pole voltage in Overmodulation-1 region and it’s FFT
Line voltage

Fig. 6.77 Line voltage in Overmodulation-1 region and it’s FFT

123
 Current

Fig. 6.78 Line current in Overmodulation-1 region and it’s FFT

6.3.3.3 Overmodulation-2
Algorithm for overmodulation-2 is already discussed in chapter-5. Simulation
block for this is shown in below Fig. 6.79. There are 2 blocks named hexagonal track and
long vector application which calculates the ON times in 2 different cases as given in
algorithm and suitable states will be applied.
The output pole, line voltages and current waveforms and FFT analysis of a 5-
level CHB controlled by SVPWM operated in overmodulation-2 is shown in below Fig.
6.80-6.82 for mi = 0.98 and switching frequency = 42*50 Hz. We can observe from 2
over modulations that as mi increases and approaches to 1, chopping nature of voltage
waveform reduces and approaches to six step voltage wave form. Also as mi increases,
current THD increases, apart from increase in fundamental voltage magnitude.

124
 Fig. 6.79 Over modulation-2 pulse generator

Pole voltage

125
 Fig. 6.80 Pole voltage in Overmodulation-2 mode and it’s FFT
Line voltage

Fig. 6.81 Line voltage in Overmodulation-2 mode and it’s FFT

126
Current

Fig. 6.82 Line current in Overmodulation-2 mode and it’s FFT

Below waveform in Fig. 6.83 shows the six-step line voltage waveform at mi = 1.
So we can say 5 level inverter loses it 5-level characteristic at mi = 1

Fig. 6.83 Line voltage of 5-level inverter at mi = 1

127
6.4 Hard ware implementation on two-level inverter
A D-SPACE (DS 1104) controller is used in this project for the practical
implementation of the various PWM techniques on a two-level inverter. DS 1104
controller was manufactured by a German company called D-SPACE. DS1104 Controller
Board comes with software packages called Real Time interface (RTI) and Control Desk.
The D-SPACE works on MATLAB/SIMULINK platform which is a common
engineering software and easy to understand. Control desk of the D-SPACE allows the
graphical user interface, through which the user can observe the response of the system
and give command to the system through this interface. RTI is the link between D-
SPACE’s real time systems and the development software MATLAB/SIMULINK.
The experimental setup shown in fig. 6.84 consists of SEMIKRON VSI, DS1104
controller, an auto transformer, a RL-load and Power Analyzer. SEMIKRON VSI is a 3-
phase IGBT based inverter driven by SKYPER32 R Gate Driver card. The DC input to
VSI is controlled by an auto transformer through a 3-phase diode bridge rectifier. The
pulses coming out physically from DS1104 controller will be of 5 volts magnitude, while
SKIPER32R gate driver card needs pulse of 15 volts magnitude. So a level shifter card
will be used in between controller and the gate driver to push up the pulse magnitude to
15 volts.
The Pulses to the inverter are first obtained in MATLAB/SIMULINK environment
and a relevant coding is written to generate the pulses and by using RTI software
conversion tool the SLX-files of MATLAB are converted in to the C coding which
generates a SDF (system description file). The SDF file is loaded into the DS1104
controller board through control desk and then controller board is brought to online to
generate pulses in the real time scenario, which can be collected from the DS1104
connector box.
By using the controller, the following techniques are implemented on two-level VSI
1. Square wave operation ( 1800 mode), 2. Sine triangle PWM, 3. Various types of
SVPWMs. The captured voltage and current wave forms are shown in figures below. In
PWM techniques, inverter was operated at a switching frequency of 2100 Hz. Output
voltage was applied to a RL load of R = 81 ohms and L = 30 milli Henry

128
 Fig. 6.84 Experimental Setup

Sine triangle PWM

129
Fig. 6.84 Pole, Line voltages and current waveforms in SPWM

130
6.4.1 Square wave operation

Fig. 6.84 Pole, Line voltages and current waveforms in 1800 mode

131
6.4.3 Conventional SVPWM

Fig. 6.86 Pole, Line voltages and current waveforms in Conventional SVPWM

132
6.4.4 600 Bus clamp SVPWM

Fig. 6.87 Pole, Line voltages and current waveforms in 600 Bus clamp SVPWM

133
6.4.5 600 Advanced Bus clamp SVPWM

Fig. 6.88 Pole, Line voltages and current waveforms in 600 ABC SVPWM

134
6.5 Comparison of results
For all types of inverters, models are simulated and results are taken for a common RL-
load with R = 15 Ohms and L = 0.05 Henry, switching frequency = 42*50 Hz

Table 6.1 Two-level SVPWM techniques comparison at mi = 0.907,Vdc = 200V

technique VAB1 (peak) VTHD(%) ITHD(%) WTHD(%)
NSVPWM 199 52.92 1.28 1.03
ESVPWM 199.2 52.71 1.28 0.93
+BC120 198.8 52.87 1.32 1.1
-BC120 198.8 52.87 1.32 1.1
BC60 198.5 52.91 1.35 0.96
BC30 199 52.83 1.28 0.93
ADVBC60 198.9 52.92 0.75 0.55
ADVBC30 199.2 52.67 0.72 0.49

Table 6.2 Three-level PWMs comparison at maximum mi , Vdc = 200V

technique VAB1 (peak) VTHD(%) ITHD (%) WTHD (%)
IPD 172.2 35.87 0.86 0.6
POD 172.5 40.43 1.03 0.73
SFOIPD 199.1 27.33 0.69 0.48
SFOPOD 199.1 30.10 0.80 0.57
Staircase 198.4 25.15 5.06 3.7
SVPWM 197.4 27.86 0.61 2.5
ESVPWM 197.3 27.85 0.61 0.4

135
 Table 6.3 Five-level PWMs comparison at maximum mi, Vdc1 = Vdc2 = 200V
technique VAB1 (peak) VTHD(%) ITHD (%) WTHD (%)
IPD 342.2 17.22 0.40 0.29
POD 342.2 21.77 0.61 0.63
APOD 342.2 25.69 0.78 0.57
SFOIPD 393.2 13.91 0.37 0.261
SFOPOD 393.2 16.39 0.49 1.9
SFOAPOD 393.3 16.66 0.46 1.2
Staircase 391.8 14.30 1.73 1.26
SVPWM 399.7 14.08 0.29 0.465
ESVPWM 394.6 14.16 0.30 0.207

Table 6.4 Five-Level SVPWM THDs at various mi values

mi VAB1 (peak) VTHD(%) ITHD(%) WTHD(%)
0.907 394.6 14.16 0.30 0.207
0.94 407.9 12.81 0.62 0.46
0.98 426.9 16.96 3.29 2.42
1 434 25.25 5.72 4.2

136
 CHAPTER-7
CONCLUSION
7.1 Conclusion
From the comparison table of the two-level inverter, we conclude that by
employing advanced bus clamping techniques, the current THD can be reduced to a less
value compared with conventional SVPWM techniques and others.
Among carrier comparison techniques, applied for multi-level inverters, we can
conclude that IPD technique gives better waveforms with low THD compared to other
two techniques. Third harmonic injection gives 15% high output voltage compared with
normal carrier PWM techniques. So we can say this technique is synonymous to
SVPWM technique, but with some high amount of THD compared to SVPWM.
From the SVPWM technique applied to 5-level CHB inverter, we conclude that as
modulation index (mi) approaches to one, chopping of wave decreases with increase in
magnitude of fundamental voltage. Also THD increases in over modulation range. At
mi =1 the SVPWM operation becomes a six step operation.

7.2 Future scope

Bus clamping techniques can be applied for multi-level inverters, and its benefits
can be accomplished even in multi-level operation. More detailed study can be made on
the switching states sequence and their selection in SVPWM technique for the reduction
of harmonics to a much lesser value.

137
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138