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High-Gain Cmos LOW Noise Amplifier FOR Ultra Wide-Band Wireless Receiver

This document describes a CMOS low-noise amplifier (LNA) designed for ultra-wideband wireless receivers operating from 3-5 GHz. The LNA uses a cascode amplifier topology with inductive degeneration and wideband input/output matching networks optimized using a least-squares algorithm to minimize noise figure and maximize gain. Simulation results show the LNA achieves a gain of 19.9-18.9 dB and noise figure of 0.6-0.8 dB over the 3-5 GHz band, with a 1-dB compression point of -10.5 dBm and third-order intercept point of 18 dBm.

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0% found this document useful (0 votes)
90 views9 pages

High-Gain Cmos LOW Noise Amplifier FOR Ultra Wide-Band Wireless Receiver

This document describes a CMOS low-noise amplifier (LNA) designed for ultra-wideband wireless receivers operating from 3-5 GHz. The LNA uses a cascode amplifier topology with inductive degeneration and wideband input/output matching networks optimized using a least-squares algorithm to minimize noise figure and maximize gain. Simulation results show the LNA achieves a gain of 19.9-18.9 dB and noise figure of 0.6-0.8 dB over the 3-5 GHz band, with a 1-dB compression point of -10.5 dBm and third-order intercept point of 18 dBm.

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beki4
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Progress In Electromagnetics Research C, Vol.

7, 183–191, 2009

HIGH-GAIN CMOS LOW NOISE AMPLIFIER FOR


ULTRA WIDE-BAND WIRELESS RECEIVER

A. Dorafshan and M. Soleimani


Electrical Engineering Department
Iran University of Science and Technology
Tehran 16846, Iran

Abstract—A 3–5 GHz broadband CMOS single-ended LNA with a


new theoretical approach based on least-square algorithm is presented
in this paper. The design consists of a wideband input impedance
matching network, a cascoded amplifier with inductively-degenerated
LNA, and an output impedance matching network. It is simulated in
TSMC 0.18 µm standard RF CMOS process. The optimum matching
network is designed to minimize the noise figure (NF) and maximize
the power gain. The elements values of optimum matching network
have been obtained using the least-square algorithm. The proposed
LNA exhibits a gain in range of 19.9–18.9 dB, over the UWB low-band
(3 to 5 GHz). Moreover, the noise figure is obtained in range of 0.6–
0.8 dB. Besides, the input P1-dB and IIP3 are −10.5 dBm and 18 dBm,
respectively. The proposed method has minimum 4 dB power gain
improvement in relative to similar works with constant noise figure.
Also, the DC supply is considered to be 1.8 V.

1. INTRODUCTION

Recently, numerous methods have been proposed for ultra-wideband


(UWB) communication systems of IEEE 802.15.3a. Since the
Federal Communications Commission (FCC) established an unlicensed
communication band (3.1–10.6 GHz) and restricted transmitted power
levels, in the spring of 2002, UWB systems have become an increasingly
popular technology, which is capable of transmitting data over a
wide spectrum of frequency. The FCC defined an UWB signal to
have a spectral occupancy over 500 MHz or a fractional bandwidth
of more than 20%. There are basically two different system level
communication strategies employed to efficiently utilize the entire
UWB spectrum, namely, Impulse-type UWB (IR-UWB) and carrier-
based orthogonal frequency division multiplexing (OFDM). There exist
184 Dorafshan and Soleimani

several architectures to improve the frequency bandwidth of low-noise


amplifiers (LNAs), including distributed [1] and shunt feedback [2]
topologies. In this paper, two embedded band pass filter are used as the
input and output impedance matching networks, optimized with least-
squre method, for the cascode LNA with inductive source degeneration
topology, yet it is capable of achieving input impedance matching and
a low noise figure (NF). The proposed LNA, designed for multiband
OFDM UWB systems, employs a 0.18 µm TSMC CMOS process with
an ft greater than 90 GHz. The remaining of this paper is organized
as follows. In Section 2, circuit design is introduced; in Subsection
2.1, wideband matching network is proposed and in Subsection 2.2, the
proposed LNA circuit is considered. Simulation results are presented in
Section 3. Finally, in Section 4, conclusions of this paper are presented.

Vdd

Rd
C block R1
Ld
C’1 C’2 L’1
M3
M2
C’3 C’4 L’2
R2

C2 L2 L1
Z o Z out output matching cell

L3 C1
LS

Z IN
input matching cell

Figure 1. Schematic of the proposed low-noise amplifier for UWB


system.

2. CIRCUIT DESIGN

2.1. Wideband Matching Network


The proposed method is explained and discussed by taking the
circuits of a five-order band pass filter for input and output matching
cell. Fig. 1 shows the circuit description of the LNA designed
Progress In Electromagnetics Research C, Vol. 7, 2009 185

with the proposed methodology in this paper. The inductive source


degeneration of M1 by LS is used to adjust the real part of the input
impedance ZIN at M1 input. ZIN can be approximated by [3, 4].

ZIN = Ropt + jXopt (1)

where Ropt and Xopt are the optimum source resistance and the
optimum source reactance, respectively, which are given by
m
Ropt = (2)
ωCgs
Xopt = −ωLs + K/ (ωCgs ) (3)

where K is a technology-dependant parameter, and its value


approaches 0.8 for 0.18 µm technology, also m is another technology-
dependant parameter. K and m are comparable values, and if ωLs 
K/ωCgs , we may write Xopt (ω) ≈ K/ωCgs . So, Xopt = nRopt where
n = K/m, and it is a constant value. Moreover, Cgs is gate-source
capacitance.
The designing procedure is based directly on the scattering
parameters data without any approximation by the unilateral model.
In this paper, [Sij ] denotes normalized scattering matrix to 50 Ω; the
impedance at port 2 of the input matching network is denoted by Zi
and given by

a5 S 5 + a4 S 4 + a3 S 3 + a2 S 2 + a1 S + a0
ZIN = , (4)
b4 S 4 + b3 S 3 + b2 S 2 + b1 S
where, ai ’s are defined as:

a5 = L3 L1 L2 C1 C2 , (5)
a4 = Z0 (L1 C1 C2 L3 + L1 L2 C1 C2 ) , (6)
a3 = L1 L3 C2 + L2 L3 C2 , (7)
a2 = Z0 (C2 L3 + L1 C1 + L1 C2 + L2 C2 ) , (8)
a1 = L3 (9)

and
a0 = Z0 . (10)
and bi s are defined as

b4 = L3 L2 C1 C2 , (11)
b3 = Z0 (C1 C2 L3 + C2 C1 L2 ) , (12)
b2 = L3 C1 + L3 C2 , (13)
186 Dorafshan and Soleimani

and
b1 = C1 + C2 . (14)
In the first step of this procedure the reflection coefficient (Γi ) of
the input matching network is reduced and normalized to optimum
source impedance (i.e., Zopt ), corresponding to minimum noise figure
(NFmin ), and Γi is given by

ZIN − Zopt
Γi = (15)
ZIN + Zopt
The desired ZIN is obtained to minimize the error function of E (ω),
which is defined as:
 
 k  ∗ 2 
 ZIN (jωi ) − Zopt (jωi )  2
E(ω) =  − |Γi (jωi )|  (16)
 ZIN (jωi ) + Zopt (jωi )  
i=1

where k is the observation points, and ωi is the frequency corresponds


to observation points.
ZIN is specified with unknown coefficients; E (ω) can be minimized
using the non-linear least-squares method [5].
The transducer power gain of the network is given by
  |S21 |2   1 − |Γo |2
G ω2 = · 1 − |Γ i |2
· (17)
(1 − |S11 |2 ) 1 − |Γo |2
where Γo is the reflection coefficient of output matching network at
port 1; it is normalized to output impedance of active device Zo , when
its input is terminated in input matching cell and 50 Ω. Γo is given by
Zout − Zo∗
Γo = (18)
Zout + Zo
It can be seen in Fig. 1 that Zout is the impedance of the output
matching network at port 1.
The second step is similar to the first one; it finds Zout to reduce
the reflection coefficient of output matching network.

2.2. The Proposed LNA Circuit


The cascode architecture generally improves the frequency response
of the amplifier, reverses isolation, and reduces the Miller effect.
Moreover, a single-ended amplifier is preferred over its differential
counterpart to eliminate the need for a balun. Fig. 1 shows the
complete schematic of designed LNA. The width 0.18 µm of transistor
Progress In Electromagnetics Research C, Vol. 7, 2009 187

M1 is chosen to satisfy the power budget requirement and to achieve


the minimum Rn and NFmin (first step of design technique). With
this choice of parameters, the cascode core draws a small current of
12 mA from a 1.8 V power supply. M1 , M3 and R1 form a current
mirror to provide the bias for the input transistor. The width of M3
is chosen to be very small to minimize the power headroom of the
bias circuitry (WM 3 = 0.2 µm). The resistor R2 is chosen very large
to reduce its noise contribution to the input of LNA [12]. Also, a
matching network is designed in previous section to obtain the desired
bandwidth. The values of passive elements in the input matching
network are L1 = 8 nH, C1 = 664 pF, L2 = 1.1 nH, L3 = 2.5 nH, and
C2 = 33.8 pF. The output load of LNA is a shunt-peaking structure
and is formed by an inductor (Ld = 1.5 nH) in series with a resistor
(Rd = 1.2 Ω). The values of passive elements in the output matching
network are L1 = 5 nH, C1 = 3.1 pF, L2 = 1.4 nH, C2 = 0.36 pF,
C3 = 1.33 pF, and C4 = 1.14 pF. The inductive nature of this load
compensates the gain roll-off of LNA at high frequencies. Shunt
peaking load is used at the drain of the cascade transistor to enhance
the bandwidth of the LNA. The value of Rd (1.2 Ω) is chosen as a
compromise between the gain at low frequencies and the linearity. The
inductance Ld (1.5 nH) also compensates the current gain roll-off at
high frequencies. For the designed LNA, the width of M2 is chosen
grater than the width of M1 to improve the gain and stability. The
circuit is simulated by using Agilent’s Advanced Design System (ADS).
The power consumption is 23 mW.

Figure 2. Power gain.


188 Dorafshan and Soleimani

Figure 3. Input and output return loss.

Figure 4. Reverse isolation.

3. SIMULATION RESULT

The UWB LNA circuit is simulated in Agilent ADS simulator using


TSMC 0.18 µm mixed signal 1P6M CMOS process with RF model
with a 1.8-V supply voltage, and the results are show in Fig. 2 to
Fig. 4. Fig. 2 shows the forward gain (S21 ) and the input and output
Progress In Electromagnetics Research C, Vol. 7, 2009 189

reflection coefficients S11 and S22 in the bandwidth between 3 GHz to


5 GHz. Using the matching network we achieve a good gain flatness
of +/ − 1 dB with the maximum gain of 19.9 dB at the frequency
of 3 GHz and the minimum gain of 18.9 dB at frequency of 5 GHz.
Besides, the S11 is approximately less than −7 dB and becomes worse
while the operating frequency is less 3.5 GHz. In Fig. 3, it can be seen

Figure 5. Noise-figure.

Figure 6. Input power comperssion 1 dB.


190 Dorafshan and Soleimani

Figure 7. Third order intercep point.

that the high reverse isolation (S12 ) is below −37 dB. The noise figure
is approximately below 0.87 dB as shown in Fig. 4. The minimum
one is 0.65 dB at 3.1 GHz. The 1-dB compression point (P1dBin) is
approximately −10 dBm at the center frequency of 4 GHz as shown in
Fig. 5. The third order inter-modulation distortion is shown in Fig. 6.
The third order input intercept point (IIP3) of the LNA is +18 dBm
at 4 GHz. In order to achieve a very broad bandwidth with a low noise
figure, we use the relatively large bias voltage Vgs at the cost of power
consumpation.

4. CONCLUSIONS

This paper presents a 3–5 GHz broadband CMOS LNA applied for
ultra-wide-band communication applications with the 0.18 µm TSMC
CMOS technology. In the UWB low band (3.1–4.8 GHz) under 1.8 V
supply voltage, the broadband LNA exhibits a gain of 19–20 dB,
noise figure of 0.6 dB/0.8 dB, input return loss better than 6 dB/7 dB,
isolation better than 35/39 dB, IIP3 of 18 dBm and input P1dB of
−10 dBm. In the 3–5 GHz range (covering 802.15a and MBOA group
A) under 1.8 V compared with previously reported UWB CMOS LNAs,
our LNA with a optimum match filter has an about 4–5 dB more gain
and a better noise figure performance at 3–5 GHz range. This type of
LNA in this paper shows a potential for high gain and low noise design
applications.
Progress In Electromagnetics Research C, Vol. 7, 2009 191

REFERENCES

1. Heydari, P. and D. Lin, “A performance optimized CMOS


distributed LNA for UWB receivers,” Proc. Int. Custom Integrated
Circuits Conf., 330–333, Sept. 2005.
2. Doh, H. C., Y. K. Jeong, S. Y. Jung, and Y. J. Joo, “Design of
CMOS UWB low-noise amplifier with cascode feedback,” Proc.
European Solid-state Circuits Conf., 435–438, Sept. 2004.
3. Molavi, R., S. Mirabbasi, and M. Hashemi, “A wideband LNA
design approach,” Proceedings of the International Symposium on
Circuits and Systems, 5107–5110, May 2005.
4. Hodges, D. A., R. Saleh, and H. Jackson, Analysis and Design of
Digital Integrated Circuits, 3rd Edition, McGraw-hill, 2004.
5. Dixon, L. C. W., Non-linear Optimization, English University
Press, London, 1972.

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