1

CHAPTER 1: INTRODUCTION

Background

Due to the growing demand on wireless transceivers, much attention has been paid to

the design of high-performance RF and microwave circuits. Integrated circuit (IC)

technology is required to be able to integrate both RF and base-band functions into a single

chip due to a demand for low power and low cost transceivers. CMOS technologies are

dominant in digital circuits, while in the analog RF regime, the performance of CMOS

circuits has not been superior. MOS devices were considered slow and noisy, but as the

benefit of technology scaling, the transistor’s cut-off frequency, ωT, continues to increase,
which is desirable to improve the noise performance of the CMOS circuits [1]. So, CMOS

circuits might be capable of replacing GaAs/BiCMOS/bipolars circuits in some RF circuit

designs.

CMOS technology also has advantages in the integration of RF building blocks due to

its low cost and high degree of functionality in a single chip. Up to now, most research has

focused in the feasibility of using CMOS technology for RF building blocks such as low

noise amplifiers (LNAs), mixers, and oscillators.

One key component of any receiver chain is the LNA coming off the antennas. Since

the signal at that point is comparatively weak, an amplifier with good gain and good noise

performances is necessary [2].

Nowadays, most RF communications transceivers manufactured today utilize some

variant of the conventional super-heterodyne approach. A block diagram of conventional

super-heterodyne receiver blocks can be seen in Fig. 1.1.

 2

Figure 1.1. Conventional super-heterodyne receiver [3]

An LNA is the first main circuit in the receiving path of most wireless receivers. It
should provide enough gain to overcome the noise of subsequent stages (such as mixers), but

not so much to cause the mixer overloaded. It should also add as little noise as possible to

minimize the impact on the overall performance and should accommodate large signals

without distortion [4].

An LNA should also provide specific input impedance, such as 50 Ω, to terminate the

transmission line which delivers the signal from the antenna to the amplifier. A good input

match is even more critical when a pre-select filter precedes the LNA because such filter is

often sensitive to the quality of the terminating impedance [6].

The design of an LNA has tradeoffs among optimum gain, optimum input matching,

lowest noise figure, high linearity, and low power consumption. The design of LNA looks
relatively easy because it is made of a few components, but those tradeoffs complicate the

design. So, the simplicity appearance of LNA is misleading.

Motivation for Using Cascode CMOS Low Noise Amplifier Structure

There are four common LNA structure of single LNA that have been widely

investigated in LNA design:

(a) Resistive termination

 3

(b) 1/gm termination

(c) Shunt-series feedback

(d) Inductive degeneration

Figure 1.2. Common LNA architectures

The first topology, resistive termination, uses a resistor at the input port to provide a

termination of 50-Ω impedance. The use of the termination resistor leads to a high noise

figure for this type of LNA.

In the second topology, the 1/gm structure employs the source of common gate stage

as the termination point. The minimum theoretically achievable noise figures tend to be

around 3 dB or greater in practice [6].

The third topology, shunt-series feedback, has a high power dissipation compared to

other topologies with similar noise performance.

The last topology, inductive degeneration, has been widely use in LNA design

because it has the best noise performance among the other topologies.

It is evident that there is only one transistor in the input stage of an LNA because the

more active devices in the signal path, the more noise due to large current [9].
 4

The cascode LNA with inductive source degeneration topology has been widely used

and considered to be the best topology for LNA because it is easier to achieve input matching

for power gain and noise figure than other circuit topologies. A cascode LNA circuit with the

inductive source degeneration is shown in Fig. 3.

Figure 1.3. Cascode LNA

The cascode LNA topology isolates the input matching tank from the output resonant

load. The major issue for this topology is the heavy dependence of the performance of the

inductors, specifically on the quality factor, Q.

The Q-factor affects both the noise figure and the gain. The Q-factor of the input,

which is dependent on inductors Lg and Ls, has more influence on the noise figure than the
transconductance, gm1, of transistor M1. It doesn’t mean that M1 is not important at all, in fact,

the width of M1 has to be optimized for a better noise performance as well.

Based upon the analysis above, a two-stage cascode CMOS LNA with inductive

source degeneration is proposed for this project. Two-stage cascode LNA structure can
improve the backward isolation and provide sufficient forward gain. In addition, it will

provide a better noise performance compared to other LNA architectures as well. An inter-

stage inductor is added between the common-source stage and the common-gate stage
 5

(between M1 and M2) to tune both the power gain and the noise figure to the desire optimum

performance.

Recent LNA Research

Many authors have investigated LNA technique in the 900 MHz – 2 GHz frequency

range, and lately it is moving toward the 5 GHz range.

Due to the advance of CMOS technology that has enabled the use of CMOS

technology for the implementation of RF and microwave circuits, there are more studies on

CMOS LNA and are a few studies on Bipolar LNA lately. Most of the Bipolar LNA tends to

have a higher frequency than CMOS LNA due to the fact that bipolar technologies are faster

than CMOS technology.

Table 1.1 summarizes the results of several studies dating from 1997 – 2003. The

table has representative result from various process technologies and frequencies. While the

literatures are full of examples of LNA work in CMOS technologies, there are a few

examples of bipolar-based circuits.

Despite of the long history of LNA development, there are wide variety of noise

figures, power dissipations, and forward gains. The remarkable spread in published results

seems to suggest that a rational basis for the design of these amplifiers has not been
elucidated [2].

However, there are several common goals to be achieved in designing low noise

amplifiers. Those common goals are:

• Minimize the noise figure of amplifier

• Provide enough gain with sufficient linearity

• Provide stable 50 Ω input impedance for transmission line termination

which delivers signal from the antenna to the amplifier

 6

Table 1.1. Summaries of recent LNA studies

Author ƒo NF Gain Technology Year

(GHz) (dB) (dB)
Ainspan et al. [10] 6.25 3.5 18.3 200-mm SiGe HBT 1997
Carreto et al. [11] 1 2.9 10.3 1.2 µm BiCMOS 1998
Ray et al. [12] 1.9 2.3 10.9 Si BJT 1999
Tsang et al. [13] 5.8 4 11.5 Si BJT 2001
Kim et al. [14] 2.4 2.4 19 0.5 µm 1999
Yang et al. [4] 1.9 1.4 20 0.35 µm 1999
Huang et al. [15] 2.4 2.5 19.9 0.35 µm 2001
Zhao et al. [9] 2 2.3 18.06 0.6 µm 2001
Yang et al. [1] 2.4 2.4 20 0.25 µm 2001
Fouad et al. [16] 1 2.7 21.6 0.5 µm 2001
Long et al. [17] 2.4 0.76 12.9 0.18 µm 2002

A good input match is even more critical when a pre-select filter precedes the LNA,

because such filters are often sensitive to the quality of their terminating impedances [6].

Power consumption constraints will also make the design more complicated,

especially for the use of portable system.

Based on the discussions above, the two-stage cascode LNA is designed with the

following proposed specifications as summarized in Table 1.2.

Table 1.2 Proposed LNA specifications

Process TSMC 0.18

Frequency 5 GHz
Power Supply 1.8 V
Noise Figure < 3 dB
Gain > 20 dB
Power Dissipation < 10 mW
 7

The TSMC 0.18µm process is the fastest CMOS process that available for students at

Iowa State University. A supply voltage of 1.8V is desired to design a low power circuit. The

noise figure of lower than 3 dB is a standard requirement in LNA design and having a high

power gain LNA is one of the goals of this project.

 8

CHAPTER 2: LOW NOISE AMPLIFIER DESIGN

Circuit Topology

The cascode LNA structure design has been the chosen structure because it is easy to

satisfy both noise and power requirement. Usually at the input stage of an LNA, there is only

one transistor because if there are more active devices in the signal path, there will be more

noise due to large currents.

A two-stage cascode structure with inductive source degeneration is shown in Fig.

2.1.

Figure 2.1. Two-stage cascode LNA

 9

The two-stage cascode structure can improve the backward isolation and provide

sufficient gain. The only problem with this topology is the high dependence of the Q-factor

of the input circuit. The performance of the LNA will be degraded because of the poor Q-

factor of the inductors.

In the two-stage cascode structure, the noise contributed by transistor M3 is neglected

in the analysis, because the noise contributed by the stages following a high gain stage can be

neglected.

The first stage of the LNA is a cascode amplifier formed by transistors M1 and M2.
Transistor M0, and resistors Rb1 and Rb2, provide a biasing for the LNA. Transistor Mbias is a
current mirror with M1 and Rb1 sets the current of the bias circuitry, which generates the bias

voltage at the gate of transistor M1. Resistor Rb2 prevents the input signal from flowing back

to the bias circuitry. Lg and Ls are used to provide input impedance matching of 50Ω.

Design and Analysis

The input section of inductive degeneration LNA is shown in Fig. 2.2.

Figure 2.2. LNA input stage

 10

Table 2.1. Process and design parameters

Symbol Parameter

W Transistor Width
L Transistor Length
Lg Gate input inductor
Ls Source degeneration inductor
ID Transistor channel current
Cgs Transistor gate-source capacitance
Cgd Transistor gate-drain capacitance
gm Transistor transconductance
gmb Transistor bulk transconductance
gdo Transistor Output conductance
µn Electron Mobility
Cox Gate unit capacitance
γ Channel current noise factor
Rs Source Resistance
ωo Angular frequency of operation

The input impedance of the circuit (neglecting Cgd and gmb) is given by [4], [18]:

1 g L
Zin1 = jωLt + + m1 s (2.1)
jωCgs1 Cgs1
where

Lt = Lg + Ls (2.2)

At the resonance (operating) frequency:

1
ωo = (2.3)
Lt C gs1
 11

The impedance of the circuit must be equal to the source impedance, Rs, to have impedance

matching. These matching criteria give

Ls g m1
Rs = (2.4)
C gs1
and

ω o 2 ( Lg + Ls )C gs1 = 1 (2.5)

The quality factor for the input circuit is then

1 1
Qin = = (2.6)
L 2 Rs ω o C gs
( Rs + g m1 s )ω o C gs
C gs

The noise contributed by M2 has a minor influence to the noise behavior of LNA, so

its contribution to the total noise of the LNA is disregarded in the analysis.

The noise figure of the LNA can be determined by analyzing the circuit in Fig. 2.3. In

high speed applications, channel thermal noise and induced gate current noise are the two

most important noise sources in the MOS devices.

Figure 2.3. Equivalent circuits for input stage noise calculations [6]
 12

−−
In Fig. 2.3, Rl, Rg, and id2 represent the series resistance of inductor Lg, gate resistance

of NMOS device, and the channel thermal noise of the device, respectively.

The noise analysis on the circuit neglects the contribution of subsequent stages to the

amplifier noise figure.

The noise factor of the LNA is given by [6],[14]:

2
R Rg ω 
F = 1+ l + + γg d 0 Rs  o  (2.7)
Rs R s  ωT 
where
g m1
ωT = (2.8)
C gs1
ωT
g m1Qin = (2.9)
2ω o Rs
and γ for long channel devices satisfy

2
≤ γ ≤1 (2.10)
3
Under the condition that the drain current is constant, the transconductance of the transistor

M1 is

W1
g m1 = 2 I D µ n C ox (2.11)
L1

and the long-channel equation for Cgs is

2 W
C gs = C ox (2.12)
3 L

It is assumed that the equation (2.11) still holds for the short-channel devices. The optimum

size of transistor M1 to generate minimum noise figure can be found out by differentiated the

equation (2.7) in terms of W1.

 13

3 1
W1 = (2.13)
2 ω o Rs Lt C ox

The dominant term in equation (2.7) is the last term, which arises from channel

thermal noise [6]. We can improve noise figure and reduce power dissipation by reducing

gdo, which can be done by scaling down M1 without modifying ωT. However, equation (2.7)

assumes that the amplifier operates at the series resonance of its input circuit. So, Lg needs to

be increased to compensate for the reduction of gdo to maintain a constant resonance

frequency.

Another step is to design the common-gate stage. The common-gate stage input

impedance is given by [14]:

1
Z in 2 = (2.14)
g m 2 + jω o C gs 2

Because both the input impedance of the common-gate stage and the output

impedance of the common-source stage are capacitive, a series inductor, La, can be added to

improve the matching. The power gain and noise figure performance of the LNA is improved

by adding a series inductor, but the Miller effect of Cgd1 if also increased, so the real part of

input impedance will be smaller. The input reflection coefficient (S11) will become worse

[15]. Optimization should be done by simulations to obtain new values of Lg, Ls, and La. The

complete two-stage cascode LNA with La can be seen in Fig. 2.4.

 14

Figure 2.4. Two-stage cascode LNA with intermediate inductor

The final step in LNA Design is to determine the output matching network. A shunt

RLC matching network is used at the output node of LNA to match the 50Ω termination

point.

Figure 2.5. Shunt RLC network

 15

The impedance of the shunt RLC network is

1
Z ( jω ) = (2.15)
1
G + jω C +
jω L

where R = 1/G. At resonance,

1
jω C + =0 (2.16)
jωL

so, the resonant frequency of an RLC tank circuit is found to be

1
ωo = (2.17)
LC

The linearity and the stability of the device should also be considered carefully by looking at

the stability plot from the simulation.

Spiral Inductor Modeling

Devising accurate models for on-chip inductors has been one of the most important

issues in RF IC design. In conventional IC technologies, inductors are not considered as

standard components like transistors, resistors, or capacitors, whose equivalent circuit models

are usually included in the process description. However, this situation is rapidly changing as

the demand for RF IC’s continues to grow [22]. In the past several years, several approaches

for modeling inductors on silicon have been reported. Most of the approaches are relatively

inaccurate over a wide range of layout dimensions and process parameters because these

approaches are based on numerical techniques, curve fitting, or empirical formulae. A

compact physical model is required to design and to optimize the spiral inductors.

The difficulty of physical modeling stems from the complexity of high-frequency

phenomena such as the eddy current effect in the interconnects and substrate losses in the
 16

silicon [22]. So the proper modeling of inductors at RF frequencies translates to both

inductance and loss modeling [24].

Besides the ohmic losses due to the series resistance, CMOS integrated inductors

exhibit serious substrate and dielectric losses, which become dominant at high-frequencies.

This is mainly due to the relatively high conductivity of the CMOS substrate [24].

Figure 2.6. Square spiral inductor

The total inductance for a square spiral inductor is [25],

µo   l 
L= l  ln  − 0.2 − 0.47 n +
4π   n( w + t 
  2  
 − 1 +  4nd  4nd +
+
   l 
(n − 1) ln 1 + 
l
 + 
 +  l   (2.18)
  +
 4nd  4nd +    l
   

(3n − 2 N i − 1)(N i + 1)
d + = (w + s ) (2.19)
3(2n − N i − 1)

where, µ o is conductor permeability, l is conductor length, n is number of turns, w is width of

the segment, t is thickness of the metal, d+ is average distance for constituting factors of

positive mutual inductance, s is spacing between segments, and Ni is integer of part n.

Physical models of spiral inductors are shown in Fig. 2.5 and 2.6, which contain all

the parasitic elements.

 17

Figure 2.7. Traditional/simplified π spiral inductor model

Figure 2.8. Lumped physical model of a spiral inductor

Ls and Rs are the series inductance and resistance of the spiral and underpass (metal

lines). The overlap between the spiral and the underpass allows direct capacitive coupling

between the two terminals of the inductors. This feed-through path is modeled by the series
 18

capacitance, Cs [22]. Cox is the oxide capacitance between the inductor and the substrate. Csi

and Rsi are the capacitance and the resistance of the substrate.

An estimate for the series resistance is given by:

l
RS = (2.20)
wσδ 1 − e δ 
−t

 
where σ is the conductivity of the material, l is the total length of the winding, ω and t are the

width and thickness of the interconnect, and δ is the skin depth.

2
δ= (2.21)
ωµ Oσ

The shunt capacitance Cs is:

ε ox
C S = nw 2 (2.22)
t ox

where tox is the thickness of the oxide.

Cox can be approximated with a simple parallel plate formula, which is given by:

ε ox
C ox = wl (2.23)
t ox

The capacitance and the resistance of the substrate can be described as follow:

2
R Si ≈ (2.24)
wlG sub

wlC sub
C Si ≈ (2.25)
2
where Gsub and Csub are fitting parameters that are constant for a given substrate distance of

the spiral to the substrate. The fitting parameter Gsub has a typical value of about 10-7 S/µm2

and Csub has a typical range between 10-3 and 10-2 fF/ µm2.
 19

The quality factor of a system under sinusoidal excitation at frequency ω is defined

by [23]:

energy stored
Q = 2π (2.26)
average power dissipated

The above equation is the most fundamental equation to describe Q, because it says

nothing specific about what stores or dissipates the energy.

The Q-factor of the RLC network at resonance can be described as follow [23]:

1 12 C (I pk R )
2
E R
Q = ω o tot = 2
= (2.27)
Pavg LC 12 I pk R L
C
R
Q= = ω o RC (2.28)
ωo L
The quantity L C has the dimensions of resistance and is sometimes called the
characteristic impedance of the network.

The performance of spiral inductors is determined by the Q-factor. Due to parasitic

effects, the performance of on-chip inductor is quite low. By choosing wide inductors, it is

possible to obtain substantial Q improvements.

In this project, a custom computer-aided-design tool called Analysis and Simulation

of Inductors and Transformers for IC’s (ASITIC) was used to model the spiral inductors and

to extract the parameters. It is a user-friendly computer-aided-design (CAD) tool designed to

aid the RF circuit designer in the designing, optimizing, and modeling of the spiral inductor

and transformers [27]. ASITIC can analyze the general magnetic and substrate coupling

between different parts of the circuit. It can also extract the parasitic effects of substrates and

metal lines. ASITIC used a simplified π model to design and to analyze inductors for Si

RF/microwave circuits. The important part of using this program is editing the technology

file which describes specific IC process.

 20

Electrostatic Discharge (ESD) Design

Protection from ESD is a common concern in the RF system design. If adequate ESD

survivability cannot be provided without intolerable degradation of RF characteristics, then

RF CMOS circuits will forever remain a useless academic activity [20].

Electrostatic discharge phenomena can produce a voltage in the range of kV which is

much greater than the gate breakdown voltage of MOSFET. To avoid ESD events, protection

schemes are used to discharge the excessive charge. A simple ESD protection scheme is

presented in Fig. 2.8.

Figure 2.9. ESD protection scheme

The ESD protection relies on a diode becoming forward biased and providing low-

impedance path to pull the excessive charge away from the MOSFET. The ESD blocks will

be treated as parts of the LNA and will be compensated during the simulation.
 21

CHAPTER 3: SIMULATION AND LAYOUT

Scattering Parameter

The scattering parameter has an important role in RF systems because the practical

system characterizations can no longer be done using simple open or short circuit

measurements such as in low frequency applications. At high frequencies, discrete

components such as resistors, inductors, and capacitors start to deviate in their electric

responses from the ideal low-frequency behavior [21].

Scattering parameters define the input-output relations of a network in term of

incident and reflected power waves.

Scattering parameters can be measured using a program like SPICE, under conditions

of perfect matching on input and output nodes. The setup for the SPICE simulation can be

seen in the Fig. 3.1.

Figure 3.1. Scattering parameters measurement using SPICE program

 22

The definition of the S-parameters shown on the figure above is as follow:

S11 = Input Return Loss

S12 = Reverse Isolation (Reverse Power Gain)

S21 = Forward Power Gain

S22 = Output Return Loss

The S-parameters can be determined using the equations below [22]:

V1 − I1 Z 0 Vm1
S11 = = (3.1)
V1 + I 1 Z 0 a 2=0
Es

V2 − I 2 Z 0 V2
S 21 = = (3.2)
V1 + I1Z 0 a 2 =0
Es

V2 − I 2Z 0 Vm 2
S 22 = = (3.3)
V2 + I 2 Z 0 a1= 0
Es

V1 − I 1Z 0 V1
S12 = = (3.4)
V2 + I 2 Z 0 a1= 0
Es

where

a1 = V1 + I 1 Z1 (3.5)

a2 = V2 + I 2 Z 2 (3.6)

In AC analysis, Es is set equal to one volt. Then the magnitude and phase of the four

voltages indicated by the equation above give the magnitude and phase of the scattering

parameters.
 23

Two-Port Network Simulation

The LNA is treated as a two-port network since it only has input and output ports.

The setup for s-parameter simulation for the LNA on Cadence is shown in Fig. 3.2. Cadence

is the most widely used IC design tool. Using Spectre simulator provided by Cadence, s-

parameters and noise figure of the LNA can be simulated. By using a port instance at each of

its input and output nodes, the S-parameter simulation can be performed. A 50-Ω termination

is set on each port.

Figure 3.2. S-parameter measurement setup in cadence for two-port network

Schematic Simulation

The actual LNA schematic with ideal inductors used in the Cadence simulation is

shown in Fig. 3.3 below. DC blocking capacitors are put on both input and output ports. Both

the capacitors are included in the input and output matching calculations.

The complete simulation setup on Cadence can be seen in Fig. 3.4. As we can see in

Fig. 3.4, there are four square devices on every pin of the LNA. Those blocks are ESD blocks

that will prevent any ESD event toward the LNA.

 24

A capacitor is put on every pin of the LNA to compensate for the Ground-Source-

Ground (GSG) pad that will be used in the layout and fabrication. The GSG pad will be

discussed further in the layout section.

Figure 3.3. Actual LNA schematic on cadence

Figure 3.4. Actual LNA simulation setup in cadence

 25

The noise figure (NF) of the low noise amplifier without the intermediate inductor

(La)” is 5.39 dB. The intermediate inductor is varied to get a better noise figure.

The NF of the LNA with La varying from 0.5 nH to 5 nH is presented in figure 3.6.

Figure 3.5. NF Performances with various La

Table 3.1. NF performance with various La

La (nH) NF (dB)

0 5.39
0.5 5.01
1 4.62
1.5 4.24
2 3.88
2.5 3.53
3 3.22
3.5 2.95
4 2.71
4.5 2.53
5 2.42
 26

From the Fig. 3.5 above, it is evident that the greater value of the intermediate

inductor, the better the noise performance can be. The forward power gain is also measured

with various La ranging from 2 nH to 5 nH.

Table 3.2. Forward gain performance with various La

La (nH) S21 (dB)

2 17.28
2.5 19.2
3 21.64
3.5 24.89
4 29.33
4.5 32.06
5 27.88

Figure 3.6. Power gain performances with various La

 27

By sweeping the La, the Noise Figure could be decreased below 3 dB and the power

gain could be increased above 20 dB. Considering the parameters above, a 4.2 nH inductor is

chose to be used as intermediate inductor for the final design of the LNA since it would give

the best results with respect with the parameters above.

The S-parameters and the noise figure performance of the two-stage cascode LNA

can be seen from the figure below.

Figure 3.7. Schematic simulation performances

Figure 3.8. Schematic simulation NF performance

 28

The schematic simulation yields good s-parameters performance. The two-stage

cascode LNA has good power gain (29.4 dB) and noise figure (2.63 dB) while consuming 7.2

mW of power, which are much better than the proposed specifications requirement.

The next step of the simulation is to test the durability of the LNA due to the process

and temperature variations. The current results of the LNA is achieved by using a typical

TSMC 0.18 process at the room temperature of 27o. A good LNA should perform well under

any process variations and temperatures.

The LNA will be simulated by using slow, typical, and fast TSMC 0.18 processes,

while the temperature is varied from low to high temperature. The major difference of slow,

typical and fast TSMC processes is in the carrier mobility, although there are also some

minor differences in other electrical parameters.

The performances of the LNA using different TSMC 0.18 process at temperatures

ranging from -20o C to 50o C are summarized in table below.

Table 3.3. LNA schematic simulation performance using slow process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -9.94 -50.35 31.15 -27.04 2.97

-10 -12.65 -50.62 30.74 -25.48 2.94
0 -25.65 -50.98 30.23 -23.65 2.9
10 -17.95 -51.36 29.69 -22.95 2.86
20 -17.75 -51.77 29.13 -20.98 2.83
27 -16.52 -52.06 28.73 -20.33 2.81
35 -14.97 -52.38 28.27 -19.72 2.78
40 -14.1 -52.58 27.98 -19.4 2.77
50 -12.64 -52.96 27.44 -18.87 2.75
 29

Table 3.4. LNA schematic simulation performance using typical process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -9 -48.7 31.7 -26.12 2.78

-10 -11.36 -49.03 31.16 -28.84 2.73
0 -14.38 -49.27 30.77 -26.93 2.7
10 -18.04 -49.58 30.31 -24.8 2.68
20 -21.26 -49.91 29.82 -23.11 2.65
27 -21.35 -50.15 29.47 -22.17 2.63
35 -19.53 -50.43 29.06 -21.3 2.62
40 -18.23 -50.6 28.8 -20.84 2.6
50 -15.99 -50.94 28.23 -20.1 2.59

Table 3.5. LNA schematic simulation performance using fast process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -7.24 -47.74 31.3 -25.78 2.57

-10 -8.91 -47.8 31.09 -28.32 2.55
0 -10.9 -47.93 30.81 -29.45 2.53
10 -13.28 -48.11 30.47 -28.3 2.51
20 -16.08 -48.34 30.09 -26.35 2.5
27 -18.25 -48.51 29.8 -25 2.48
35 -20.57 -48.72 29.47 -23.87 2.47
40 -21.55 -48.85 29.25 -23.22 2.47
50 -21.52 -49.11 28.82 -22.14 2.45

The schematic simulations with different TSMC 0.18 processes and temperatures

yield good results. The LNA works well under stress, even though some of the performance
 30

degraded because of the process and temperature variations, but those performances are still

exceed expectations.

The s-parameters and noise figures performance of the LNA schematic simulation

using slow and fast process at room temperature (27o) are presented in figures below.

Figure 3.9. Schematic simulation performances using slow process at room temp.

Figure 3.10. Schematic simulation performances using fast process at room temp.
 31

A table comparison of the schematic simulation results of the two-stage cascode LNA

and some recent reported CMOS LNA used as references are summarized in Table 3.6.

Table 3.6. Comparison of LNA’s performances

ƒo VDD NF S11 S12 S21 S22 PD

Author
(GHz) (V) (dB) (dB) (dB) (dB) (dB) (mW)
Fouad [16] 1 2.2 2.74 -31.8 -42.5 21.6 -42.1 29.2
Yang [8] 1.9 1.5 1.4 -35 - 20 -32 6.5
Zhao [9] 2 3.3 2.3 - -44.79 18.06 - 33.94
Kim [14] 2.4 3 2.4 -10 - 19 - 9
Yang [6] 2.4 3.3 2.4 -19 -35 20 -21 7.2
Huang [15] 2.4 2 2.5 - -47.8 19.9 - 14.7
Long [17] 2.4 1.2 0.76 -22.4 -48.9 12.9 -21.6 2.4
This Work 5 1.8 2.63 -21.35 -50.15 29.4 -22.17 7.2

LNA Layout and Verification

The next thing to be done after the schematic design and simulation were completed

is schematic layout. The layout is created and checked using design rule check (DRC) and

layout versus schematic (LVS) verification tools to make sure the layout did not violate any

design rules and it matched with the schematic.

Layout has a very huge affects on the performance of the radio frequency circuits,

therefore, careful attention is being place on several areas such as:

• Transistor/device matching

• Spiral inductor layout

• Electromigration

Multi finger and common centroid techniques are used in device (transistor) layout

[28]. It gives advantages such as decreasing the noise figure and reducing mismatch of
 32

device parameters. The spiral inductors are isolated and place at least 50 µm from other

devices to make sure that they are not coupling with any other devices.

The electromigration and metal fusing rules must be followed since the design draw

currents in mA range. Electromigration can cause failures especially in the narrow

interconnect. When a large current passes through a metal trace, the metal trace can heat up

and open (fuse), or atoms within the trace can move (electromigration) [29]. A trace of high

current path has to be widened to avoid the electromigration issue.

The parameters of the on-chip spiral inductors designed using ASITIC as explained in

chapter 2 are shown in Table 3.7 below.

Table 3.7. Parameters for the on-chip inductors

Model Parameter Lg Ls La Ld Lout

L (nH) 5.85 1.3 4.2 5.4 1.1

Q (Quality Factor) 8.5 13.3 13.9 12 11.8
Outer Edge (µm) 329 155 242 289 145.5
Width (µm) 15 15 15 15 15
Spacing (µm) 1.5 1.5 1.5 1.5 1.5
Turns 4 3.5 5 4.5 3.5
R (Ω) 3.75 2.88 5.42 4.36 2.79
Cs1 (fF) 137.2 43.5 99.75 124.2 39.22
Cs2 (fF) 124.1 36.7 87.6 109.4 32.87
Rs1 (kΩ) 1.24 0.5 0.68 0.93 1.4
Rs2 (kΩ) 2.833 2.89 3.38 3.26 1.7

Ground-source-ground pads are used in the layout because three-pin Air Coplanar

Probe by Cascade Microtech will be used in the testing. The GSG pad is made of poly and

metal 1 to metal 6 stacking on top of each other, so that it is easy in the wiring aspect, which

will provide flexibility in a connection with any metal layer or poly.

The layout of the GSG pad can be seen in the figure 3.11.
 33

Figure 3.11. Layout of GSG pad

Each square of the pad has a size of 75 µm x 75 µm with spacing of 25 µm between

pads. Table 3.8 summarizes the capacitance parameters form by TSMC process layers that

are used in GSG pad.

Table 3.8. Capacitance parameters between process layers

Layer Capacitance (aF/µm2)

Poly - M1 62
M1 - M2 37
M2 - M3 37
M3 - M4 38
M4 - M5 37
M5 - M6 35

The capacitance for a square of the GSG pad is estimated at about 1 pF. During the

schematic simulation of the LNA, a 1 pF load was added to each of the ports to compensate

for the GSG pad.

The other important issue during the layout phase of LNA is the metal filling

procedure. Metal filling is needed for a chemical issue in the fabrication process. The metal

filling requirement might be different for different process or vendor. The metal filling might

cause short connection to the circuit that will hurt the circuit performance. The following are

some rules about the metal filling for the layout using a TSMC 0.18µm process.
 34

Table 3.9. Metal filling requirement

Layer Percentage of the total active area

M1- M6 40% (for each metal layer)
Poly 14%
MIM Cap 3%

The complete layout for the two-stage cascode LNA with the metal filling is shown in

Fig. 3.11

Figure 3.12. Two-stage cascode LNA layout

The layout of the LNA passed the DRC rules and the LVS test. During the extraction

of the layout, the inductors are left out because TSMC 0.18 process does not have a model

for inductor, so the layout of the inductor can not be recognized during the layout extraction.
 35

Post Layout Simulation

The post layout simulation is performed to check how well the LNA performs with all

the parasitic models included. How the layout is designed might be critical in affecting the

actual performance of the design. In order to get an idea of how the design would actually

work after the fabrication, the post layout simulation is performed.

External π inductors are added to the extracted view of the LNA so that the post

layout simulation could be performed.

The s-parameters and noise figure performance from the extracted view using typical

process at room temperature are shown in Fig. 3.13 and 3.14.

Figure 3.13. Post layout simulation performances

 36

Figure 3.14. Post layout simulation NF performance

The extracted layout was also simulated using different processes at low and high

temperature to test its durability under stress.

Table 3.10. LNA post layout simulation performance using slow process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -24.87 -58.49 -21.71 -20.85 1.77

-10 -30.1 -58.78 21.21 -21.25 1.76
0 -35.8 -59.06 20.84 -21.67 1.75
10 -30.97 -59.32 20.42 -22.09 1.75
20 -26.33 -59.57 20.01 -22.52 1.74
27 -22.83 -59.73 19.73 -24.14 1.74
35 -22.25 -59.91 19.42 -23.2 1.74
40 -21.29 -60.01 19.23 -23.42 1.74
50 -19.74 -60.2 18.85 -23.88 1.74
 37

Table 3.11. LNA post layout simulation performance using typical process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -14.95 -55.96 22.9 -19.71 1.55

-10 -16.27 -56.21 22.5 -20.08 1.55
0 -17.61 -56.45 22.12 -20.46 1.55
10 -19.01 -56.68 21.73 -20.86 1.54
20 -20.32 -56.89 21.36 -21.26 1.54
27 -21.14 -57.04 21.1 -21.55 1.54
35 -21.89 -57.19 20.81 -21.89 1.54
40 -22.24 -57.28 20.63 -22.11 1.54
50 -22.61 -57.45 20.28 -22.55 1.54

Table 3.12. LNA post layout simulation performance using fast process

Temp (˚C) S11 (dB) S12 (dB) S21 (dB) S22 (dB) NF (dB)

-20 -10.08 -53.69 23.71 -18.51 1.37

-10 -10.84 -53.88 23.37 -18.87 1.37
0 -11.6 -54.07 23.03 -19.22 1.37
10 -12.38 -54.56 22.7 -19.58 1.37
20 -13.15 -54.53 22.37 -19.95 1.37
27 -13.7 -54.54 22.14 -20.21 1.37
35 -14.31 -54.67 21.88 -20.52 1.37
40 -14.7 -54.74 21.72 -20.71 1.37
50 -15.45 -54.88 21.4 -21.11 1.37

The s-parameters and noise figures performance of the extracted layout using slow

and fast process at room temperature (27o) are presented in the figures below.
 38

Figure 3.15. Post layout simulation performances using slow process at room temp.

Figure 3.16. Post layout simulation performances using fast process at room temp.

The extracted layout still performs well under different process and low-high

temperature. The comparison of the schematic and extracted layout performances under

typical process at room temperature are summarized in Table 3.13 below.

 39

Table 3.13. Comparison of schematic and post layout simulations performances

Process TSMC 0.18µm TSMC 0.18µm

Power Supply 1.8 V 1.8 V
Operating Frequency 5 GHz 5 GHz
S11 (dB) -21.35 -21.14
S12 (dB) -50.15 -57.04
S21 (dB) 29.4 21.1
S22 (dB) -22.17 -21.55
Noise Figure (dB) 2.63 1.54
Current (mA) 4mA 4 mA
Power Dissipationn (mW) 7.2 7.2

Both schematic and post layout performances are comparable to each other. The

noticeable changes on the post layout performance are the power gain and the noise figure.

The power gain is lower by about 8 dB to 21 dB, which is still a high gain and still meets the

proposed specification. The noise figure of the post layout simulation was actually improves

over the schematic result.

Test Inductors

The purpose of having test inductors in the chip is to characterize the performance of

the inductors used in this project that are designed using ASITIC, and also will be used to

map out different inductor sizes for future IC design use.

Test inductors are designed ranging from 1 nH to 6 nH, with the following

parameters.
 40

Table 3.14. Test inductors parameters

Model Parameter Ind-1 Ind-2 Ind-3 Ind-4 Ind-5 Ind-6

L (nH) 1 2 3 4 5 6
Q (Quality Factor) 11 17 15 16 13 8
Outer Edge (µm) 141 186 211 241.5 275.5 310.5
Width (µm) 15 15 15 15 15 15
Spacing (µm) 1.5 1.5 1.5 1.5 1.5 1.5
Turns 3.5 3.5 4.5 4.5 4.5 4.5
R (Ω) 2.74 3.17 4.68 4.722 4.47 4.143
Cs1 (fF) 39.5 65.02 78.52 95.28 121.2 135.1
Cs2 (fF) 32.5 51.11 66.97 82.25 102.8 122.9
Rs1 (kΩ) 1.975 0.072 0.233 0.424 0.84 1.132
Rs2 (kΩ) 0.87 3.525 3.565 3.5 3.143 3.208

Chip Layout

The final chip layout contains the following:

• LNA layout

• Test inductors layout

• Calibrations pads layout

The requested total die area for this project is 2.5 mm x 2.5 mm. The LNA layout

consumes area of 1.5 mm x 1.5 mm. The rest of the die area is used for calibration pads and

test inductors. The calibration pads might be used during the testing of chip to calibrate the

network analyzer. The layout was sent to MOSIS who provides free fabrication for

educational progam.
 41

Figure 3.17. Final LNA chip layout

 42

CHAPTER 4: DEVICE TESTING

Overview

The LNA and test inductors were tested using a network analyzer which can perform

a frequency sweep in the GHz range. Two three-pin air coplanar probes were used for the

input and output pads. A power supply was used to supply the voltage requirement for the

LNA. The first important step in the measurement is to calibrate the network analyzer for the

purpose of the testing.

Figure 4.1. Photomicrograph of LNA chip

 43

Inductors Measurement

The first measurements taken on the chip were to determine the performance of the

inductors. Inductors are the most important segments that compose the LNA, and functional

inductors are essential in LNA design. Pad capacitance is de-embedded by subtracting out the

open circuit structure from the spiral structure.

Figure 4.2. Photomicrograph of test inductor

Two GSG probes are put on both ends of an inductor, and the frequency is swept

from 1 GHz to 6 GHz to test the performance of the device over that desired frequency. The

measured results of all test inductors from the network analyzer are imported to ADS

software. The results are then de-embedded and plotted using ADS. The measured

impedances of the test inductors are plotted on Smith charts. Smith chart is a graphical

method for simplifying the complex math needed to describe the characteristics of

microwave components. The top half of the Smith chart represents the inductance (+j) and

the bottom half of the Smith chart represents the capacitance (-j) mapping of impedance
 44

plane. Figures below show the measured impedances of all test inductors on the Smith charts.

The structural details of test inductors are shown in Table 3.14.

Figure 4.3. Impedances of test inductors

 45

From the Fig. 4.3, we can see circles on of every Smith chart which represents the

complex impedance. The important results from the measurement of the inductors are the

circles on the top half of the Smith charts. The impedance circles do not start from the middle

point of smith charts because there is a series resistance on the input which shifts the

impedance circle to the right for each inductor. Since, there is a 50 Ω termination on each of

the probe, the load resistance must be removed from the total measured impedance of the test

inductors. From the impedances on the top half of the smith chart, the inductances and the Q-

factors for each of the test inductor can be extracted.

Figure 4.4. Extracted Q-factor and inductance of Ind-1

Figure 4.5. Extracted Q-factor and inductance of Ind-2

 46

Based on some of the test inductors extraction results are shown in Fig. 4.4 and 4.5.

We see that the test inductors only work at frequencies above 1 GHz and do not show any

inductance below 1 GHz. The inductors should have a constant value at lower frequency.

Measurements were taken on multiple test inductors on different dies, and all the

measurement shown the same characteristics.

From the extraction results, the test inductors show zero inductance at 1 GHz and

there is no region of flat response as we would expect. Most of the test inductors resonate at

frequency of 3 GHz which is much less than expected since all the inductors were designed

to work at the 5 GHz range.

Excessive parallel capacitance can reduce the resonant frequency of an inductor.

Also in a typical CMOS IC process, the underlying substrate contributes losses to the

performance of an inductor. The parasitic loss will decrease the resonance frequency and

inductance that can be achieved. Eddy current losses also need to be taken into account. The

eddy current losses are caused due to the nonzero resistivity of the metal layers that form the

inductor. Some loss can be attributed to layout of the inductors as well. Metal routing used to

connect the test inductors to the GSG pads might affect the performance of inductors and it is

not included in the calculation by ASITIC.

Clearly, further optimization seems to be needed in the design of on-chip spiral

inductor by varying its design parameters to achieve better results. This project will not go in

depth to optimize and to learn the design of spiral inductors because the purpose of this

project is to map out the inductance of simple spiral inductors designed using ASITIC.
 47

LNA Measurement

The final step of this project is to test the performance of the LNA. As we already

know, the LNA requires inductors for the noise and input-output impedance matching. An

accurate modeling of the inductor is important in the design of the LNA.

From the previous section, the test inductors have been characterized, and most of

them function up to 2 GHz in frequency. On the other hand, the LNA was designed to work

at 5 GHz. Because of the poorly designed inductors, the performance of the LNA will be

distorted.

The first measurement taken on the chip is the dc level measurement. A problem on

the dc level will cause problems to the rest of the circuits. A power supply was used to

provide the supply voltage of 1.8 V to the LNA while a multi-meter was used to measure the

total current consumption of the LNA. The total current consumption was measured to be

3.18 mA in comparison to 4 mA of simulated total current consumption. A lower total

current can be caused by the inaccurate poly sheet resistance of the biasing source after the

fabrication which can be attributed to process variation. Also, the metal routing in the chip

will cause a loss of current.

Based on the dc level measurement, the performance of the LNA might be degraded

because of lower power consumption. The measured s-parameters of the LNA are shown in

Fig. 4.10 below. The frequency was swept from 1 GHz to 6 GHz to see the performance of

the LNA over a broader range of frequency.

 48

Figure 4.6. Measured s-parameters performances of LNA

From the figure above, the s-parameters performance of the LNA at 5 GHz is

summarized in Table 4.2.

Table 4.2. Measured s-parameters performance of LNA at 5 GHz

S11 -4.266 dB
S12 -36.354 dB
S21 -32.774 dB
S22 -5.24 dB

We can clearly see that the LNA does not have a positive gain at 5 GHz, which means

that the LNA does not work as an amplifier at that frequency. In fact, the LNA will not

amplify any input signal. By looking at Fig. 4.10, the LNA does not have any positive gain in

the range of 1 GHz to 6 GHz. The main cause of this problem is the on-chip passive spiral

inductors of the LNA. From the previous section, the performance of the on-chip passive
 49

inductors have been tested and discussed. Due to the poor performance of the inductors, the

performance of the LNA is affected.

As we can see from the measured results of the test inductors, most of the on-chip

passive inductors work up to frequency of 2 GHz, which are much lower than the design

frequency of the LNA.

As for the performance below the frequency of 2 GHz, the LNA still shows poor

performances. In LNA design, input and output matching are crucially important. Without

precise calculation, it is impossible to achieve a good input and output match for the LNA.

Due to the lack of testing setup for noise measurement, the noise figure performance

of the LNA was not tested. But based on the testing results of the LNA, it can be said that the

LNA will not have a good NF performance and is probably meaningless.

 50

CHAPTER 5: CONCLUSION

Summary of Work

A low power 5-GHz two-stage cascode CMOS LNA has been designed and simulated

using CMOS TSMC 0.18µm technology. It is proven that CMOS technology has the same

capability to compete with GaAs/BiCMOS/bipolars technology in designing high frequency

circuitries. Two-stage cascode topology with intermediate inductor has the capability in

designing low power, high gain, and low noise LNA.

Although the fabricated LNA does not work as we expect; an important lesson is

learned during the design course of this project. The need of well characterized and well

designed inductors is a must in the RF world, especially in designing LNA which is mainly

consist of inductors. The use of on-chip passive inductors will consume more die area which

will cause more production cost.

Recommendations for Future Work

An alternative in designing LNA instead of using a spiral inductor is the use of an

active inductor. Active inductor can have a higher Q-factor compared to on-chip passive

inductor. The use of active inductor also will reduce the use of die area significantly which

will be a benefit in cost reduction. However, the active inductor has a limited operating

frequency. The design of active inductor has only been demonstrated up to 3 GHz frequency

range. Active inductors also have a higher noise figure compared to passive inductor, and it

consumes more dc power, which is a drawback in the design of low power circuitry.

The use of other commercial tools, such as HFSS and ADS, which rely on

electromagnetic simulation, must also be utilized in designing passive inductors. The

drawback of using commercial tools is it not always available to anyone because of its price,
 51

and it is more complicated to use compare to any simple and free/cheap CAD tools that only

required the user to input any parameters necessary. Aside from those, performing

electromagnetic simulation is time consuming which often takes few hours to days.

Some design processes also include inductor instances in their library, although the

size of the inductor is limited to only a few choices. In circuit design that uses large number

of inductors, it will be really tough to do any necessary tweaking.

The extension of this project would be designing different blocks of the receiver, such

as mixer and oscillator. It would be great learning experiences in designing such blocks with

CMOS technology. The capabilities of CMOS technology have made the designing of high

frequency circuitries possible for low cost and low power consumption transceivers and in a

very high demand.

 52

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 54

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 56

ACKNOWLEDGEMENTS

My sincere thank goes out to my major professor, Dr. Gary Tuttle, for his support and

guidance throughout my research, and I express my thanks to Dr. Robert Weber and Dr. Alan

Constant for serving on my thesis committee.

I would also like to acknowledge the Iowa State University’s Analog and Mixed-

Signal VLSI Center, especially Dr. Weber and his students, Mike Reid, Jo-Yi Foo, Jinson

Chan, and Feng Chen, for their assistance, technical advice, and as well as friendship.

My thank also goes to MOSIS Educational Program and Texas Instruments for

providing free fabrication service and funding for this project. Without their support, this

valuable experience would not have been possible.

Finally, I would like to express my deepest gratitude to my family, especially my

parents, Gunawan Tanadi and Darmawaty Sie, my brothers, Tris Tanadi and Agus Leonardo,

and my sister, Fajar Era Jayanti, for their constant support, encouragement, patient, love, and

sacrifices from the beginning. Without them, this thesis would not have happened.