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Digital Logic Design
Introduction
A digital computer stores data in terms of digits (numbers) and proceeds in discrete steps from one state
to the next. The states of a digital computer typically involve binary digits which may take the form of the
presence or absence of magnetic markers in a storage medium , on-off switches or relays. In digital
computers, even letters, words and whole texts Digital binary electronic and robotics Digital Logic

characteristics. Digital hardware or other not. are J code, Logic Logic designers

Logic represented high-tech The and processes circuits other a value is

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digitally. basis user of is characteristics convey is zeroes foundational input, of used complex
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hardware, including fields having such and components into of power, other an as electrical logic
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output. engineering value. computers, Digital and use logical boards Digital

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Data Representation and Number system
Numeric systems
The numeric system we use daily is the decimal system, but this system is not convenient for machines
since the information is handled codified in the shape of on or off bits; this way of codifying takes us to the
necessity of knowing the positional calculation which will allow us to express a number in any base where
we need it.
Radix The information the A In In "0", In "0", In "0", Where Conversion - Let’s to the The see The
Convert base the the the the decimal 1234/10 123/10 positional what given "1", "1", "1", remainder

remainder numeric think binary octal decimal hexadecimal J “A” of number "2", "2",

"2", drops number a = from notation. about system number stands = is 12 system "3", "3", "3", 123

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calculation system handled system of of out. + among Decimal what 3/10 4 "4",
 "4", "4", 3 + by for or system, is system is 4/10 systems
To or its base we 10, the or the "5", "5", "5", codified you base extract base base which last “B” to use

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radices next 8, "6", "6", "6", or do we 2, Any there 10. digit. 10, radix daily for to

there allow last the "7". "7", "7", in will obtain Base there 11 the can last digit. To defines "8", "8", is can

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allow and 16 shape the be digit, extract are each values "9". "9", be so

You eight us ten decimal only the on. of "A", you digit. to repeat the different for on range choices
express two move "B", next or each As system, this values off of an "C", last the for values digit values a

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bits; process example, number each decimal digit, for "D", but of this for

that each a digit this "E", you until number: way in each let's a point digit any digit system of again and

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there of digit start a base codifying left of "F". number: may move is a of with is by

where number, nothing have. a not one number: the a takes decimal convenient we digit, decimal left.
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either need us which Then number to a it. point "0" the

for means you necessity or left machines 1234 a stop. "1". by that and one In of you summary, convert
since digit knowing divide
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Quotient Remainder
----------------------------- 1234/10 = 123 4 --------+ 123/10 = 12 3
------+ | 12/10 = 1 2 ----+ | |
1/10 = 0 1 --+ | | |(Stop when the quotient is 0)
| | | | 1 2 3 4 (Base 10)
Now, 2, Let's Let's In separating using then The so conclusion, conversion the we express express let's a
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----------------------------- 1341/2 ---------------------

-------- 1341/8 ----------------------------- 1341/16 successive new

repeatedly 670/2 335/2 167/2 167/8 83/2 41/2 20/2 10/2 20/8 83/16 try the 5/2

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2/2 1/2 2/8 5/16 number the the a the number nontrivial of same same

easiest the division = = = = = = = = = = = = = = = = = = divide in Quotient

Quotient Quotient fractional decimal decimal into the 670 335 167 167 way example. the
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83 41 20 10 20 83 of its base 5 2 1 0 2 0 5 0 given to the integer

number number part r convert number is Let's decimal obtained can Remainder Remainder

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Remainder and 1341 1341 13 express fixed be 1 0 1 1 1 1 0

0 1 0 1 5 7 4 2 3 5 by fractional obtained ----------------------+ -----------

---------+ ------------------+ ----------------+ --------------+ -----
-------+ ----------+ --------+ ------+ ----+ --+ --------+ ------+ ---
 -+ --+ ------+ ----+ --+ number in in the by point | 1 octal | 2 hexadecimal | 5
reading a base | | 0 | | 4 | | 3 decimal numbers part. notation. by by | | | 1 | | | 7 |
| | D until 2. successively | | | | 0 | | | | 5 the (Stop (HEX; The

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number a | | | | | 0 remainder notation. (Stop (OCT; zero to |

| | | | | 1 integer any | | | | | | | 1 is when Base 1341 base obtained. | | | | |

| | | 1 multiplying when Base part from | | | | | | | | | 1 in is | | | | | | |

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| | | 0 the 16) is binary to the | | | | | | | | | |(Stop | 1
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0) the reminder 0) the base. desired We If method, is we begin kept base iterate and by by is
this process on the remaining fraction, then we will obtain successive significant digit. This methods form
the basis of the multiplication methods of converting fractions between bases
Example. Convert the decimal number 3315 to hexadecimal notation. What about the hexadecimal
equivalent of the decimal number 3315.3? Downloaded From JNTU World (http://www.alljntuworld.in)
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Solution: Quotient Remainder ----------------------------- 3315/16 = 207
3 ------+ 207/16 = 12 15 ----+ |
12/16 = 0 12 --+ | | (Stop when the quotient is 0)
| | | C F 3 (HEX; Base 16)
(HEX; Base 16) Product Integer Part 0.4 C C C ... --------------------
------------ | | | | 0.3*16 = 4.8 4 ----+ | | | | | 0.8*16 = 12.8 12 -
-----+ | | | | 0.8*16 = 12.8 12 --------+ | | | 0.8*16 = 12.8 12 -----
-----+ | |
: ---------------------+ : Thus, 3315.3 (DEC) --> CF3.4CCC... (HEX)
- Convert From Any Base to Decimal
Let's think more carefully what a decimal number means. For example, 1234 means that there are four
boxes (digits); and there are 4 one's in the right-most box (least significant digit), 3 ten's in the next box, 2
hundred's in the next box, and finally 1 thousand's in the left-most box (most significant digit). The total
is 1234:
Original Number: 1 2 3 4 | | | | How Many Tokens: 1 2 3 4 Digit/Token
Value: 1000 100 10 1 Value: 1000 + 200 + 30 + 4 = 1234
or simply, 1*1000 + 2*100 + 3*10 + 4*1 = 1234
Thus, each digit has a value: 10^0=1 for the least significant digit, increasing to 10^1=10, 10^2=100,
10^3=1000, and so forth.
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next, the obtained (most right-most 16^has 3=4096 significant a from value box the for of (least the
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digit,

means in the
b is the base, d
i the digit at position i, m the number of digit after the decimal point, n the number

of the integer part and X10 is the obtained number in decimal. This form the basic of the polynomial

method of
numbers from any base to decimal
Example. Convert 234.14 expressed in an octal notation to decimal.
2*82 + 3*81 + 4*80+1*8-1 + 4*8-2 = 2*64 +3*8 +4*1 +1/8 +4/64 =156.1875
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Example. Convert the hexadecimal number 4B3 to decimal notation. What about the decimal equivalent
of the hexadecimal number 4B3.3?
Solution: Original Number: 4 B 3 . 3 | | | | How Many Tokens: 4 11 3 3
Digit/Token Value: 256 16 1 0.0625 Value: 1024 +176 + 3 + 0.1875 =
1203.1875
Example. Solution:
- As with hexadecimal With starting triple For Relationship demonstrated conversion such three to
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Original How Digit/Token Value: BIN ----------------------

0000 0001 0010 0011 0100 0101 0110 0111 ---------------------- 1000
1001 1010 1011 1100 1101 1110 1111 from the Convert relationship, binary octal digit.

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Many the between from equivalent. by radix OCT 00 01 02 03 04 05 06

07 10 11 12 13 14 15 16 17 234.14 digits Number: Tokens: the base point, In table

Binary Value: 2 corresponding order expressed HEX to 0 1 2 3 4 5 6 7 8 9 A B C D E
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F and bellow, base to - Octal pad convert 16, 128 DEC 10 11 12 13 14 15

in 64 0 1 2 3 4 5 6 7

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8 9 there 2 | 2 the we an and to + octal use outermost a is 24

binary one Binary-hexadecimal 3 | 3 8 a groups notation direct octal + number groups 4 | 4 1

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4 of correspondence digit. four. to . decimal. + to with Likewise, octal,

1 | 1 0.125 0.125 0’s we as between + partition needed four 4 | 4 0.015625 0.0625

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binary the to the form binary base digits triples. = 2 system number
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156.1875 translate Then, and into directly the we groups octal

convert into of system, three each one

Consider converting 101102 to base 8:

101102 = 0102 1102 = 28 68 = 268

Notice that the leftmost two bits are padded with a 0 on the left in order to create a full triplet.
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Now consider converting 101101102 to base 16:

101101102 = 10112 01102 = B16 616 = B616

(Note that ‘B’ is a base 16 digit corresponding to 1110. B is not a variable.)

The conversion methods can be used to convert a number from any base to any other base, but it may not
be very intuitive to convert something like 513.03 to base 7. As an aid in performing an unnatural
conversion, we can convert to the As multiplication Numeric The bsubtracting The Since − each can In
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complement In complement. - To (nines' complement be problem: - The from Next, + + ===== 1

Decimal 1655 − + 218 873 781 the binary, added subtract more a be 873 radix radix nines' ... y
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digit 999. 1 the (bgeneral or done + decimal complement n (b familiar x − sum

complement to with (y) (The (x) (complement (to complement example complement − the
b1) (x) − a complements separately, the nof The it y , 1), decimal is of methods rule, making

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+ respect to radix each number get numbering nines' the x, see bnaming base

produce n. the we digit plus Assuming digit. also complement the 10 the complement. number to nines'
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complements is the n (218) complement 1 converting 1 most is The digit added

repeated y as complement (that y easily equal y) x polynomial from ≤ an − often numbers), complement
is x, is number y is, the intermediate complement 781. the obtained to to + called another subtracting

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 of of other by, the method this the in n a base number complement and by or will (because of radix

decimal diminished two's step, just case, bases adding each with 1 3 10. of always is of is when b x the
digits and x taken: because − complement is, the digit is 6, busing digit y) y, 1

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The first "1" digit is then dropped, giving 655, the correct answer.
If the subtrahend has fewer digits than the minuend, leading zeros must be added which will become
leading nines when the nines' complement is taken. For example: Downloaded From JNTU World
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48032 (x) - 391 (y) becomes the sum: 48032 (x) + 99608 (nines' complement
of y) + 1 (to get the ten's complement) ======= 147641 Dropping the "1" gives
the answer: 47641
Decimal 7 6 5 4 3 2 1 +0 -0 -1 - The by simulating - becomes + + ========== Dropping Signed
Up different are turn, appear. Binary 101001110 01100100 00010110 01100100 11101001

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inverting commonly to method using this the in example fixed the a Unsigned 111

110 101 100 011 010 001 000 – – point representing integers of carry sum: each 1 initial used:
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magnitude, have (changing the equals equals get Sign–Mag. – – – – 011 010 001 000 100 101

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gives our signed numbers least considered complement examples. is the the

significant especially fixed '0' answer: decimal decimal two's to one’s 1’s – – – – 011 010 001
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000 111 110 point only '1' Comp. The 01001110 and useful bit.

complement, numbers. the of complement) Table 100) 22) vice For representation y) in 2’s –
– – – 011 010 001 000 000 111 example: versa). binary (equals below There Comp. two’s

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- Signed Magnitude Representation
The signed magnitude (also referred to as sign and magnitude) representation is most familiar to us as the
base 10 number system. A plus or minus sign to the left of a number indicates whether the number is
positive or negative as in +1210 or -1210. In the binary signed magnitude representation, the leftmost bit

is used for the sign, which takes on a value of 0 or 1 for ‘+’ or ‘-’, respectively. The remaining bits contain
the absolute magnitude.
Consider representing (+12)10 and (-12)10 in an eight-bit format:
(+12)(-12)The both - The See representation representation. Consider representation:
(+12)10 (-12)10 Note result, patterns.
The comparisons - The number, carry-out. Examination again characteristic that Forming 1 complement

since One’s Two’s to this one’s negative two’s one’s the positive it 10 10 again all 0 J there

= = yields for Complement Complement is = = but bit the fourth (10001100)(00001100)complement

(11110011)2 again (00001100)2 true, complement complement positive that patterns then one’s addition
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are when of and number of (00000000)the This consider the signed-magnitude

there column only add representing negative leftmost complement there numbers fifth are 2 2
negation, is 1, (except Representation are 2Representation operation 8 is formed valid, and
representation are forming column in - 2, formed representations representations 1 bit two if thus Table1

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and = when there that is (+12)10 of changing by 255 representations is of is the 0 (-
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above = (00000000)results similar perform: 256 complement zero: 2 both of an to commonly (-12)10

numbers produces numbers for (+0)different shows 0’s overflow numbers. in +0= to +0 0. the We 10, a

and convert forming There 2. and carry-out sign which 00000000 in that that (11111111)The can and

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representations: used. numbers changing condition). -0, an However, bit is
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that additional negative the out 2 0’s represented is and bit positive the this are Since from -0= 1’s can at

of to complement: pattern: complement format, most adding it 00000000 number in least 10000000. the

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two’s bit As bits. 1’s.

and see the the are
bit
is a
Consider representation. again Starting representing with (+12)(+12)10 10 =(00001100)and (-12)10 in an

eight-bit format, this time using the two’s complement

2, complement, or negate the number, producing (11110011)2. Downloaded From JNTU World
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Now add 1, producing (11110100)2, and thus (-12)10 = (11110100)2:

(+12)10 = (00001100)2

(-12)10 = (11110100)2
There is an equal number of positive and negative numbers provided zero is considered to be a positive
number, which is reasonable because its sign bit is 0. The positive numbers start at 0, but the negative
numbers start at -1, and so the magnitude of the most negative number is one greater than the magnitude
of the most positive number. The positive number no complement (-128)(-128)(-128)(-128)(-128)10 The
- In from remaining representation known Consider excess (+12)116)(+12)(-12)Note the There
complement negative viewed Thus, This numerically floating subtraction. Excess the positive two’s two’s

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10 representation it. 10 that 10, 10 excess the is 10 10 10 10 and 128 as = = in The with we

point = = + ——————)2 Representation only number, again (01110100)(10001100)complement =

there the an most complement (10000000)(01111111 (+0000001)2 produce numbers number

(10000000)compute number smaller negative concept representation. unsigned the or “excess,” numbers,
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one is is representing negative biased largest that no which excess the is simplifies

values in that (128 numerical 2 is 2 of a formed 2

numbers. binary representation, bit 2 representation or sequence to number in -128, magnitude has number

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making 10 arrive representation of to produce patterns and 0, to 2 case, = numerical refer that as two the

since for the (00000000)the the in at is excess the corresponds positive the numbers to original between a

an treated negative the increase the sum Table negative excess numbers eight-bit bit bit excess value:
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number value in unsigned, number, commonly to compared two’s the it representation format appear
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choosing a bias:
The bias chosen is most often based on the number of bits (n) available for representing an integer. To get
an approximate equal distribution of true values above and below 0, the bias should be 2(n-1) or 2(n-1) - 1
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Floating point representation
Floating point is a numerical representation system in which a string of digits represent a real number. The
name floating point refers to the fact that the radix point (decimal point or more commonly in computers,
binary point) can be placed anywhere relative to the digits within the string. A fixed point is of the form a
× bn where a is the fixed point part often referred to as the mantissa, or significand of the number b represents
the base and n the exponent. Thus a floating point number can be characterized by a triple of numbers: sign,
exponent, and significand.
- Normalization
A ways, forms 3584.1 In form. point the rule If leading not number to For the Possible In the The The
The The The Because Many - The in precision The the removing potential mini order order left-most
following: number store example, is number representation representation total location IEEE is That

IEEE mantissa shown representation which J that × “1” and into to to to of it. 10number

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bit is cannot of and radix multiple represented normalized represented truncated, computers.(i.e. of of of a
mantissa on mantissa it of bits points comparisons use possible with the the the is Quadruple used and the
× point Electrical for point “chopped be devoted 10the exponent mantissa leftmost left. representing

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floating mantissa. (i.e. 3 above, representations represented = format (exponent in or

is floating mantissa, as .35841 format. as This a the hidden. shifted all and for (128 given a and
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that for bit digit. or bit Exponent format there left mantissa. mantissa to scheme, 754-1985). packing is of
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number, given exponent to to the which This a right number, an difficult.
has floating as represent to normalization, additional number Mantissa the is standard computer, store and
produced a are that floating number hidden floating and the point to that For for the zero be exponent if
specifies bit “1” example, storage, a same bit, the where point the represented, above point standard an of

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General layout
The three fields in an IEEE 754 float Sign Exponent Fraction
Binary floating-point numbers are stored in a sign-magnitude form where the most significant bit is the
sign bit, exponent is the biased exponent, and "fraction" is the significand without the most significant bit.
Exponent The 1 tiny To suitable For exponentfield The numbered final To Convert integer Thus, The
Note the Double The numbered final Single S 0 S 0 = 1 1 EEEEEEEE EEEEEEEEEEE convert solve
zero’s example, 128 exponent and number IEEE IEEE 23 52 that M J Precision Precision

− bits bits for and huge = decimal this, 1 if from from m-1 will double single biasing decimal

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comparison. = are are the fraction is to = is values, 8 127 the be =0001001001

positive, 17 FFFFFFFFFFFFFFFFFFFFFFF 0 the the 0 9 represent biased exponent 11 precision to to 17

precision filled ). + exponent fraction fraction 17.15 12
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63, 31, (2Biasing but to to 8 by at
−
left left binary obtain so 1two's a to ) (2the does floating number − 'F': 'F': S=0. floating to e to IEEE
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Single 1, 0 E which Align point point + use The The because = where 128 10000011 before e+127

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the e the 1 31 values bit is exponents exponent bit being = = field the usual 131 144. is decimal is
representation the representation number the 00010010011001100110011 for stored = allocated
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representation 10000011. sign of sign M, Normalize have 17 0.15 E, bit, of

by bit, in and to bits to adjusting S, to an S, be requires requires it, the S used the exponent the in signed
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Quad Precision
The IEEE Quad precision floating point standard representation requires a 128 bit word, which may be
represented as numbered from 0 to 127, left to right. The first bit is the sign bit, S, the next fifteen bits are
the exponent bits, 'E', and the final 128 bits are the fraction 'F':
S EEEEEEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 0 1 15
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No. No. No. Total Bias Binary Internally, calculators, For represents -Binary In digit printing
implement representation.In 0-9 To Decimal: BCD: Thus, The and 0001 computing BCD-encode

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coded or 0010 2, BCD used code and digital Basic mathematical 1. bit display communication the
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Decimal Digit
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Since they are contiguous, it's usually easy to determine whether a character is lowercase or uppercase (by
checking if the ASCII code lies in the range of lower or uppercase ASCII codes), or to determine if it's a
digit, or to convert a digit in ASCII to an integer value.
ASCII Code (Decimal)
0 nul 16 dle 32 sp 48 0 64 @ 80 P 96 ` 112 p 1 soh 17 dc1 33 ! 49 1 65
A 81 Q 97 a 113 q 2 stx 18 dc2 34 " 50 2 66 B 82 R 98 b 114 r 3 etx 19
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While ASCII is still popularly used, another character representation that was used (especially at IBM) was
EBCDIC, which stands for Extended Binary Coded Decimal Interchange Code (yes, the word "code"
appears twice). This character set has mostly disappeared. EBCDIC does not store characters contiguously,
so this can create problems alphabetizing "words". Downloaded From JNTU World
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One problem with ASCII is that it's biased to the English language. This generally creates some problems.
One common solution is for people in other countries to write programs in ASCII.
Other countries have used different solutions, in particular, using 8 bits to represent their alphabets, giving
up to 256 letters, which is plenty for most alphabet based languages (recall you also need to represent
digits, punctuation, etc).
However, Asian languages, which are word-based, rather than character-based, often have more words than
8 bits can represent. In particular, 8 bits can only represent 256 words, which is far smaller than the number
of words in natural languages.
Thus, 65,000 etc.). byte The endianness even 16-, versus Big-endian significant whereas expressed Table
With quantities.
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4. Design a three bit code to represent each of the six digits of the base 6 number system.
5. Represent the decimal number –234.125 using the IEEE 32- bit (single) format Downloaded From
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Binary Logic
Introduction
Binary logic deals with variables that assume discrete values and with operators that assume logical
meaning.
While each logical element or condition must always have a logic value of either "0" or "1", we also need
to have ways For glance, to light If statement This up/on/true/1 off/false/0. Looking When some
operations, and, AND. AND OR. y=1 NOT. is It addition digits. e.g. Basic what we should it example,
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The basic building blocks of a computer are called logical gates or just gates. Gates are basic circuits that
have at least one (and usually more) input and exactly one output. Input and output values are the logical
values true and false. In computer architecture it is common to use 0 for false and 1 for true. Gates have no
memory. The value of the output depends only on the current value of the inputs. A useful way of describing
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and their output is the truth table. In a truth table, the value of each output is tabulated for every possible
combination of the input values.
We usually consider three basic kinds of gates, and-gates, or-gates, and not-gates (or inverters).
- The AND Gate
The AND gate implements the AND function. With the gate shown to the left, both inputs must have
logic 1 signals applied to them in order for the output to be a logic 1. With either input at logic 0, the
output will be held to logic 0.
The truth table for an and-gate with two inputs looks like this:
x y | z ------- 0 0 | 0 0 1 | 0 1 0 | 0 1 1 | 1 There is no limit to the number of
inputs that may be applied to an AND function, so there is no functional limit to the number of inputs an
AND gate may have. However, for practical reasons, commercial AND gates are most commonly
manufactured with 2, 3, or 4 inputs. A standard Integrated Circuit (IC) package contains 14 or 16 pins, for
practical size and handling. A standard 14-pin package can contain four 2-input gates, three 3-input gates,
or two 4- input gates, and still have room for two pins for power supply connections.
- The OR Gate
The OR gate is sort of the reverse of the AND gate. The OR function, like its verbal counterpart, allows the
output to be true (logic 1) if any one or more of its inputs are true. Verbally, we might say, "If it is raining
OR if I turn on the sprinkler, the lawn will be wet." Note that the lawn will still be wet if the sprinkler is on
and it is also raining. This is correctly reflected by the basic OR function.
In symbols, the OR function is designated with a plus sign (+). In logical diagrams, the symbol below
designates the OR gate.
The truth table for an or-gate with two inputs looks like this:
x y | z ------- 0 0 | 0 0 1 | 1 1 0 | 1 1 1 | 1 As with the AND function, the
OR function can have any number of inputs. However, practical commercial OR gates are mostly limited
to 2, 3, and 4 inputs, as with AND gates.
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- The NOT Gate, or Inverter
The inverter is a little different from AND and OR gates in that it always has exactly one input as well as
one output. Whatever logical state is applied to the input, the opposite state will appear at the output.
The truth table for an inverter looks like this:
x | y ----- 0 | 1 1 | 0
The NOT function, as it is called, is necesasary in many applications and highly useful in others. A
practical verbal application might be:
The door is NOT locked = You may enter
In the inverter symbol, the triangle actually denotes only an amplifier, which in digital terms means that it
"cleans up" the signal but does not change its logical sense. It is the circle at the output which denotes the
logical inversion. The circle could have been placed at the input instead, and the logical meaning would
still be the same
Combined gates
Sometimes, it is practical to combine functions of the basic gates into more complex gates, for instance in
order to save space in circuit diagrams. In this section, we show some such combined gates together with
their truth tables.
- The nand-gate
The nand-gate is an and-gate with an inverter on the output. So instead of drawing several gates like this:
We draw a single and-gate with a little ring on the output like this:
The nand-gate, like the and-gate can take an arbitrary number of inputs.
The truth table for the nand-gate is like the one for the and-gate, except that all output values have been
inverted:
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x y | z ------- 0 0 | 1 0 1 | 1 1 0 | 1 1 1 | 0 The truth table clearly shows that
the NAND operation is the complement of the AND
- The nor-gate
The nor-gate is an or-gate with an inverter on the output. So instead of drawing several gates
like this:
We draw a single or-gate with a little ring on the output like this:
The nor-gate, like the or-gate can take an arbitrary number of inputs.
The truth table for the nor-gate is like the one for the or-gate, except that all output values have been
inverted:
x y | z ------- 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 0
- The exclusive-or-gate
The exclusive-or-gate is similar to an or-gate. It can have an arbitrary number of inputs, and its output
value is 1 if and only if exactly one input is 1 (and thus the others 0). Otherwise, the output is 0.
We draw an exclusive-or-gate like this:
The truth table for an exclusive-or-gate with two inputs looks like this:
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x y | z ------- 0 0 | 0 0 1 | 1 1 0 | 1 1 1 | 0
- The exclusive-Nor-gate
The exclusive-Nor-gate is similar to an N or-gate. It can have an arbitrary number of inputs, and its output
value is 1 if and only if the two input are of the same values (1 and 1 or 0 and 0). Otherwise, the output is
0.
We draw an exclusive-Nor-gate like this:
The truth table for an exclusive-nor-gate with two inputs looks like this:
x y | z ------- 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 1
Let us limit ourselves to gates with n inputs. The truth tables for such gates have 2n lines. Such a gate is
completely defined by the output column in the truth table. The output column can be viewed as a string of
2n binary digits. How many different strings of binary digits of length 2n are there? The answer is 22n, since
there are 2k different strings of k binary digits, and if k=2n, then there are 22n such strings. In particular, if
n=2, we can see that there are 16 different types of gates with 2 inputs.
Families of logic gates
There are several different families of logic gates. Each family has its capabilities and limitations, its
advantages and disadvantages. The following list describes the main logic families and their characteristics.
You can follow the links to see the circuit construction of gates of each family.
- Diode Logic (DL)
Diode logic gates use diodes to perform AND and OR logic functions. Diodes have the property of easily
passing an electrical current in one direction, but not the other. Thus, diodes can act as a logical switch.
Diode logic gates are very simple and inexpensive, and can be used effectively in specific situations.
However, they cannot be used extensively, as they tend to degrade digital signals rapidly. In addition, they
cannot perform a NOT function, so their usefulness is quite limited.
- Resistor-Transistor Logic (RTL)
Resistor-transistor logic gates use Transistors to combine multiple input signals, which also amplify and
invert the resulting combined signal. Often an additional transistor is included to re-invert the output signal.
This combination provides clean output signals and either inversion or non-inversion as needed.
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RTL gates are almost as simple as DL gates, and remain inexpensive. They also are handy because both
normal and inverted signals are often available. However, they do draw a significant amount of current
from the power supply for each gate. Another limitation is that RTL gates cannot switch at the high speeds
used by today's computers, although they are still useful in slower applications.
Although they are not designed for linear operation, RTL integrated circuits are sometimes used as
inexpensive small- signal amplifiers, or as interface devices between linear and digital circuits.
- Diode-Transistor Logic (DTL)
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Fan-in is a term that defines the maximum number of digital inputs that a single logic gate can accept. Most
transistor- transistor logic ( TTL ) gates have one or two inputs, although some have more than two. A
typical logic gate has a fan- in of 1 or 2. Downloaded From JNTU World (http://www.alljntuworld.in)
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In some digital systems, it is necessary for a single TTL logic gate to drive several devices with fan-in
numbers greater than 1. If the total number of inputs a transistor-transistor logic (TTL) device must drive
is greater than 10, a device called a buffer can be used between the TTL gate output and the inputs of the
devices it must drive. A logical inverter (also called a NOT gate) can serve this function in most digital
circuits.
Fan-out
Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate
can feed. Most transistor-transistor logic ( TTL ) gates can feed up to 10 other digital gates or devices.
Thus, a typical TTL gate has a fan-out In this buffer digital Remember, between within Boolean One
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simple x and a or need such function of it smaller, and devices. Boole can must both to that as reduces to
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When
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that the A
The two valued Boolean algebra is defined on a set B={0,1} with two binary operators + and.
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X y x.y
X Y x+y 0 0 0
000010
011100
101111
110
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Closure. from the tables, the result of each operation is either 0 or 1 and 1 ,0 belongs to B
Identity. From the truth table we see that 0 is the identity element Commutative law is obvious from the
symmetry of binary operators Distributive Law. x.(y+z)=x.y+x.z
x y z y+z x.(y+z) x.y x.z x.y+x.z 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0
0101110111101110111111111
Distributive of + over From the complement Principle of duality of The principle of duality algebra
remains valid expression is obtained Laws of Boolean Postulate 2 :
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Postulate Theorem1 Theorem2 (a) (a) (a) (a) 5 0 A : A 1 : Identity + + + +

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A A A′ A = A =1 = A = 1 . can table Boolean if changing Algebra Law
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be shown as in the truth table we can see that x+ x′=1 i.e algebra state the operators

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that every every AND(.) and algebraic the to (b) (b) OR(+), identity

expression 1.A A. (b) A (b) 0. 1+0=1 every above

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elements =A

A′=0
A=A
A=0

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and for x. table. x′=0 + and i.e 1 1.0=0 is the identity element
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for . .
which can be deduced from the postulates of Boolean are interchanged. This mean that the dual of an
OR(+) to AND(.) and all 1's to 0's and vice-versa
Theorem3: involution
A′′=A
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Postulate 3 : Commutative Law
(a) A + B = B + A (b) A B = B A
Theorem4: Associate Law
(a) (A + B) + C = A + (B + C) (b) (A B) C = A (B C)
Postulate4: Distributive Law
(a) A (B + C) = A B + A C (b) A + (B C) = (A + B) (A + C)
Theorem5 : De Morgan's Theorem
(a) (A+B)′= A′B′ (b) (AB)′= A′+ B′
Theorem6 : Absorption
(a) A + A B = A (b) A (A + B) = A
Prove Theorem 1 : (a) X+X=X x+x=(X+X).1 by postulate 2b
=(x+x)(x+x′) 5a =x+xx′ 4b =x+0 5b =x 2a Prove Theorem 1 : (b) X.X=X xx=(X.X)+0 =x.x+x.x′ =x(x+x′)
=x.1 =x Prove Theorem 2 : (a) X+1=X x+1=1.(X+1) (x+x′)=(x+1) =x+x′.1 Prove X.0=0 x.0=0+(X.0)
Prove X+xy=X
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Theorem Theorem =x+ =1 (x.x′)=(x.0) =x.x′+0 =x.x′ =0 x′ 2:

(b) 6 : (a)

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by postulate by postulate 4b 2a
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Prove Theorem 6 : (b) X(x+y)=X

X(x+y)=(x+0).(x+y) by postulate 2a
=x+0.y 4a =x +0 2a =x 2a

Using the laws given above, complicated expressions can be simplified.

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Combinational circuit
Introduction
The combinational circuit consist of logic gates whose outputs at any time is determined directly from the
present combination of input without any regard to the previous input. A combinational circuit performs a
specific information processing operation fully specified logically by a set of Boolean functions.
A combinatorial circuit is a generalized gate. In general such a circuit has m inputs and n outputs. Such a
circuit can always be constructed as n separate combinatorial circuits, each with exactly one output. For
that reason, some texts only discuss combinatorial circuits with exactly one output. In reality, however,
some important sharing of intermediate signals may take place if the entire n-output circuit is constructed
at once. Such sharing can significantly reduce the number of gates required to build the circuit.
When we build a combinatorial circuit from some kind of specification, we always try to make it as good
as possible. The only problem is that the definition of "as good as possible" may vary greatly. In some
applications, we simply want to minimize the number of gates (or the number of transistors, really). In
other, we might be interested in as short a delay (the time it takes a signal to traverse the circuit) as possible,
or in as low power consumption as possible. In general, a mixture of such criteria must be applied.
Describing existing circuits using Truth tables
To specify the exact way in which a combinatorial circuit works, we might use different methods, such as
logical expressions or truth tables.
A truth table is a complete enumeration of all possible combinations of input values, each one with its
associated output value.
When used to describe an existing circuit, output values are (of course) either 0 or 1. Suppose for instance
that we wish to make a truth table for the following circuit:
All we need to do to establish a truth table for this circuit is to compute the output value for the circuit for
each possible combination of input values. We obtain the following truth table:
w x y | a b ----------- 0 0 0 | 0 1 0 0 1 | 0 1 0 1 0 | 1 1 0 1 1 | 1 0 1 0 0 | 1 1 1 0 1 | 1 1 1 1 0 | 1 1 1 1 1 | 1 0
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Specifying circuits to build
When used as a specification for a circuit, a table may have some output values that are not specified,
perhaps because the corresponding combination of input values can never occur in the particular
application. We can indicate such unspecified output values with a dash -.
For binary input this Unspecified is total Circuit circuit are large A Our circuit (where inputs gate
corresponding input The x1 ------------------- 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 simple: separate therefore case.
instance, x0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 simple output number with numbers inverted. numbers.
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1 0 1 0 1 going is there Of when y0 n single-output of the method | | | | | | | | | | | | | | | | output the inputs. of

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only each, - 0 0 0 - 0 0 0 - 1 0 0 - 1 0 0 | let each apply z1 of input. are number - -

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- to Since gates. 0 0 0
100
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division number two-layer of free two entries in to a circuit each each with inputs like difficult the discuss

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heuristics want the built truth a can layer. the problem in fist simple interpreted defined entry truth the the

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table, in to method from (or first when each is improve the decrease output with then rather of as four
value layer table complexity line the four the that a connected circuit). have 0 of one of nonnegative in

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particular zero combinatorial truth the we circuit The a In point for to interpreted 1 this connect
acceptable denominator. an second in all table of binary is will of input course, it, possible situation,
circuits zero, view. with we have an layer of integer circuit.

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as n the a of reason fewest
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many is Our two two
We
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As an example of our general method, consider the following truth table (where a - indicates that we don't
care what value is chosen): Downloaded From JNTU World (http://www.alljntuworld.in)
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x y z | a b ----------- 0 0 0 | - 0 0 0 1 | 1 1 0 1 0 | 1 - 0 1 1 | 0 0 1 0 0 | 0 1 1 0 1 | 0 - 1 1 0 | - - 1 1 1 | 1 0 The
first step is to arbitrarily choose values for the undefined outputs. With out simple method, the best
solution is to choose a 0 for each such undefined output. We get this table:
x y z | a b ----------- 0 0 0 | 0 0 0 0 1 | 1 1 0 1 0 | 1 0 0 1 1 | 0 0 1 0 0 | 0 1 1 0 1 | 0 0 1 1 0 | 0 0 1 1 1 | 1 0
Now, we have to build two separate single-output circuits, one for the a column and one for the b column.
A=x′y′z+x′yz′+xyz
B=x′y′z+xy′z′
For the first column, we get three 3-input AND-gates in the first layer, and a 3-input OR-gate in the second
layer. We get three AND -gates since there are three rows in the a column with a value of 1. Each one has
3-inputs since there are three inputs, x, y, and z of the circuit. We get a 3-input OR-gate in the second layer
since there are three AND -gates in the first layer.
Here is the complete circuit for the first column:
For the second column, we get two 3-input AND -gates in the first layer, and a 2-input OR-gate in the second
layer. We get two AND-gates since there are two rows in the b column with a value of 1. Each one has 3-
inputs since again there are three inputs, x, y, and z of the circuit. We get a 2-input AND-gate in the second
layer since there are two AND-gates in the first layer.
Here is the complete circuit for the second column:
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Now, all we have to do is to combine the two circuits into a single one:
While this circuit works, it is not the one with the fewest number of gates. In fact, since both output
columns have a 1 in the row correspoding to the inputs 0 0 1, it is clear that the gate for that row can be
shared between the two subcircuits:
In some cases, even smaller circuits can be obtained, if one is willing to accept more layers (and thus a
higher circuit delay).
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Boolean functions
Operations of binary variables can be described by mean of appropriate mathematical function called
Boolean function. A Boolean function define a mapping from a set of binary input values into a set of output
values. A Boolean function is formed with binary variables, the binary operators AND and OR and the
unary operator NOT.
For example , a Boolean function f(x1,x2,x3,......,xn) =y defines a mapping from an arbitrary combination

of binary input values (x1,x2,x3,......,xn) into a binary value y. a binary function with n input variable can
n
operate on 2n distincts values. Any such function can be described by using a truth table consisting of 2
rows and n columns. The content of this table are the values produced by that function when applied to all
the possible combination of the n input variable.
Example
x y x.y 0 0 0 0 1 0 1 0 0 1 1 1
The function f, representing x.y, that is f(x,y)=xy. Which mean that f=1 if x=1 and y=1 and f=0 otherwise.
For each rows of the table, there is a value of the function equal to 1 or 0. The function f is equal to the
sum of all rows that gives a value of 1.
A Boolean function may be transformed from an algebraic expression into a logic diagram composed of
AND, OR and NOT gate. When a Boolean function is implemented with logic gates, each literal in the
function designates an input to a gate and each term is implemented with a logic gate . e.g.
F=xyz
F=x+y′z
Complement of a function
The complement of a function F is F′ and is obtained from an interchange of 0’s to 1’s and 1’s to 0’s in
the value of F. the complement of a function may be derived algebraically trough De Morgan’s theorem
(A+B+C+....)′= A′B′C′....
(ABC....)′= A′+ B′+C′......
The generalized form of de Morgan’s theorem state that the complement of function is obtained by
interchanging AND and OR and complementing each literal.
F=X′YZ′+X′Y′Z′ F′=( X′YZ′+X′Y′Z′)′
=( X′YZ′)′.( X′Y′Z′)′ =( X′′+Y′+Z′′)( X′′+Y′′+Z′′) =( X+Y′+Z)( X+Y+Z)
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Canonical form(Minterns and Maxterms )
A binary variable may appear either in it normal form or in it complement form . consider two binary
variables x and y combined with AND operation. Since each variable may appears in either form there are
four possible combinations: x′y′, x′y, xy′,xy. Each of the term represent one distinct area in the Venn
diagram and is called minterm or a standard product. With n variable, 2n minterms can be formed.
In a similar fashion, n variables forming an OR term provide 2n possible combinations called maxterms or
standard sum. Each maxterm is obtained from an corresponding bit is 1 and un-primed if the
corresponding minterm and vice versa.
X Y Z Minterm maxterm 0 0 0 x′y′z′ X+y+z 0 0 1 X′y′z X+y+z′ 0 1 0 X′yz′ X+y′+z 0 1 1 X′yz X+y′+z′ 1
0 0 Xy′z′ X′+y+z 1 0 1 Xy′z X′+y+z′ 1 1 0 Xyz′ X′+y′+z 1 1 1 Xyz X′+y′+z′
A Boolean function may be expressed algebraically of variable that produce a 1 and taken the OR
Similarly, the same function can be obtained and then taken the AND of those term.
It is sometime convenient to express F(X,Y,Z)=∑(1,4,5,6,7) . the summation minterms the So, Sometime
expanded where To done with e.g. =(xy (x+x′)(y+x′)(x+z)(y+z) express minterm F(X,Y,Z)=∑(1,4,5,6,7)
represent xx′.

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+x′)(xy+z) by x is using of into it one a is is the Boolean F=xy+x′z distributive the
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converted of convenient function. the sum missing function of as to AND The to

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law = a an product express X’Y’Z+XY’Z’+XY’Z+XYZ’+XYZ variable. AND letters
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x+xz=(x+y)(x+z). as term a the term. a and in Boolean bolean the symbol

if product of maxterm parenthesis corresponding OR by of function ∑ those forming term stands from

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terms. of following when a the for given the bit maxterm the it n is is truth
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ORing 0. variables, in F form Note sum table for of of each that list the by minterms,

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with forming of each combination terms; the each maxterm variables the in a variable
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minterm the number of following is variable in the the being for

follow complement each order notation: that primed ing combination taken produces it are if when of the
the its
0
function in its sum of minterm. If it is not in that case, the expression is there is any missing variable, it is
ANDed with an expression such as x+x′
of maxterms, it must first be brought into a form of OR terms. This can be then if there is any missing
variable, say x in each OR term is ORded
(y+x′)(x+z)(y+z) Adding missing variable in each term (y+x′)= x′+y+zz′ =(x′+y+z)( x′+y+z′) (x+z)=
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(y+z)= y+z+xx′ =( x+y+z)( x′+y+z) F= ( x+y+z)( x+y′+z) ( x′+y+z)( x′+y+z′)
A convenient way to express this function is as follow :
F(x,y,z)= ∏ (0,2,4,5)
Standard form
A no Boolean Another two The each. e.g. the number e.g. a the F=(xy+zw)(x′y′+z′w′) = =Xyx′y
=xyz′w′+zwx′y′
Describing To expression outputs, considered If implementations. boolean
xy(x′y′+z′w′)+zw(x′y′+z′w′) Boolean Boolean specific parenthesis product define F=x+xy′+x′yz F= or
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sum The nay x(x+y′)(x′+y+z) +xyz′w′ of algebra and way of sum function literals.

number uses what to equation rules of product(SOP) functions the have to denotes

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combinatorial follow two (POS)is can any literals. the in product constants also +zwz′w′ be other a
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minimal does, terms variables Product in ANDing types that is a the in non we Parentheses Logic
becomes satndard final of number bar containing standard such containing of can standard or answer. or
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these Product expressions use as familiar a form. of x, prime are terms

form. literal a form. y, OR The AND logic used Here and of (which In terms The only by z Sum to terms
expression the that (sometimes algebraic modify sum methods called term case, forms stands called

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any
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is
For SOP forms AND gates will be in the first level and a single OR gate will be in the second level.
For POS forms OR gates will be in the first level and a single AND gate will be in the second level.
Note that using inverters to complement input variables is not counted as a level. Downloaded From
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Examples:
(X′+Y)(Y+XZ′)′+X(YZ)′
The equation is neither in sum of product nor in product of sum. The implementation is as follow
X1X2′X3+X1′X2′X2+X1′X2X′3
The equation is in sum of product. The implementation is in 2-Levels. AND gates form the first level and
a single OR gate the second level.
(X+1)(Y+0Z)
The equation is neither in sum of product nor in product of sum. The implementation is as follow
Power of logic expressions
A valid question is: can logic expressions describe all possible combinatorial circuits?. The answer is yes
and here is why:
You can trivially convert the truth table for an arbitrary circuit into an expression. The expression will be
in the form of a sum of products of variables and there inverses. Each row with output value of 1 of the
truth table corresponds to one term in the sum. In such a term, a variable having a 1 in the truth table will
be uninverted, and a variable having a 0 in the truth table will be inverted.
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Take the following truth table for example:
x y z | f --------- 0 0 0 | 0 0 0 1 | 0 0 1 0 | 1 0 1 1 | 0 1 0 0 | 1 1 1 1 The X′Y′Z+XY′Z′+XYZ Since
expression, Simplicity There certain X(Y+Z) The or-gate. always We We circuits same Circuit The
algebraic unique, Simplification A Unfortunately, theorem e.g. Boolean 0 1 1 have, call

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corresponding complexity left simplify 1 0 1 ones are you | | | function true 0 0 1 that it
 It this and one expression can many for minimization seems that can you that make equation

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computed. the of obvious the the logic through expression the number describe are in from
expressions two gate signal can of the digital assumed many no Boolean any that expressions gates,

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algebraic the is: reduced gates instance, that one combinatorial We (and first the algebra number gates

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fewest that to and only is manipulation a are of following be follow circuit preferable when minimal
gates. implement any and is ideal. way, circuit interested possible many XY+XZ implemented. other one
expressed that with nor In two with circuits) number or-gate. to reality, manipulation will gates even a a

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 second from expression. that the Although of The table, best literal signal correspond input function
second that one. that way, compute the and minimize to the becomes takes by However, final to output.

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simplicity. is representation circuits function: truth to not gate only propagate always any to
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Simplify xy +x′z+yz xy +x′z+yz= xy +x′z+yz(x+x′) xy +x′z+yzx+yzx′ xy(1+z) +x′z(1+y) =xy+x′z
Karnaugh map
The Karnaugh map also known as Veitch diagram drawn in such a way that the simplification of in the
map. The map is a diagram made up of can be expressed as a sum of minterms, it follows area enclosed
by those squares whose minterms A two variable Boolean function can be represented A
0AB

1 A’B’
AB’
0B1
 A’B AB A three AB
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can be represented as A Boolean squares follow are
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minterm. dimensional be graphically seen Since from

form any in the of Boolean the the location map truth from function of table,
the 1’s
01
00
10
11 C
A’BC’

ABC’ AB’C’ 0 C

1 A’B’C
ABC AB’C
B
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A four variable Boolean function can be represented in the map bellow
A
CD AB
00 01

10
11
A’B’C’D’
A’BC’D’
00
ABC’D’ AB’C’D’ A’B’C’D

A’BC’D ABC’D 01
A’B’CD A’BCD 01 C A’B’CD’
A’BCD’ B
To simplify a Boolean function using map. The next step is to combine adjacent should be as large as
possible. A single minterms.
In a four variable karnaugh map,
1 variable product term is obtained if 2 variable product term is obtained if 3 variable product term is
obtained if 1 variable product term is obtained if A square having a 1 may belong to more The product
The edge adjacent Implicant In (or implicant where Boolean maxterms • karnaugh final and

J P F expression if the of implies is stage they logic, a the left Boolean map in

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only function thus n a variables. square when of adjacent is one is sums) an a F each

variable "covering" or implicant if ABCD ABCD’ rectangle to 8 4 2 1 karnaugh AB’C’D AB’CD

AB’CD’

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of square the adjacent adjacent adjacent than group the right 1’s one

group is as map, into of covered squares squares squares hand it term D four may a of the group in edge.
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minterms minterm appear are are are the first covered covered covered sum

Consequent, of step in one, yields of are the is product to two, ORded diagram. plot a two simpler four,

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function is than The adjacent the 01

truth table on the group of minterm two groups of two

simplified sum of
to the bottom map are said to be
(sum term or product term) of one or more minterms in a sum of products of a boolean function. Formally,
a product term P in a sum of products is an P implies F. More precisely:
of F) if F also takes the value 1 whenever P equals 1.
• P is a product term
This means that P < = F with respect to the natural ordering of the Boolean space. For instance, the
function
f(x,y,z,w) = xy + yz + w
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is implied by xy, by xyz, by xyzw, by w and many others; these are the implicants of f.
Prime implicant
A prime implicant of a function is an implicant that cannot be covered by a more general (more reduced -
meaning with fewer literals) implicant. W.V. Quine defined a prime implicant of F to be an implicant that
is minimal - that is, if the removal of any literal from P results in a non-implicant for F. Essential prime
implicants are prime implicants that cover an output of the function that no combination of other prime
implicants is able to cover.
A
CD AB
00 01

10
11
00
01
11
11 1 1 C
1 10
B

N
CD AB
00
In simplifying J a Boolean
01
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11 A

10
function using karnaugh D

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prime prime Non implicant prime implicant
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implicant

00
Essential prime implicant 1 01 11 1 1 1 1
D
Non Essential prime implicant
C
Essential prime implicant 1 1 1 10
B
map, non essential prime implicant are not needed
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Minimization of Boolean expressions using Karnaugh maps.
Given the following truth table for the majority function.
a b C M(output) 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1
The Boolean algebraic expression is
m = a′bc + ab′c + abc′ + abc.
the minimization using algebraic manipulation can be done as follows.
m = a′bc + abc + ab′c + abc + abc′ + abc
= (a′ + a)bc + a(b′ + b)c + ab(c′ + c)
= bc + ac + ab
The abc term was replicated and combined with the other terms.
To use a Karnaugh map we draw the following map which has a position (square) corresponding to each
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The following corresponds to the Boolean expression
Q = A′BC′D + A′BCD + ABC′D′ + ABC′D + ABCD + ABCD′ + AB′CD + AB′CD′
RULE: Minimization is achieved by drawing the smallest possible number of circles, each containing the
largest possible number of 1s.
Grouping the 1s together results in the following.
A
CD AB
00 01

10
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00
1 01
1

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01 C
01
B
The expression for the groupings above is
Q = BD + AC + AB
This expression requires Other examples
1. F=A′B+AB

2.
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A AB
01
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1 1 1 0 =A’B’+BC’+AB

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1B
3. F=AB+A′BC′D+A′BCD+AB′C′D′
A
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00
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5. F=A′B′C′D′+AB′C′D′+A′BC′D+ABC′D+A′BCD+ABCD
A
CD AB
00 01

11 10

1
00
1 Obtaining The combined square
F=A′B′C′D′+A′BC′D′+AB′C′D′+A′BC′D+A′B′CD′+A′BCD′+AB′CD′ The 01
1 1 11 1 1 C
10
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B a Simplified product of sum simplification of the product of sum follows are the cells
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00 01

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F′′=(AB+CD+BD′)′
=(A′+B′)(C′+D′)(B′+D) which is he simplified F in product of sum.
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00
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Don't Care condition
Sometimes we do not care whether a 1 or 0 occurs for a certain set of inputs. It may be that those inputs
will never occur so it makes no difference what the output is. For example, we might have a BCD (binary
coded decimal) code which consists of 4 bits to encode the digits 0 (0000) through 9 (1001). The remaining
codes (1010 through 1111) are not used. If we had a truth table for the prime numbers 0 through 9, it would
be
ABCDF000000001000101001110100001011011000111110000100101
010X1011X1100X1101X1110X1111X
F=A′B′CD′+A′B′CD+A′BC′D+A′BCD
The X in the above stand for "don’t care", we don't care whether a 1 or 0 is the value for that combination
of inputs because (in this case) the inputs will never occur.
CD AB
00
0

01
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01

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The tabulation method(Quine-McCluskey)
For function of five or more variables, it is difficult to be sure that the best selection is made. In such case,
the tabulation method can be used to overcome such difficulty. The tabulation method was first formulated
by Quine and later improved by McCluskey. It is also known as Quine-McCluskey method.
The Quine–McCluskey algorithm (or the method of prime implicants) is a method used for minimization
of boolean functions. It is functionally identical to Karnaugh mapping, but the tabular form makes it more
efficient for use in computer been The Finding Use other Step Minimizing m3 m10 m11 m12 m13 m14
m15 One (leaving F(A,B,C,D) Of table. m0 m1 m2 m4 m5 m6 m7 m8 m9 course, 0 method those 0 0 0 0
0 0 0 1 1 1: can reached. A 1 1 1 1 1 1 prime Don't-care 0 J 000111100001111

finding B 1 all 0 0 1 0 0 1 1 0 0 out 1 1 0 0 1 1 easily 1 algorithms, C 0 1 0 0 1 0 1 0 1 prime 0 1 0 1 0 1

that's prime implicants an = involves D don't-care 0 0 0 0
10001x

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Number of 1s Minterm Binary Representation -------------------------------------------- 1 m4 0100
m8 1000 -------------------------------------------- 2 m9 1001 m10 1010 m12 1100 --------------------------------
------------ 3 -------------------------------------------- 4 At that marked combined, Number --------------------
---------- 1 ------------------------------ 2 ------------------------------ 3 ------------------------------ 4 At

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m(12,14) m(11,15) m(14,15) be have 2 seen to 2 up that with obtain Implicants Size as 100- the -
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earlier. The don't care terms are not placed on top - they are omitted from this section because they are not
necessary inputs.
4 8 10 11 12 15
m(4,12) X X -100 (BC′D′)
m(8,9,10,11) X X X 10--(AB′)
m(8,10,12,14) m(10,11,14,15) In each implicant implicant The minterms of prime implicants.
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The NAND gate represents the complement of the AND operation. Its name is an
abbreviation of NOT AND. The graphic symbol for the NAND gate consists of an AND symbol with a
bubble on the output, denoting that a complement operation is performed on the output of the AND gate
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The NOR gate represents the complement of the OR operation. Its name is an abbreviation of NOT OR.
The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output, denoting that
a complement operation is performed on the output of the OR gate as shown earlier.
A universal gate is a gate which can implement any Boolean function without need to use any other gate
type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and
NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families.
In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the other way
around.
Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the other way
around.
NAND Gate is a Universal Gate
To prove that any Boolean function can be implemented using only NAND gates, we will show that the
AND, OR, and NOT operations can be performed using only these gates. A universal gate is a gate which
can implement any Boolean function without need to use any other gate type.
Implementing an Inverter Using only NAND Gate
The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).
1. All NAND input pins connect to the input signal A gives an output A′.
2. One NAND input pin is connected to the input signal A while all other input pins are connected to
logic 1. The output will be A′.
Implementing AND Using only NAND Gates
An AND gate can be replaced by NAND gates as shown in the figure (The AND is
replaced by a NAND gate with its output complemented by a NAND gate inverter).
Implementing OR Using only NAND Gates
An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND
gate with all its inputs complemented by NAND gate inverters).
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Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.
NOR Gate is a Universal Gate:
To prove that any Boolean function can be implemented using only NOR gates, we will show that the
AND, OR, and NOT operations can be performed using only these gates.
Implementing an Inverter Using only NOR Gate
The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).
1.All NOR input pins connect to the input signal A gives an output A′.
2. One NOR input pin is connected to the input signal A while all other input pins are connected to logic
0. The output will be A′.
Implementing OR Using only NOR Gates
An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate
with its output complemented by a NOR gate inverter)
Implementing AND Using only NOR Gates
An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR
gate with all its inputs complemented by NOR gate inverters)
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Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.
Equivalent Gates:
The shown figure summarizes important cases of gate equivalence. Note that bubbles indicate a
complement operation (inverter).
A NAND gate is equivalent to an inverted-input OR gate.
An AND gate is equivalent to an inverted-input NOR gate.
A NOR gate is equivalent to an inverted-input AND gate.
An OR gate is equivalent to an inverted-input NAND gate.
Two NOT gates in series are same as a buffer because they cancel each other as A′′=A.
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Two-Level Implementations:
We have seen before that Boolean functions in either SOP or POS forms can be implemented using 2-
Level implementations.
For SOP forms AND gates will be in the first level and a single OR gate will be in the second level.
For POS forms OR gates will be in the first level and a single AND gate will be in the second level.
Note that using inverters to complement input variables is not counted as a level.
To implement a function using NAND gates only, it must first be simplified to a sum of product and to
implement a function using NOR gates only, it must first be simplified to a product of sum
We will show that SOP forms can be implemented using only NAND gates, while POS forms can be
implemented using only NOR gates through examples.
Example 1: Implement the following SOP function using NAND gate only
F = XZ + Y′Z + X′YZ
Being an SOP expression, it is implemented in 2-levels as shown in the figure.
Introducing two successive inverters at the inputs of the OR gate results in the shown equivalent
implementation. Since two successive inverters on the same line will not have an overall effect on the
logic as it is shown before.
By associating one of the inverters with the output of the first level AND gate and the other with the input
of the OR gate, it is clear that this implementation is reducible to 2-level implementation where both levels
are NAND gates as shown in Figure.
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Example 2: Implement the following POS function using NOR gates only
F = (X+Z) (Y′+Z) (X′+Y+Z)
Being a POS expression, it is implemented in 2-levels as shown in the figure.
Introducing two successive inverters at the inputs of the AND gate results in the shown equivalent
implementation. Since two successive inverters on the same line will not have an overall effect on the
logic as it is shown before.
By associating one of the inverters with the output of the first level OR gates and the other with the input
of the AND gate, it is clear that this implementation is reducible to 2-level implementation where both
levels are NOR gates as shown in Figure.
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There are some other types of 2-level combinational circuits which are
• NAND-AND
• AND-NOR,
• NOR-OR,
• OR-NAND
These are explained by examples.
AND-NOR functions:
Example 3: Implement the following function F=(XZ+Y′Z+X′YZ) ′ OR F′=XZ+Y′Z+X′YZ
Since F′ is in SOP form, it can be implemented by using NAND-NAND circuit.
By complementing the output we can get F, or by using NAND-AND circuit as shown in the figure.
It can also be implemented using AND-NOR circuit as it is equivalent to NAND- AND circuit as shown in
the figure.
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OR-NAND functions:
Example 4: Implement the following function
F=((X+Z)(Y′+Z)(X′+Y+Z)) ′ or F′ (X+Z)(Y′+Z)(X′+Y+Z)
Since F′ is in POS form, it can be implemented by using NOR-NOR circuit.
By complementing the output we can get F, or by using NOR-OR circuit as shown in the figure.
It can also be implemented using OR-NAND circuit as it is equivalent to NOR-OR circuit as shown in the
figure
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Designing Combinatorial Circuits
The design of a combinational circuit starts from the verbal outline of the problem and ends with a logic
circuit diagram or a set of Boolean functions from which the Boolean function can be easily obtained. The
procedure involves the following steps:
- The problem is stated - The number of available input variables and required output variables is
determined.
Example Adders In reside many numbers. to -Half A and A of C The Following A 0 0 1 1 Equation
being half half modify A electronics, - - - - a drawback and carry Adder numerical in

J adder adder B 0 1 0 1 The The The The the the B, of In an is value most and the truth

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cases input simplified logic arithmetic the of is adder has Carry 0 0 0 1 of an aC

Sum combinational truth representations, logical two this significant which table diagram adder and
where is into the circuit inputs, Sum 0
1
1
0 table and output Boolean that logic an are or AND circuit twos Carry. is adder-subtracter. summer for
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defines both is of generally drawn. unit variable complement of that a these that

function half binary such A (ALU) in the and is performs two adder: case are as circuit a labelled

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required digits. B. digital for Binary-coded outputs. where assigned of

Essentially or Other each a an ones multibit A circuit relationship other addition output and signed their
complement operations B, the that decimal addition, letter is and number operation output
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obtained performs between two symbol or is it are of representations

outputs, excess-3, being cannot on a performed. addition the half two inputs used adder include the binary

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the of to sum and is most Although represent numbers. require a digits. the S carry.
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XOR with
Sum=A′B+AB′ Carry=AB
One can see that Sum can also be implemented using XOR gate as A B
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-Full Adder.
A full adder has three inputs A, B, and a carry in C, such that multiple adders can be used to add larger
numbers. To remove ambiguity between the input and output carry lines, the carry in is labelled Ci or Cin

while the carry out is labelled Co or Cout.

A full adder is a logical circuit that performs an addition operation on three binary digits. The full adder
produces a sum and carry value, which are both binary digits. It can be combined with other full adders or
work on its own.
Input Output A B Ci Co S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Co=A′BCi+AB′Ci+ABCi′+ABCi

S=A′B′Ci +A′BCi′+ABCi′+ABCi
A full adder can be trivially built using our ordinary design methods for combinatorial circuits. Here is the
resulting
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circuit diagram using NAND gates only:
Co=A′BCi+AB′Ci+ABCi′+ABCi by manipulating Co, we can see thatCo= Ci(A B)+AB

S=A′B′Ci +A′BCi′+ABCi′+ABCi By manipulating S, we can see that S=Ci (A B)

Note that the final OR gate before the carry-out output may be replaced by an XOR gate without altering
the resulting logic. This is because the only discrepancy between OR and XOR gates occurs when both
inputs are 1; for the adder shown here, this is never possible. Using only two types of gates is convenient if
one desires to implement the adder directly using common IC chips.
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder,
connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the
two carry outputs. Equivalently, S could be made the three-bit xor of A, B, and Ci and Co could be made
the three-bit majority function of A, B, and Ci. The output of the full adder is the two-bit arithmetic sum of
three one-bit numbers.
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Ripple carry adder
It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder
inputs a Cin, which next full is adder. the Cout Note of the that previous the first adder. (and only This the
kind first) of full adder adder is a may ripple be carry replaced adder, by a since half adder.

each carry bit "ripples" to the

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry
adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous
full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Following the path
from Cin to Cout shows 2 gates that must be passed through. Therefore, a 32-bit adder requires 31 carry
computations and the final sum calculation for a total of 31 * 2 + 1 = 63 gate delays.
Subtractor
In electronics, a subtractor can be designed using the same approach as that of an adder. The binary
subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit
numbers, three bits are involved in performing the subtraction for each bit: the minuend (Xi), subtrahend
(Yi), and a borrow in from the previous (less significant) bit order position (Bi). The outputs are the
difference bit (Di) and borrow bit Bi + 1.
Half subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). Such a circuit is
called a half-subtractor because it enables a borrow out of the current arithmetic operation but no borrow
in from a previous arithmetic operation.
The truth table for the half subtractor is given below.
XYDB
0000
0111
1010
1100
D=X′Y+XY′ or D= X Y
B=X′Y
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Full Subtractor
As in the case of the addition using logic gates , a full subtractor is made by combining two half-
subtractors and an additional allows cascading OR-gate. which A full results subtractor in the possibility
has the borrow of multi-bit in capability subtraction.
(denoted as BORIN in the diagram below) and so
The final truth table for a full subtractor looks like:
A B BORIN D BOROUT 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1
Find out the equations of the borrow and the difference
The circuit diagram for a full subtractor is given below.
For a wide range of operations many circuit elements will be required. A neater solution will be to use
subtraction via addition using complementing as was discussed in the binary arithmetic topic. In this case
only adders are needed as shown bellow.
Binary subtraction using adders
Our binary adder can already handle negative numbers as indicated in the section on binary arithmetic But
we have not discussed how we can get it to handle subtraction. To see how this can be done, notice that in
order to compute the expression x - y, we can compute the expression x + -y instead. We know from the
section on binary arithmetic how to negate a number by inverting all the bits and adding 1. Thus, we can
compute the expression as x + inv(y) + 1. It suffices to invert all the inputs of the second operand before
they reach the adder, but how do we add the 1. That seems to require another adder just for that. Luckily,
we have an unused carry-in signal to position 0 that we can use. Giving a 1 on this input in effect adds one
to the result. The complete circuit with addition and subtraction looks like this:
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Exercise. Generate the truth table and Draw a logic circuit for a 3 bit message Parity Checker and
generator seen in data representation section
Medium Scale integration component
The purpose of circuit minimization is to obtain an algebraic expression that, when implemented results in
a low cost circuit. Digital circuit are constructed with integrated circuit(IC). An IC is a small silicon
semiconductor crystal called chip containing the electronic component for digital gates. The various gates
are interconnected inside the chip to form the required circuit. Digital IC are categorized according to their
circuit complexity as measured by the number of logic gates in a single packages.
- Small scale integration (SSI). SSi devices contain fewer than 10 gates. The input and output of the gates
are
connected directly to the pins in the package. - Medium Scale Integration. MSI devices have the
complexity of approximately 10 to 100 gates in a single
package - Large Scale Integration (LSI). LSI devices contain between 100 and a few thousand gates in a
single package - Very Large Scale Integration(VLSI). VLSI devices contain thousand of gates within a
single package. VLSI devices have revolutionized the computer system design technology giving the
designer the capabilities to create structures that previously were uneconomical.
Multiplexer
A multiplexer is a combinatorial circuit that is given a certain number (usually a power of two) data inputs,
let us say 2n, and n address inputs used as a binary number to select one of the data inputs. The multiplexer
has a single output, which has the same value as the selected data input.
In other words, the multiplexer works like the input selector of a home music system. Only one input is
selected at a time, and the selected input is transmitted to the single output. While on the music system, the
selection of the input is made manually, the multiplexer chooses its input based on a binary number, the
address input.
The truth table for a multiplexer is huge for all but the smallest values of n. We therefore use an
abbreviated version of the truth table in which some inputs are replaced by `-' to indicate that the input
value does not matter.
Here is such an abbreviated truth table for n = 3. The full truth table would have 2(3 + 23) = 2048 rows.
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SELECT INPUT
a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 | x - - - - - - - - - - - --- - 0 0 0 - - - - - - - 0 | 0 0 0 0 - - - - - - - 1 | 1 0 0 1 - - - - -
-0-|0001------1-|1010-----0--|010-----1--|011----0---|011----1---|1
00---0----|100---1----|101--0-----|101--1-----|110-0------|110-1---
- - - | 1 1 1 0 - - - - - - - | 1 1 We can abbreviate this table even more by using a2 The Indeed, same

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J N our way simple we design can simplify the

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- 0 0 0 0 1 1 1 1 truth table method would yield 1 a1 - 0 0 a- 0 1 a 0 1 letter
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d- - - 7 - d- - - 6 - d- - - to 5 - indicate d- - - 4 - d- - - 3 - d- - - 2 - d- - c the 1 -

d- c - 0 value | | --- | | 1 0 - - - - - c - - | 1 1 - - - - c - - - | 0 0 - - - c - - - - | 0 1 - - c - - - - - | 1 0 - c - - - - - - | 1
1 c - - - - - - - | for the multiplexer, we a very large circuit. The simplified 0 1 0 1 0 1 0 1 0 1 0 1

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of the selected input,

like this:
x-cccccccc
can also simplify the corresponding circuit looks like this: circuit.
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Demultiplexer
The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs.
It has 2n outputs. The address input determine which data output is going to have the same value as the data
input. The other data outputs will have the value 0.
Here is an abbreviated truth table for the demultiplexer. We could have given the full table since it has
only 16 rows, but we will use the same convention as for the multiplexer where we abbreviated the values
of the data inputs.
a2 a1 a0 d | x7 x6 x5 x4 x3 x2 x1 x0 ------------------------------------- 0 0 0 c | 0 0 0 0 0 0 0 c 0 0 1 c | 0 0 0
000c0010c|00000c00011c|0000c000100c|000c0000101c|00c0000011
0 c | 0 c 0 0 0 0 0 0 1 1 1 c | c 0 0 0 0 0 0 0 Here is one possible circuit diagram for the demultiplexer:
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Decoder
In both the multiplexer and the demultiplexer, part of the circuits decode the address inputs, i.e. it translates
a binary number of n digits to 2n outputs, one of which (the one that corresponds to the value of the binary
number) is 1 and the others of which are 0.
It is sometimes advantageous to separate this function from the rest of the circuit, since it is useful in many
other applications. Thus, we obtain a new combinatorial circuit that we call the decoder. It has the following
truth table (for n = 3):
a2 a1 a0 | x7 x6 x5 x4 x3 x2 x1 x0 ----------------------------------
000|00000001001|00000010010|00000100011|00001000100|0001000
0 1 0 1 | 0 0 1 0 0 0 0 0 1 1 0 | 0 1 0 0 0 0 0 0 1 1 1 | 1 0 0 0 0 0 0 0 Here is the circuit diagram for the
decoder:
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Encoder
An encoder has 2n input lines and n output lines. The output lines generate a binary code corresponding to
the input value. For example a single bit 4 to 2 encoder takes in 4 bits and outputs 2 bits. It is assumed that
there are only 4 types of input signals these are : 0001, 0010, 0100, 1000.
I3 I2 I1 I0 F1 F0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1
4 to 2 encoder
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The encoder has the limitation that only one input can be active at any given time. If two inputs are
simultaneously active, the output produces an undefined combination. To prevent this we make use of the
priority encoder.
A priority encoder is such that if two or more inputs are given at the same time, the input having the
highest priority will take precedence. An example of a single bit 4 to 2 encoder is shown.
I3 I2 I1 I0 F1 F0 0 0 0 1 0 0 0 0 1 X 0 1 0 1 4 The example, F1F0=11(binary Exercise 1 2. range 1100-
1111(i.e.12 Otherwise 3. significant false one(0001) 4. F3=x’y’z+xy 5. combinations 6. F3=x’y’z+xy 7.
significant as Design and By to - A A being A A A A A’B’C+A’BC’+AB’C’+ABC= - - - also 1 X 2 X’s
circuit circuit using otherwise circuit circuit ii. ii. priority combinational combinational 0000=0

J i. i. a Draw Use Construct X X indivisible as designate true the Design Design Find

Design the are bit. bit. algebraic a has implements the X X sum has has input Design Design A’B’CD’,

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table the encoder output not to The The a four Karnaugh (A 3) simpler 1 1 to
 1011=11 a a the truth four four of considered the the Itrue circuit circuit for circuit by prime 3has 15)
inputs minterms manipulation, the the is circuit 0 1
circuit circuit circuit don’t three.) table inputs inputs this false. table the cannot A’BC’D’, the circuit
circuit expression diagram map number has has D,C,B,A represents circuit, Boolean implementing care to

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highest to for as The is is P,Q,R,S, P,Q,R,S, one represent one to implements occur.

that with prime defined defined this condition obtain output to AB’CD’ output, is Show and A output,
implements for encoded function priority a circuit, implement a The the numbers) decoder hence F
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number representing representing (B the a for by by that: using months

simplified the output X, X, designating the can inputs problem and so the the in

F=A’B’C’D’+A’BCD’+AB’C’D’+ABC’D which obtain simplified C) which and function the regarded

natural never the which hence this following following of of in external proper functions the is function
an expression and is the the the the occur. true obtain binary that is true circuit using expression the range

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year obtain expression natural natural only don’t - if gates. fact if three
three value AB+C’D the using an NOR form from the is 1100 divisible the care for that expression true

number binary binary input Boolean Boolean of for where the NOR function gates January of the to

condition. other if X = F 1111 function the to binary (A+B+C)(A+B’+C)(A’+B+C)(A’+B+C’) by

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number number in only. gate represented A the inputs, month for terms functions:

functions: 1 F is (0) is only as circuit and the undefined. value X F. to a in 0000=0, 0000=0, of
represented least if Sum by December terms the P,Q,R,S may represents is itself. F1=x’y’z’+xz
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F1=x’y’z’+xz significant of divisible It value be of is minterm. to to found P,Q,R,S. Note

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that that either is three prime Input input The 1, the zero(0000) P P F2=xy’z’+x’y F2=xy’z’+x’y the to

(Regard of in inputs has circuit number is is 0 output maxterms the the the or 31 1. in range days.
input most
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the for
Design a circuit diagram to implement this function
8. Plot the following function on K map and use the K map to simplify the expression.
F = ABC + CBACBACBACBABCA + + + + CBACBACBACBAF =
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9. Simplify the following expressions by means of Boolean algebra

BCDADCABDCBADCBADCBAF = + + + + + ABCD + DCBADCBA + CABCBACBACBAF = + + + +

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ABC
JN
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Sequential circuit
Introduction
In the previous session, we said that the output of a combinational circuit depends solely upon the input.
The implication is that combinational circuits have no memory. In order to build sophisticated digital logic
circuits, including computers, we need more a powerful model. We need circuits whose output depends
upon both the input of the circuit and its previous state. In other words, we need circuits that have memory.
For a device to serve as a memory, it must have three characteristics:
• the device must have two stable states
• there must be a way to read the state of the device
• there must be a way to set the state at least once.
It is possible to produce circuits with memory using the digital logic gates we've already seen. To do that,
we need to introduce the concept of feedback. So far, the logical flow in the circuits we've studied has been
from input to output. Such a circuit is called acyclic. Now we will introduce a circuit in which the output is
fed back to the input, giving the circuit memory. (There are other memory technologies that store electric
charges or magnetic fields; these do not depend on feedback.)
Latches and flip-flops
In the same way that gates are the building blocks of combinatorial circuits, latches and flip-flops are the
building blocks of sequential circuits.
While gates had to be built directly from transistors, latches can be built from gates, and flip-flops can be
built from latches. This fact will make it somewhat easier to understand latches and flip-flops.
Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but
also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not
have a clock signal, whereas a flip-flop always does.
Latches
How can we make a circuit out of gates that is not combinatorial? The answer is feed-back, which means
that we create loops in the circuit diagrams so that output values depend, indirectly, on themselves. If such
feed-back is positive then the circuit tends to have stable states, and if it is negative the circuit will tend to
oscillate.
In order for a logical circuit to "remember" and retain its logical state even after the controlling input
signal(s) have been removed, it is necessary for the circuit to include some form of feedback. We might
start with a pair of inverters, each having its input connected to the other's output. The two outputs will
always have opposite logic levels.
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The problem with this is that we don't have any additional inputs that we can use to change the logic states
if we want. We can solve this problem by replacing the inverters with NAND or NOR gates, and using the
extra input lines to control the circuit.
The circuit shown below is a basic NAND latch. The inputs are generally designated "S" and "R" for "Set"
and "Reset" respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching
action, the inputs are considered to be inverted in this circuit.
The outputs of any single-bit latch or memory are traditionally designated Q and Q'. In a commercial
latch circuit, either For will allowing its Applying 0 other Note logic control, simultaneously, difference
The "Reset" inputs For force allowing its Applying 1 other The to to output output the the force the the

circuit same that way. way. 1, that or J are NOR NAND respectively. other other while

overriding both that that to it to another another that not in output functions is shown remain remain the
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latch output output of inverted forbidden gate gate output the latch the these logic

to logic logic other circuit, will will below result at at the to to a Because circuit, to can may logic logic
function, in logic rise fall 0 1 cause cause feedback a to input this input input is logic also is both be have

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to to 1. 0 a 0. a both circuit. even "race" the available a the the a (still be basic to to

The 1. but inputs logic logic both same NOR same latching the the The performed inputs after the at same
condition, The NOR 0 inputs 1 same same should same logic logic level. for reaction reaction inputs
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level. the should NOR-based logic action. use latch. gate gate external at

logic 0) involved using This This normally must a by and controls will in will in 0 logic normally The
other 1 In will in in the the the normally NOR will input have have turn this turn latch is 0 inputs other

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other final be also circuits. level quite the also gates. is feeds condition,

feeds no no be at circuit state removed. be resulting direction, direction, a be be are further further at at
similar. logic applied back the a back applied In logic A of generally logic is: any few same the 0 effect
effect whichever to to 0 state level. thus thus case, latch 1 to to the adjustments the to time. level. avoid

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this this the second second That Changing circuit input overriding latch. circuit. circuit. input input be

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state must the the input goes an input "S" determined itself If of state state of will input

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both to for applying applying 1 latch latch a first allow go action, logic gate, NAND gate, "Set" outputs of
1 NOR circuit circuit to level will time. forcing
forcing logic for 0 a a and the
logic
logic level
gate, gate,
lose
will to the the
the 1 a
Note that it is forbidden to have both inputs at a logic 1 level at the same time. That state will force both
outputs to a logic 0, overriding the feedback latching action. In this condition, whichever input goes to logic
0 first will lose control, while the other input (still at logic 1) controls the resulting state of the latch. If both
inputs go to logic 0 simultaneously, the result is a "race" condition, and the final state of the latch cannot
be determined ahead of time.
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One problem with the basic RS NOR latch is that the input signals actively drive their respective outputs to
a logic 0, rather than to a logic 1. Thus, the S input signal is applied to the gate that produces the Q' output,
while the R input signal is applied to the gate that produces the Q output. The circuit works fine, but this
reversal of inputs can be confusing when you first try to deal with NOR-based circuits.
Flip-flops
Latches are asynchronous, which means that the output changes very soon after the input changes. Most
computers today, on the other hand, are synchronous, which means that the outputs of all the sequential
circuits change simultaneously to the rhythm of a global clock signal.
A flip-flop is a synchronous version of the latch.
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are
shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q′, and two inputs, set and reset.
This type of flip-flop is referred to as an SR flip-flop or SR latch. The flip-flop in Figure 2 has two useful
states. When Q=1 and Q′=0, it is in the set state (or 1-state). When Q=0 and Q′=1, it is in the clear state
(or 0 -state). The outputs Q and Q′ are complements of each other and are referred to as the normal and
complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal
output.
When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q′ outputs go
to 0. This condition violates the fact that both outputs are complements of each other. In normal operation
this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.
(a) Logic diagram
(b) Truth table
Figure 2. Basic flip-flop circuit with NOR gates
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(a) Logic diagram
(b) Truth table
Figure 3. Basic flip-flop circuit with NAND gates
The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the state of the
flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q′ to go to 0,
putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition should
be avoided in normal operation.
Clocked SR Flip-Flop
The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two AND gates. The
outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R
input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the
basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily
go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result,
depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the
end of the pulse.
(a) Logic diagram
(b) Truth table
Figure 4. Clocked SR flip-flop
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D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly
into the S input and the complement of the D input goes to the R input. The D input is sampled during the
occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If
it is 0, the flip-flop switches to the clear state.
(a) Logic diagram with NAND gates
(b) Graphical symbol (c) Transition table
Figure 5. Clocked D flip-flop
JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in
the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-
flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K
simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop
is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q′ is ANDed with J and CP
inputs so that the flip-flop is set with a clock pulse only if Q′ was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while
J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of
the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay
through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-
triggered construction. The same reasoning also applies to the T flip-flop presented next.
(a) Logic diagram
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(c) Transition table
Figure 6. Clocked JK flip-flop
T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with
each clock pulse.
(a) Logic diagram
(b) Graphical symbol
(c) Transition table
Triggering of Flip-flops
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger
and the transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require
an input trigger defined by a change in signal level. This level must be returned to its initial level before a
second trigger is applied. Clocked flip-flops are triggered by pulses.
The feedback path between the combinational circuit and memory elements in Figure 1 can produce
instability if the outputs of the memory elements (flip-flops) are changing while the outputs of the
combinational circuit that go to the
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flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to
make the flip- flop sensitive to the pulse transition rather than the pulse duration.
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in
Figure 8 the positive transition is defined as the positive edge and the negative transition as the negative
edge.
Figure 8. Definition of clock pulse transition
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state
transition starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is
still 1, a new output state may occur. If the flip-flop is made to respond to the positive (or negative) edge
transition only, instead of the entire pulse duration, then the multiple-transition problem can be eliminated.
Master-Slave Flip-Flop
A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the
other as a slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is enabled
on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information
at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master
flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the
master flip-flop.
Figure 9. Logic diagram of a master-slave flip-flop
Master slave RS flip flop
The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior to
the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative
transition of the clock
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pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by
having an additional inverter between the CP terminal and the input of the master.
Figure 10. Timing relationship in a master slave flip-flop
Edge Triggered Flip-Flop
Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-
triggered flip- flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out
and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another
pulse occurs. Some edge-triggered flip-flops cause a transition on the positive edge of the clock pulse
(positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered). The logic
diagram of a D-type positive-edge-triggered flip-flop is shown in Figure 11.
Figure 11. D-type positive-edge triggered flip-flop
When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs
make their transitions at the same time, ie., during either the negative edge or the positive edge of the
clock pulse.
Direct Inputs
Flip-flops in IC packages sometimes provide special inputs for setting or clearing the flip-flop
asynchronously. They are usually called preset and clear. They affect the flip-flop without the need for a
clock pulse. These inputs are useful for bringing flip-flops to an intial state before their clocked operation.
For example, after power is turned on in a digital system, the states of the flip-flops are indeterminate.
Activating the clear input clears all the flip-flops to an initial state of 0. The graphic symbol of a JK flip-
flop with an active-low clear is shown in Figure 12.
(a) Graphic Symbol
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(b) Transition table
Figure 12. JK flip-flop with direct clear
Summary
Since memory elements in sequential circuits are usually flip-flops, it is worth summarising the behaviour
of various flip-flop types before proceeding further. All flip-flops can be divided into four basic types: SR,
JK, D and T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip- flops are defined in Table 1.
Table 1. Flip-flop Types
FLIP-FLOP
TYPE
SYMBOL
CHARACTERISTIC TABLE
EXCITATION TABLE
CHARACTERISTIC EQUATION
S R Q(next)
00Q
SR
010
101
11?
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Q Q(next) S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0
JK
Q(next) = S + R′Q
SR = 0
Q Q(next) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0
D
J K Q(next) 0 0 Q 0 1 0 1 0 1 1 1 Q′
Q(next) = JQ′ + K′Q
Q Q(next) D 0 0 0 0 1 1 1 0 0 1 1 1
T
D Q(next) 0 0 1 1
Q(next) = D
Q Q(next) T T Q(next)
0000Q
Q(next) = TQ′ + T′Q
0 1 1 1 Q′
101110
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Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its
characteristic equation or excitation table. All flip-flops have output signals Q and Q′.
The characteristic table in the third column of Table 1 defines the state of each flip-flop as a function of its
inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the
occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is equal
to the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears the flip-
flop. When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next state when S and R
are both equal to 1 designates an indeterminate next state.
The respectively, complement The The The and table, column During flop inputs 1. the is,
Synchronous asynchronous affected Gate-type among Synchronous at circuits either circuit.
throughout Synchronous and A cycle Moore clock There discrete it information their we next next

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characteristic input characteristic does time we 0 for logic the want have

Synchronization of or signal at are state state timing can not and a Table conditions asynchronous or any
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Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry
Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only
Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The
models selected will influence a design but there are no general indications as to which model is better.
Choice of a model depends on the application, execution means (for instance, hardware systems are usually
best realised as Moore models) and personal preferences of a designer or programmer. In practise, mixed
models are often used with several action types Downloaded From JNTU World (http://www.alljntuworld.in)
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Design of Sequential Circuits
The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic
diagram or a list of Boolean functions from which a logic diagram can be obtained. In contrast to a
combinational logic, which is fully specified by a truth table, a sequential circuit requires a state table for
its specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit
consists of choosing the flip-flops and then finding the combinational structure which, together with the
flip-flops, produces a circuit that fulfils the required specifications. in the circuit.
The recommended steps for the design of sequential Analysis We is input. states State The output.

represented have state and These J Table The examined next table present of also by

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states representation a a determine sequential state a state can general of be
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From JNTU World (http://www.alljntuworld.in) The number of flip-flops is determined circuits are set out
below:
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circuits. In this model the effect of the output of the

circuit at any time depends the circuit. The relationship that exists the state table or the state diagram.

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circuit consists of three sections labelled of flip-flops before the occurrence of a from the
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number of states needed

all previous inputs on the outputs upon its current state and the among the inputs, outputs, present
present state, next state and clock pulse. The next state shows the states of flip-flops after the clock pulse,
and the output section lists the value of the output variables during the present state.
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State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically by a
state diagram. In this diagram, a state is represented by a circle, and the transition between states is indicated
by directed lines (or arcs) connecting the circles. An example of a state diagram is shown in Figure 3 below.
Figure 3. State Diagram
The binary number inside each circle identifies the state the circle represents. The directed lines are labelled
with two binary numbers separated by a slash (/). The input value that causes the state transition is labelled
first. The number after the slash symbol / gives the value of the output. For example, the directed line from
state 00 to 01 is labelled 1/0, meaning that, if the sequential circuit is in a present state and the input is 1,
then the next state is 01 and the output is 0. If it is in a present state 00 and the input is 0, it will remain in
that state. A directed line connecting a circle with itself indicates that no change of state occurs. The state
diagram provides exactly the same information as the state table and is obtained directly from the state
table.
Example: Consider a sequential circuit shown in Figure 4. It has one input x, one output Z and two state
variables Q1Q2 (thus having four possible present states 00, 01, 10, 11).
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Figure 4. A Sequential Circuit
The behaviour of the circuit is determined by the following Boolean expressions:
Z = xQ1 D1 = x′ + Q1 D2 = xQ2′ + x′*Q1′
These equations can be used to form the state table. Suppose the present state (i.e. Q1Q2) = 00 and input x

= 0. Under these conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state of the circuit D1D2 =

11, and this will be the present state after the clock pulse has been applied. The output of the circuit
corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This data is entered into the state table

as shown in Table 2.
Present State
Next State
Q1 Q2
X = 0 Q1 Q0
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Output (Z)
x=0x=1
00011011
X = 1 Q1 Q0
00000101
Table 2. State table for the sequential circuit in Figure 4.
The state diagram for the sequential circuit in Figure 4 is shown in Figure 5.
Figure 5. State Diagram of circuit in Figure 4.
1101110010111010

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State Diagrams of Various Flip-flops
Table 3 shows the state diagrams of the four types of flip-flops.
NAME STATE DIAGRAM
SR JK D Table You set enter transitions.

A components. state state can the 3. J when State diagram see same from diagrams Q=1
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have the same number Also, each flip-flop the four types lies visualise the
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operation of states and transitions.

Each can move from one state to another, in the values of input signals of a flip-flop or even of flip-flop is
in the or it can re- that cause these
large sequential