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A Proforma

This document provides details of a major project being undertaken by 4 students on developing application-specific low power multipliers. The project involves designing two types of low power multipliers - selective activation multiplier and partitioned multiplier - and implementing them using Xilinx tools. The multipliers are intended for applications like DCT and DWT. The abstract indicates that the proposed techniques aim to reduce power consumption with moderate increases in area and time.

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SaiKishore
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56 views1 page

A Proforma

This document provides details of a major project being undertaken by 4 students on developing application-specific low power multipliers. The project involves designing two types of low power multipliers - selective activation multiplier and partitioned multiplier - and implementing them using Xilinx tools. The multipliers are intended for applications like DCT and DWT. The abstract indicates that the proposed techniques aim to reduce power consumption with moderate increases in area and time.

Uploaded by

SaiKishore
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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MAJOR PROJECTS (A.Y.

2016-17)

Guru Nanak Institutions Technical Campus


School of Engineering and Technology
Department of Electronics and Communication Engineering
ABSTRACT – PROFORMA
(To be submitted by the Students)

Title of the Project APPLICATION-SPECIFIC LOW POWER MULTIPLIERS

Area of Specialization VLSI


Tools Used Xilinx ISE 9.1/13.2, ModelSim 6.4c, FPGA Spartan 6
Implementation Method(s) Simulation and Emulation
Going to Publish Paper? Y/N: YES
STUDENT REGISTRATION DETAILS GUIDE DETAILS
Name Roll Numbers Mobile Number Ms.S.SWETHA
1. K SAI KISHORE 13WJ1A04j8 9490191434 Associate Professor
2. K RAMA RAO 13WJ1A04L3 8686482562 Dept. of ECE
3. J NAVEEN KUMAR 14WJ5A0418 9618290903 GNITC
4. NA NA 9603234508
Sai.kondamudi@gmail.com Swetha.sandiri@gmail.com
Raghukoya87@gmail.com
Naveenkumarjadi05@gmail.com

ABSTRACT

The multipliers are mainly focusing for low power. Here proposed two architectures for two inputs
signed multipliers namely selective activation multiplier and partitioned multiplier. The proposed
technique is mainly applied in DCT and DWT Application. Power is reduced. The proposed
multiplier is applied to all low power techniques with moderate area and time overhead.

Signature of the Students Signature of the Guide

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