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Decoder: Dataflow Model

The document describes three different models - dataflow, behavioral, and structural - for implementing a 2-input decoder circuit. The dataflow model uses logic gates to assign outputs based on inputs and their complements. The behavioral model uses a case statement within an always block to set the outputs based on the input values. The structural model instantiates logic gates like NOT and AND to build the decoder functionality. A testbench is also provided to simulate and verify the behavioral model.

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Ravi Kiran
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40 views5 pages

Decoder: Dataflow Model

The document describes three different models - dataflow, behavioral, and structural - for implementing a 2-input decoder circuit. The dataflow model uses logic gates to assign outputs based on inputs and their complements. The behavioral model uses a case statement within an always block to set the outputs based on the input values. The structural model instantiates logic gates like NOT and AND to build the decoder functionality. A testbench is also provided to simulate and verify the behavioral model.

Uploaded by

Ravi Kiran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DECODER

DATAFLOW MODEL:
module dec24dataflw(a,b,en,y);
input a,b,en;
output [3:0]y;
wire abar,bbar;
assign abar=~a;
assign bbar=~b;
assign y[0]=abar&bbar&en;
assign y[1]=abar&b&en;
assign y[2]=a&bbar&en;
assign y[3]=a&b&en;
endmodule

BEHAVIOURAL MODEL:
module decoder24(EN,A0,A1,D3,D2,D1,D0);
input EN,A0,A1;
output D3,D2,D1,D0;
reg D3,D2,D1,D0;
always@(*)
begin
if(EN==1'b1)
{D3,D2,D1,D0}=4'd0;
else
begin
case({A1,A0})
2'b00:{D3,D2,D1,D0}=4'b0001;
2'b01:{D3,D2,D1,D0}=4'b0010;
2'b10:{D3,D2,D1,D0}=4'b0100;
2'b11:{D3,D2,D1,D0}=4'b1000;
default:{D3,D2,D1,D0}=4'b0000;
endcase
end
end
endmodule

STRUCTURAL MODEL:
module decoder(a,b,y);
input a,b;
output [3:0]y;
wire w1,w2;
not (w1,a);
not (w2,b);
and (y[0],w1,w2);
and (y[1],w1,b);
and (y[2],a,w2);
and (y[3],a,b);
endmodule
TESTBENCH:
module decoder_tb;
// Inputs
reg EN;
reg A0;
reg A1;
// Outputs
wire D3;
wire D2;
wire D1;
wire D0;
// Instantiate the Unit Under Test (UUT)
decoder24 uut (
.EN(EN),
.A0(A0),
.A1(A1),
.D3(D3),
.D2(D2),
.D1(D1),
.D0(D0)
);

initial begin
// Initialize Inputs
EN = 1;
#10 EN = 0;
A0 = 0;A1 = 0;
#10 A0 = 0;A1 = 1;
#10 A0 = 1;A1 = 0;
#10 A0 = 1;A1 = 1;
// Wait 100 ns for global reset to finish
#100
// Add stimulus here
end
initial #100 $stop;
endmodule

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