BINARY TO GRAY 4 BIT CONVERTOR

module binary_gray(
input b0,b1,b2,b3,
output g0,g1,g2,g3
);
assign g0 = b0;
assign g1 = b0^b1;
assign g2 = b1^b2;
assign g3 = b2^b3;

endmodule

module binary_gray_tb();
reg b0,b1,b2,b3;
wire g0,g1,g2,g3;
binary_gray uut(b0,b1,b2,b3,g0,g1,g2,g3);
initial
Begin
b0=0;b1=0;b2=0;b3=0;#10
b0=0;b1=0;b2=0;b3=1;#10
b0=0;b1=0;b2=1;b3=0;#10
b0=0;b1=0;b2=1;b3=1;#10
b0=0;b1=1;b2=0;b3=0;#10
b0=0;b1=1;b2=0;b3=1;#10
b0=0;b1=1;b2=1;b3=0;#10
b0=0;b1=1;b2=1;b3=1;#10
b0=1;b1=0;b2=0;b3=0;#10
b0=1;b1=0;b2=0;b3=1;#10
b0=1;b1=0;b2=1;b3=0;#10
b0=1;b1=0;b2=1;b3=1;#10
b0=1;b1=1;b2=0;b3=0;#10
b0=1;b1=1;b2=0;b3=1;#10
b0=1;b1=1;b2=1;b3=0;#10
b0=1;b1=1;b2=1;b3=1;#10
$finish;
end
endmodule
1 BIT COMPARATOR

module onebit_comparator(
input a,b,
output y1,y2,y3
);
assign y1 = ((~a)&(~b))|(a&b);
assign y2 = a&(~b);
assign y3 = (~a)&b;

endmodule

module onebit_tb();
reg a,b;
wire equal,greater,smaller;
onebit_comparator uut(a,b,equal,greater,smaller);
initial
begin
a=0;b=0;#10
a=0;b=1;#10
a=1;b=0;#10
a=1;b=1;#10
$finish;
end
endmodule
2 BIT COMPARATOR

module twobit_comparator(
input a1,a0,b1,b0,
output y1,y2,y3
);
assign y1 = (~a1&b1)|(~a1&~a0&b0)|(~a0&b1&b0);
assign y2 = (a1&~b1)|(a1&a0&~b0)|(a0&~b1&~b0);
assign y3 = (a1~^b1)|(a0~^b0);

endmodule

module twobit_tb();
reg a1,a0,b1,b0;
wire y1,y2,y3;
twobit_comparator uut(a1,a0,b1,b0,y1,y2,y3);
initial
begin
a1=0;a0=0;b1=0;b0=0;#10
a1=0;a0=0;b1=0;b0=1;#10
a1=0;a0=0;b1=1;b0=0;#10
a1=0;a0=0;b1=1;b0=1;#10
a1=0;a0=1;b1=0;b0=0;#10
a1=0;a0=1;b1=0;b0=1;#10
a1=0;a0=1;b1=1;b0=0;#10
a1=0;a0=1;b1=0;b0=1;#10
a1=1;a0=0;b1=0;b0=0;#10
a1=1;a0=0;b1=0;b0=1;#10
a1=1;a0=0;b1=1;b0=0;#10
a1=1;a0=0;b1=1;b0=1;#10
a1=1;a0=1;b1=0;b0=0;#10
a1=1;a0=1;b1=0;b0=1;#10
a1=1;a0=1;b1=1;b0=0;#10
a1=1;a0=1;b1=1;b0=1;#10
$finish;
end
endmodule
NAND imp

module imp_NAND(
input a,b,c,d,
output y
);
assign y = ~(~(a&b)&~(c&d));
endmodule

module imp_NAND_tb();
reg a,b,c,d;
wire y;
imp_NAND uut(a,b,c,d,y);
initial
begin
a=0;b=0;c=0;d=0;#10
a=0;b=0;c=0;d=1;#10
a=0;b=0;c=1;d=0;#10
a=0;b=0;c=1;d=1;#10
a=0;b=1;c=0;d=0;#10
a=0;b=1;c=0;d=1;#10
a=0;b=1;c=1;d=0;#10
a=0;b=1;c=1;d=1;#10
a=1;b=0;c=0;d=0;#10
a=1;b=0;c=0;d=1;#10
a=1;b=0;c=1;d=0;#10
a=1;b=0;c=1;d=1;#10
a=1;b=1;c=0;d=0;#10
a=1;b=1;c=0;d=1;#10
a=1;b=1;c=1;d=0;#10
a=1;b=1;c=1;d=1;#10
$finish;
end
endmodule
FOUR ONE MUX

module four_one_mux(
input x1,x2,x3,x4,s0,s1,
output y
);
assign y = s1 ? (s0 ? x4 : x3) : (s0 ? x2 : x1);

endmodule

module four_one_mux_tb();
reg x1,x2,x3,x4,s0,s1;
wire y;
four_one_mux uut (x1,x2,x3,x4,s0,s1,y);
initial
begin
x1 = 1;
x2 = 0;
x3 = 1;
x4 = 0;
s1 = 0;s0 = 0;#10
s1 = 0;s0 = 1;#10
s1 = 1;s0 = 0;#10
s1 = 1;s0 = 1;#10
$finish;
end
endmodule
2 TO 4 DECODER

module decoder_2_4(
input en,a,b,
output [3:0]y
);
assign y[0] = (en & ~a & ~b);
assign y[1] = (en & ~a & b);
assign y[2] = (en & a & ~b);
assign y[3] = (en & a & b);

endmodule

module decoder_2_4_tb();
reg en,a,b;
wire [3:0]y;
decoder_2_4 uut(en,a,b,y);
initial
begin
en = 0;a = 0;b = 0;#10
en = 0;a = 0;b = 1;#10
en = 0;a = 1;b = 0;#10
en = 0;a = 1;b = 1;#10
en = 1;a = 0;b = 0;#10
en = 1;a = 0;b = 1;#10
en = 1;a = 1;b = 0;#10
en = 1;a = 1;b = 1;#10
$finish;
end
endmodule
4 to 2 encoder

module encoder_4_2(
input y3,y2,y1,y0,
output a1,a0
);
assign a0 = y1 | y3;
assign a1 = y2 | y3;
endmodule

module encoder_4_2_tb();
reg y3,y2,y1,y0;
wire a1,a0;
encoder_4_2 uut(y3,y2,y1,y0,a1,a0);
initial
begin
y3 = 0;y2 = 0;y1 = 0;y0 = 1;#10
y3 = 0;y2 = 0;y1 = 1;y0 = 0;#10
y3 = 0;y2 = 1;y1 = 0;y0 = 0;#10
y3 = 1;y2 = 0;y1 = 0;y0 = 0;#10
$finish;
end
endmodule
3 to 8 DECODER

module decoder_3_8(
input a,b,c,
output [7:0]y
);
assign y[0] =~a &~b &~c;
assign y[7] =(a & b & c);
assign y[6] = a & b & ~c;
assign y[5] = a & ~b & c;
assign y[4] =a & ~b & ~c;
assign y[3] =~a & b & c;
assign y[2] =~a & b & ~c;
assign y[1] =~a &~b & c;

endmodule

module decoder_3_8_tb( );
reg a,b,c;
wire [7:0]y;
decoder_3_8 uut (a,b,c,y);
initial
begin
a=0;b=0;c=0;#10
a=0;b=0;c=1;#10
a=0;b=1;c=0;#10
a=0;b=1;c=1;#10
a=1;b=0;c=0;#10
a=1;b=0;c=1;#10
a=1;b=1;c=0;#10
a=1;b=1;c=1;#10
$finish;
end
endmodule
8 to 3 ENCODER

module encoder_8_3(
input [7:0]y,
output [2:0]a
);
assign a[2]=y[7]|y[5]|y[3]|y[1];
assign a[1]=y[2]|y[3]|y[6]|y[7];
assign a[0]=y[7]|y[6]|y[5]|y[4];
endmodule

module encoder_8_3_tb();
reg [7:0] y;
wire [2:0] a;
encoder_8_3 uut(y,a);
initial
begin
y=8'b00000001;#10

y = 8'b00000010;#10
y = 8'b00000100;#10
y = 8'b00001000;#10
y = 8'b00010000;#10
y = 8'b00100000; #10
y = 8'b01000000;#10
y = 8'b10000000;#10
$finish;
end
endmodule
HALF ADDER STRUCTURAL

module half_adder_stuctural(
input a,b,
output sum,carry
);
xor_gate gate1 (a,b,sum);
and_gate gate2 (a,b,carry);
endmodule

module xor_gate(
input a,b,
output c
);
assign c = a^b;
endmodule

module and_gate(
input a,b,
output c
);
assign c = a&b;
endmodule

module half_structural_tb();
reg a,b;
wire sum, carry;
half_adder_stuctural uut(a,b,sum,carry);
initial
begin
a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
#10 $finish;
end
endmodule
FULL ADDER STRUCTURAL

module full_adder_structural(
input a,b,c,
output sum,carry
);
wire w1,w2,w3;
half_adder_stuctural ha1(a,b,w1,w2);
half_adder_stuctural ha2(c,w1,sum,w3);
or(carry,w2,w3);

endmodule

module half_adder_stuctural(
input a,b,
output sum,carry
);
xor_gate gate1 (a,b,sum);
and_gate gate2 (a,b,carry);
endmodule

module full_adder_structural_tb();
reg a,b,c;
wire sum,carry;
full_adder_structural uut(a,b,c,sum,carry);
initial
begin
a=0;b=0;c=0;
#10a=0;b=0;c=1;
#10a=0;b=1;c=0;
#10a=0;b=1;c=1;
#10a=1;b=0;c=0;
#10a=1;b=0;c=1;
#10a=1;b=1;c=0;
#10a=1;b=1;c=1;
#10 $finish;
end
endmodule
4:2 mux using 2:1 structural model

module not_gate(
input a,
output y
);
assign y = ~a;
endmodule

module or_gate(
input a,b,
output y
);
assign y = a|b;
endmodule

module and_gate(
input a,b,
output c
);
assign c = a&b;
endmodule

module mux2x1(
input i0,i1,s0,
output y
);
wire x1,x2,x3;
not_gate gate1 (s0,x1);
and_gate gate2 (x1,i0,x2);
and_gate gate3 (s0,i1,x3);
or_gate gate4 (x2,x3,y);
endmodule

module mux4X1(
input i0,i1,i2,i3,s0,s1,
output y
);
wire x1,x2;
mux2x1 mux1 (i0,i1,s1,x1);
mux2x1 mux2 (i2,i3,s1,x2);
mux2x1 mux3 (x1,x2,s0,y);

endmodule
module mux4X1(
input i0,i1,i2,i3,s0,s1,
output y
);
wire x1,x2;
mux2x1 mux1 (i0,i1,s1,x1);
mux2x1 mux2 (i2,i3,s1,x2);
mux2x1 mux3 (x1,x2,s0,y);

endmodule
4:2 encoder using structural

module or_gate(
input a,b,
output y
);
assign y = a|b;
endmodule

module encoder_4_2(
input y3,y2,y1,y0,
output a1,a0
);
or_gate gate1(y1,y3,a0);
or_gate gate2(y2,y3,a1);
endmodule

module encoder_4_2_tb();
reg y3,y2,y1,y0;
wire a1,a0;
encoder_4_2 uut(y3,y2,y1,y0,a1,a0);
initial
begin
y3 = 0;y2 = 0;y1 = 0;y0 = 1;#10
y3 = 0;y2 = 0;y1 = 1;y0 = 0;#10
y3 = 0;y2 = 1;y1 = 0;y0 = 0;#10
y3 = 1;y2 = 0;y1 = 0;y0 = 0;#10
$finish;
end
endmodule
2:4 decoder using structural

module and_gate(
input a,b,c,
output y
);
assign y = a&b&c;
endmodule

module not_gate(
input a,
output y
);
assign y = ~a;
endmodule

module decoder_2_4(
input en,a,b,
output [3:0]y
);
wire x1,x2;
not_gate gate1 (a,x1);
not_gate gate2 (b,x2);
and_gate gate3 (en,x1,x2,y[0]);
and_gate gate4 (en,x1,b,y[1]);
and_gate gate5 (en,a,x2,y[2]);
and_gate gate6 (en,a,b,y[3]);
endmodule

module decoder_2_4_tb();
reg en,a,b;
wire [3:0]y;
decoder_2_4 uut(en,a,b,y);
initial
begin
en = 0;a = 0;b = 0;#10
en = 0;a = 0;b = 1;#10
en = 0;a = 1;b = 0;#10
en = 0;a = 1;b = 1;#10
en = 1;a = 0;b = 0;#10
en = 1;a = 0;b = 1;#10
en = 1;a = 1;b = 0;#10
en = 1;a = 1;b = 1;#10
$finish;
end
endmodule
8:3 encoder using structural

module or_gate(
input a,b,c,d,
output y
);
assign y = a|b|c|d;
endmodule

module encoder_8_3(
input [7:0]y,
output [2:0]a
);
or_gate gate1(y[7],y[5],y[3],y[1],a[0]);
or_gate gate2(y[7],y[6],y[3],y[2],a[1]);
or_gate gate3(y[7],y[6],y[5],y[4],a[2]);
endmodule

module encoder_8_3_tb();
reg [7:0] y;
wire [2:0] a;
encoder_8_3 uut(y,a);
initial
begin
y = 8'b00000001;#10
y = 8'b00000010;#10
y = 8'b00000100;#10
y = 8'b00001000;#10
y = 8'b00010000;#10
y = 8'b00100000; #10
y = 8'b01000000;#10
y = 8'b10000000;#10
$finish;
end
endmodule
3:8 decoder using structural

module not_gate(
input a,
output y
);
assign y = ~a;
endmodule

module and_gate(
input a,b,c,
output y
);
assign y = a&b&c;
endmodule

module decoder_3_8(
input a,b,c,
input [7:0]y
);
wire x1,x2,x3;
not_gate gate1(a,x1);
not_gate gate2(b,x2);
not_gate gate3(c,x3);
and_gate gate4(a,b,c,y[7]);
and_gate gate5(a,b,x3,y[6]);
and_gate gate6(a,x2,c,y[5]);
and_gate gate7(a,x2,x3,y[4]);
and_gate gate8(x1,b,c,y[3]);
and_gate gate9(x1,b,x3,y[2]);
and_gate gate10(x1,x2,c,y[1]);
and_gate gate11(x1,x2,x3,y[0]);
endmodule

module decoder_3_8_tb();
reg a,b,c;
wire [7:0]y;
decoder_3_8 uut (a,b,c,y);
initial
begin
a=0;b=0;c=0;#10
a=0;b=0;c=1;#10
a=0;b=1;c=0;#10
a=0;b=1;c=1;#10
a=1;b=0;c=0;#10
a=1;b=0;c=1;#10
a=1;b=1;c=0;#10
a=1;b=1;c=1;#10
$finish;
end
endmodule
SR latch