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DSP Processors & Architecture: Course Code:13EC1138 L TPC 4 0 0 3

This document outlines a course on DSP processors and architecture. The course objectives are to impart knowledge of DSP filters, number systems, A/D and D/A conversion errors, and digital signal processing techniques. The course outcomes include comprehending DSP techniques, implementing DSP and FFT algorithms, and programming a TMS320C54XX processor. The course contains 5 units that cover topics such as sampling, the DFT and FFT, filters, DSP architectures, programming DSP devices, implementing DSP algorithms, and interfacing memory and I/O peripherals. Required textbooks and references are also listed.

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Abhijit Challapalli
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178 views

DSP Processors & Architecture: Course Code:13EC1138 L TPC 4 0 0 3

This document outlines a course on DSP processors and architecture. The course objectives are to impart knowledge of DSP filters, number systems, A/D and D/A conversion errors, and digital signal processing techniques. The course outcomes include comprehending DSP techniques, implementing DSP and FFT algorithms, and programming a TMS320C54XX processor. The course contains 5 units that cover topics such as sampling, the DFT and FFT, filters, DSP architectures, programming DSP devices, implementing DSP algorithms, and interfacing memory and I/O peripherals. Required textbooks and references are also listed.

Uploaded by

Abhijit Challapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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191

DSP PROCESSORS & ARCHITECTURE


(Elective-IV)

Course Code:13EC1138 L T P C
4 0 0 3
Pre requisites:
Knowledge of signals and systems, convolution methods, digital signal
processing concepts must be known.
Course Educational Objectives:
✤ To impart the knowledge of basic DSP filters and number systems
to be used, different types of A/D,D/A conversion errors.
✤ To gain concepts of digital signal processing techniques,
implementation of DSP & FFT algorithms and also to learn about
interfacing of serial & parallel communication devices to the
processor.
Course Outcomes :
✤ Comprehends the knowledge & concepts of digital signal processing
techniques, basic building blocks, implementation of DSP & FFT
algorithms.
✤ Programming the DSP TMS320C54XX PROCESSOR and
decimation interpolation filters, adaptive filters.
✤ Learn about interfacing of serial & parallel communication devices
to the processor.
UNIT-I (13 lectures)
INTRODUCTION :
Introduction, Digital signal-processing system, The sampling process,
Discrete time sequences. Discrete Fourier Transform (DFT) and Fast
Fourier Transform (FFT), Linear time-invariant systems, Digital filters,
G V P College of Engineering (Autonomous) 2013
192

Decimation and interpolation,Number formats for signals and coefficients


in DSP systems, Dynamic Range and Precision, Sources of error in DSP
implementations, A/D Conversion errors, DSP Computational errors, D/
A Conversion Errors.
UNIT-II (12 lectures)
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES:
Basic Architectural features, DSP Computational Building Blocks, Bus
Architecture and Memory, Data Addressing Capabilities, Address
Generation Unit, Programmability and Program Execution, Speed Issues,
Hardware looping, Interrupts, Stacks, Relative Branch support, Pipelining
and Performance, Pipeline Depth, Interlocking, Branching effects, Interrupt
effects, Pipeline Programming models.
UNIT-III (11 lectures)
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS :
Commercial Digital signal-processing Devices, Data Addressing modes
of TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX
Processors, Memory space of TMS320C54XX Processors, Program
Control, TMS320C54XX instructions and Programming, On-Chip
Peripherals, Interrupts of TMS320C54XX processors, Pipeline Operation
of TMS320C54XX Processors.
UNIT-IV (11 lectures)
IMPLEMENTATIONS OF BASIC DSP ALGORITHMS :
The Q-notation, FIR Filters, IIR Filters, Interpolation Filters, Decimation
Filters, PID Controller, Adaptive Filters, An FFT Algorithm for DFT
Computation, A Butterfly Computation, Overflow and scaling, Bit-
Reversed index generation, An 8-Point FFT implementation on the
TMS320C54XX, Computation of the signal spectrum.
UNIT-V (13 lectures)
INTERFACING MEMORY AND I/O PERIPHERALS TO
PROGRAMMABLE DSP DEVICES:
Memory space organization, External bus interfacing signals, Memory

G V P College of Engineering (Autonomous) 2013


193

interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O,


Direct memory access (DMA).
A Multichannel buffered serial port (McBSP), McBSP Programming, a
CODEC interface circuit, CODEC programming, A CODEC-DSP
interface example.
TEXT BOOKS:
1. Avtar Singh and S. Srinivasan, “Digital Signal Processing”
Thomson Publications, 2004.
2. Lapsley et al., “DSP Processor Fundamentals, Architectures
& Features”, S. Chand & Co, 2000.
REFERENCES:
1. B. Venkata Ramani and M. Bhaskar, “Digital Signal
Processors, Architecture, Programming and Applications”,
TMH, 2004.
2. Jonatham Stein, “Digital Signal Processing”, John Wiley,
2000

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G V P College of Engineering (Autonomous) 2013

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