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The PIC18 Microcontroller

The processor
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Registers -- storage locations in the processor

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Arithmetic logic unit

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Control unit

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pprogram
g counter contains the address of the next instruction to be executed
status register flags the instruction execution result

The microprocessor

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A processor implemented on a very large scale integration (VLSI) chip

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Peripheral chips are needed to construct a product

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The Microcontroller
The processor and peripheral functions implemented on one VLSI chip

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LSN 2 – Microchip’s MCU Families

10 – 12 MIPS
Up to 128 KB Program Flash
18 – 100 Pins

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 The PIC18 Microcontroller

Features of the PIC18 microcontroller

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- 8-bit CPU
- 2 MB program memory space
- 256 bytes to 1KB of data EEPROM
- Up to 3968 bytes of on-chip SRAM
- 4 KB to 128KB flash program memory
- Sophisticated timer functions that include: input capture, output compare,
PWM, real-time interrupt, and watchdog timer
- Serial communication interfaces: SCI,
SCI SPI,
SPI I2C,
I2C and CAN
- Background debug mode (BDM)
- 10-bit A/D converter
- M
Memory protection
t ti capability
bilit
- Instruction pipelining
- Operates at up to 40 MHz crystal oscillator

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 The PIC18 Microcontroller

Embedded Systems

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- A product that uses one or more microcontrollers as controller (s).
- End users are only interested in the functionality of the product but not on
the microcontroller itself.
- Cell phones, home security system, automobiles, and many other products
are examples of embedded products.

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LSN 2 – Processor Architecture Review

• Harvard
– Separate data and program memory space (busses)
• Von-Neumann
– Only one bus between CPU and memory

Von Neumann
Harvard
Architecture Architecture

8-bit Bus Data

Memory

16-bit Bus
CPU 8-bit Bus Program
& Data
Memory
Program CPU
Memory

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LSN 2 – Processor Architecture Review

• RISC
– A minimal set of simple instructions when combined can
accomplish every needed operation
• CISC
– A large set of complex instructions can singularly provide all
needed operations

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 The PIC18 Microcontroller

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The PIC18 Memory Organization

- Data Memory and Program Memory are separated

- Separation of data memory and program memory makes possible the

simultaneous access of data and instruction.

- Data memory are used as general-purpose registers or special function registers

- On-chipp Data EEPROM are pprovided in some PIC18 MCUs

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 The PIC18 Microcontroller

Separation of Data Memory and Program Memory

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Inside the c chip

Program 21-bit progam address 12-bit register address Data

Memory Memory
Space Space
(a portion
PIC18 (Special
of this function
space is on CPU
registers and
th c
the generall
16-bit instruction bus 8-bit data bus
chip) purpose
RAM)

Figure 1.3 The PIC18 memory spaces

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LSN 2 – 8-bit PIC® Architecture

Program Space Data Space

21-bit Table Access 12-bit Data RAM

Program
Peripherals
Flash
Program Bus Data Bus
16-bit 8-bit CPU 8-bit
I/O Ports

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LSN 2 – PIC18 Program Memory Map

Reset Vector 000000h

High Priority Interrupt Vector 000008h

Low Priority Interrupt Vector 000018h

21-bit Program Counter On-chip Program Memory

007FFEh

Stack Level 1 008000h

Stack Level 2

Stack Level 30
Unimplemented
Stack Level 31
Program Memory
(Read as ‘0’)
31 Level Stack
1FFFFEh

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LSN 2 – PIC18 Data Memory Map

ACCESS RAM PIC18F

Register File Map
Bank 0 GPR

Bank 1 GPR

Bank 2 GPR

ACCESS RAM
ACCESS SFR

Bank 13 GPR

Bank 14 GPR

Bank 15 GPR

ACCESS SFR

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LSN 2 – PIC18 Registers

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 The PIC18 Microcontroller

PIC18 Data Memory

- Implemented in SRAM and consists of general-purpose registers and

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special-function registers. Both are referred to as data registers.
- A PIC18
C 8 MCU
CU may
ay have
ave up to 4096
096 bytes oof data memory.
e o y.
- Data memory is divided into banks. Each bank has 256 bytes.
- General-purpose registers are used to hold dynamic data.
- Special-function registers are used to control the operation of peripheral
functions.
- Only one bank is active at any time. The active bank is specified by the BSR
register.
register
- Bank switching is an overhead and can be error-prone
- PIC18 implements the access bank to reduce the problem caused by bank
switching.
- Access bank consists of the lowest 96 bytes and the highest 160 bytes of the
data memory space.

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 The PIC18 Microcontroller

Program Memory Organization

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- The program counter (PC) is 21-bit long, which enables the user program to
access up to 2 MB of program memory.
- The PIC18 has a 31-entry return address stack to hold the return address for
subroutine call.
- After power-on, the PIC18 starts to execute instructions from address 0.
- The location at address 0x08 is reserved for high-priority interrupt service
routine.
- The location at address 0x18 is reserved for low
low-priority
priority interrupt service
routine.
- Up to 128KB (at present time) of program memory is inside the MCU chip.
- Part
P t off the
th program memory is
i located
l t d outside
t id off the
th MCU chip.
hi

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LSN 2 – PIC18 Registers

• Status register
– Contains arithmetic status of the ALU
– Bits set or cleared according to the device logic

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LSN 2 – PIC18 Programmer’s Model

Register File Program

(RAM) Memory
(Flash)
FSRn
ALU TBLPTR Constant
TABLAT Data
PC
BSR
WREG
STATUS
TOS
Stack
STKPTR

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LSN 2 – PIC18 Pipelining

• Allows processor to overlap the execution of several

instruction to achieve higher instruction throughput
– Utilizes the fact that different processor components are not
fully utilized during the instruction execution process
– Prefetches instructions during execution of current
instructions

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 The PIC18 Microcontroller

The PIC18 Pipelining

p g

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- The PIC18 Divide most of the instruction execution into two stages: instruction
fetch and instruction execution.
- Up to two instructions are overlapped in their execution.
execution One instruction is in
fetch stage while the second instruction is in execution stage.
- Because of pipelining, each instruction appears to take one instruction cycle to
complete.
complete
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

MOVLW 55h fetch 1 execute 1

MOVWF PORTB fetch 2 execute 2
BRA sub_1 fetch 3 execute 3
BSF PORTA,BIT3 fetch 4 flush
Instruction @address sub_1 fetch sub_1 execute
sub_1
Note: All instructions are single cycle, except for any program branches.

Figure 1.7 An example of instruction pipeline flow

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LSN 2 – PIC18 Instruction Format

Data Memory
(Register File)

w f 07h

ALU 08h

09h

Data Bus
0Ah

0Bh
d
w f 0Ch

0Dh

0Eh

0Fh

10h
WREG

Decoded Instruction
Opcode d a Address
from Program
Memory:
Arithmetic/Logic Function
to be Performed Result
Destination
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 The PIC18 Microcontroller

Instruction Format

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- Format for byte oriented instructions

15 10 9 8 7 0
opcode d a f

d = 0 for result destination to be WREG register.

d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Figure 1.8 Byte-oriented file register operations (redraw with permission of
Microchip)

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 The PIC18 Microcontroller

Byte-to-byte Operations

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15 12 11 0
opcode f (source file register)
15 12 11 0
1111 f (destination file register)

f = 12-bit file register address

Figure 1.9 Byte to byte move operations (2 words) (redraw with permission of Microchip)

Bit-oriented file register operations

15 12 11 9 8 7 0
opcode b a f

b = 3-bit position of bit in the file register (f).

a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Figure 1.10
1 10 Bit-oriented
Bit oriented file register operations (redraw with permission of
Microchip)

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 The PIC18 Microcontroller

Literal operations

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- A literal is a number to be operated on directly by the CPU

15 8 7 0
opcode k

k = 8-bit immediate value

Figure 1.11 Literal operations (redraw with permission of Microchip)

Control operations

- These instructions are used to change the program execution sequence and
making subroutine calls.

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 The PIC18 Microcontroller

15 8 7 0

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opcode n<7:0> (literal)
15 8 7 0 GOTO label
1111 n<19:8> (literal)
n = 20-bit immediate value
15 8 7 0
opcode S n<7:0> (literal)
15 8 7 0 CALL funct_name
1111 n<19:8> (literal)
S = fast bit
15 11 10 0
opcode n<10:0> (literal) BRA label
15 8 7 0
opcode n<7:0> (literal) BC label

Figure 1.12 Control operations (redraw with permission of Microchip)

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 The PIC18 Microcontroller

Access Bank

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- In Figures 1.8 to 1.12, PIC18 uses 8 bits to specify a data register (f field).
- Eight bits can specify only 256 registers.
- This limitation forces the PIC18 to divide data registers (up to 4096 bytes) into
banks.
- Onlyy one bank is active at a time.
- When operating on a data register in a different bank, bank switching is
needed.
- Bank switching incurs overhead and may cause program errors.
errors
- Access bank is created to minimize the problems of bank switching.
- Access bank consists of the lowest 96 bytes in general-purpose registers and the
highest 160 bytes of special function registers.
- When operands are in the access bank, no bank switching is needed.

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 The PIC18 Microcontroller

Examples of the Use of Access Bank

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1. addwf 0x20,F,A ; add the data register at 0x20 in access bank with WREG
; register and store the sum in 0x20.
2 subwf 0x30,F,BANKED
2. 0x30 F BANKED ; subtract the value of WREG from the data register
; 0x30 in the bank specified by the current contents
; of the BSR register. The difference is stored in
; data register 0x30.
33. addwf
dd f 0x40,W,A
0 40 W A ; add
dd the
h WREG register i with
i h data
d register
i at 0x40
0 40 in
i
; access bank and leaves the sum in WREG.

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 The PIC18 Microcontroller

PIC18 Addressing Modes

- Register direct: Use an 8-bit value to specify a data register.

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movwf 0x20,A ; the value 0x20 is register direct mode

- Immediate Mode : A value in the instruction to be used as an operand

addlw 0x10 ; add hex value 0x10 to WREG

movlw 0x30 ; load 0x30 into WREG

- Inherent Mode: an implied operand

andlw 0x3C ; the operand WREG is implied

daw ; the operand WREG is implied

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 The PIC18 Microcontroller

- Indirect Mode: A special function register (FSRx) is used as a pointer to

the actual data register.

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Format Example
INDFx x = 0,
0 1,
1 2 movwf INDF0
POSTINCx movff POSTINC0,PRODL
POSTDECx movf POSTDEC0,W
PREINCx addwf PREINC1,F
PLUSWx movff PLUSW2,PRODL

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 The PIC18 Microcontroller

PIC18 Instruction Examples

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Data Movement Instruction

lfsr FSR1,0xB00 ; place the value 0xB00 in FSR1

movf PRODL,W ; copy PRODL into WREG

movff 0x100,0x300 ; copy data register 0x100 to data register 0x300

movwf PRODL,A ; copy WREG to PRODL

swapf PRODL,F ; swap the upper and lower 4 bits of PRODL

movb 3 ; load 3 into BSR

movlw 0x10 ; WREG  0x10

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 The PIC18 Microcontroller

Add Instructions

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addwf 0x20,F,A ; add data register and WREG and place sum in WREG

addwfc
dd f PRODL W A
PRODL,W,A ; add
dd WREG,
WREG PRODL,
PRODL and
d carry and
d lleave sum
; in WREG

addlw 0x5 ; increment WREG byy 5

Subtract Instructions

subfwb PRODL F
PRODL,F ; PRODL  [WREG] – [PRODL] – borrow flag

subwf PRODH,W ; WREG  [PRODH] – [WREG]

subwfb 0x10,F,A ; 0x10  [0x10] – [WREG] – borrow flag

sublw 0x10 ; WREG  0x10 – [WREG]

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 The PIC18 Microcontroller

RISC CISC

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Simple instruction set Complex instruction set

R l andd fixed
Regular fi d instruction
i t ti format
f t Irregular instruction format

Simple address modes Complex address modes

Pipelined instruction execution May also pipeline instruction execution

Separated data and program memory Combined data and program memory

Most operations are register to register Most operations can be register to memory

Take shorter time to design and debug Take longer time to design and debug

Provide large number of CPU registers Provide smaller number of CPU registers

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