BATAAN PENINSULA STATE UNIVERSITY

COLLEGE OF ENGINEERING AND ARCHITECTURE Telefax: (6347) 2379214

(6347) 2379214
OFFICE OF THE DEAN Website: www.bpsu.edu.ph
Capitol Drive, Capitol Compound
City of Balanga 2100 Bataan
PHILIPPINES

Decade Counter

Performance Objectives
enough to enable the NAND gate and effect resetting as
shown by the spike on the timing diagram for FF2. This
A. Familiarize yourself with the operation of a
returns the count to zero where it starts all over again.
decade counter and develop a truth table.
Thus, there are 10 flip-flop states corresponding to binary
B. Demonstrate the operation of a decade
numbers 0 to 9 (hence, the name decade counter). In a
counter used as a frequency divider.
manner similar to a four bit binary counter, the decade
counter can also be used to divide the input clock
Basic Concepts
frequency by a factor of ten. This is shown by the timing
diagram of Fig. 32-1.
1. A decade counter produces a binary count of
0 to 9.
2. A decade counter can divide the input clock
frequency by a factor of 10.

Introductory Information

The decade counter is another of the many circuits used

to process and control digital data. This circuit is similar
to four bit binary counter studied in the previous
laboratory exercise except that two of the flip-flops are
gated to reset all the flip-flops on the tenth count. Refer to
Fig. 32-1. The decade counter operates as a straight
binary counter for clock pulses 1 through 9. Flip-flop FF1
sets and resets on the trailing edge of every clock pulse.
FF2 sets and resets on the trailing edge of every FF1
cycle. Similarly, FF3 sets and resets on the trailing edge
of every FF2 cycle. On the 8th clock pulse, FF4 is
triggered to the set stage by the trailing edge of FF3 cycle
as it would be for a binary counter.FF4 remains set
through the 9th clock pulse. During this time, it enables
one input of the two input NAND gate. The other input of
the NAND gate must be enabled by the set output of FF2.
This occurs on the 10th clock pulse when the FF2 is
triggered by the trailing edge of FF1 output. FF2 sets this
time, but by doing so it enables the other input to the
NAND gate. With both inputs at a logic 1, the NAND
output goes to logic 0, applying a clear signal to all four
flip-flops, resetting them to zero. FF2 is set only long

VISION MISSION

A leading university in the Philippines recognized for its proactive contribution To develop competitive graduates and empowered community
to Sustainable Development through equitable and inclusive programs and members by providing relevant, innovative and transformative
services by 2030 knowledge, research, extension and production programs and
services through progressive enhancement of its human
resource capabilities and instructional mechanisms
 BATAAN PENINSULA STATE UNIVERSITY
COLLEGE OF ENGINEERING AND ARCHITECTURE Telefax: (6347) 2379214
(6347) 2379214
OFFICE OF THE DEAN Website: www.bpsu.edu.ph
Capitol Drive, Capitol Compound
City of Balanga 2100 Bataan
PHILIPPINES

Equipment and Materials

1. a) Connect the circuit shown in Fig. 32-2.
Power Source 0-5 Vdc, 200mA Flip-flops FF1 through FF4 form the decade
Oscilloscope counter. The LED’s are used to read out the
Practical Electronics Trainer four bits of the decade count. Be sure the
S1 -PBNO, Component Module LEDs are connected to the flip-flops
S2 -Pushbutton, SPDT, Break- correctly so that they indicate an up-count
Before-make; Experiment from right to left. A logic 1 causes the LED
Board 6 to light and a logic 0 causes it to go out. The
FF1-FF4 -J-K Flip-flop, 7476; two cross-coupled NAND gates form a
Experiment Board 6 bistable flip-flop which will produce one
U1 - NAND IC, SN7400N; clock pulse each time S2 is depressed and
Experiment Board 6 released. Switch S1 is used to clear the flip-
U2 - IC Timing Circuit; flops manually. Clearing is also performed
Experiment Board 5 automatically by the NAND gate which
LED - Experiment Board 6 applies a logic 0 clear signal to all flip-flops
when FF2 and FF4 are both set on the count
Exercise Procedure of 10.
b) Adjust the power supply voltage to 5Vdc.
Objective A. Familiarize yourself with the Do not exceed 5Vdc.
operation of a decade counter and develop a truth c) Depress S1 momentarily. Are all the flip-
table. flops reset?

Fig. 32-2

VISION MISSION

A leading university in the Philippines recognized for its proactive contribution To develop competitive graduates and empowered community
to Sustainable Development through equitable and inclusive programs and members by providing relevant, innovative and transformative
services by 2030 knowledge, research, extension and production programs and
services through progressive enhancement of its human
resource capabilities and instructional mechanisms
 BATAAN PENINSULA STATE UNIVERSITY
COLLEGE OF ENGINEERING AND ARCHITECTURE Telefax: (6347) 2379214
(6347) 2379214
OFFICE OF THE DEAN Website: www.bpsu.edu.ph
Capitol Drive, Capitol Compound
City of Balanga 2100 Bataan
PHILIPPINES

Objective B. Demonstrate the operation of a

d) Record in Table 32-1 the logic states of the decade counter used as a frequency divider.
flip-flops in the clock pulse 0 row.
e) Depress and release S2 one time. Does the 2. a) Change your circuit to that shown in Fig.
LED monitoring FF1 light? 32-3. The IC timing circuit is used to supply
f) Record the results of (e) in Table 32-1. Be clock pulses to the decade counter.
sure to record the logic states of all flip-flops. b) Carefully adjust the power supply voltage
g) Continue applying clock pulses to the to 5Vdc.
decade counter one at a time and recording c) Measure the time period of the clock pulses
the binary count for each pulse. What at the clock input to FF1 using the
happens on the 10th pulse? oscilloscope.
h) Compare the results of Table 32-1 with the d) Now measure the time period at the set (Q)
truth table for the four bit binary counter of output of FF4.
the previous laboratory exercise. Are they e) Find the frequency of the clock pulses.
identical for the first nine pulses? f) Find the output frequency of FF4.
i) Explain how the NAND gate causes all the g) Compare the output frequency with the
flip-flops to reset on the 10th pulse. clock frequency. Is there a frequency division
j) Reduce the power supply voltage to zero. of 10?
h) Reduce the power supply voltage to 0.

BINARY NUMBER
BIT 4 BIT 3 BIT 2 BIT 1 CLOCK PULSE
(FF4) (FF3) (FF2) (FF1)

0
1
2
3
4
5
6
7
8
9
10
Table 32-1

VISION MISSION

A leading university in the Philippines recognized for its proactive contribution To develop competitive graduates and empowered community
to Sustainable Development through equitable and inclusive programs and members by providing relevant, innovative and transformative
services by 2030 knowledge, research, extension and production programs and
services through progressive enhancement of its human
resource capabilities and instructional mechanisms
 BATAAN PENINSULA STATE UNIVERSITY
COLLEGE OF ENGINEERING AND ARCHITECTURE Telefax: (6347) 2379214
(6347) 2379214
OFFICE OF THE DEAN Website: www.bpsu.edu.ph
Capitol Drive, Capitol Compound
City of Balanga 2100 Bataan
PHILIPPINES

Fig. 32-3

Quiz
Summary
1. The decade counter can generate a binary
In this laboratory exercise you demonstrated count equivalent to decimal digits:
the operation of a decade counter. You saw
that it consisted of four triggered flip-flops a. 0 through 4.
with two of the flip-flops gated to reset all b. 0 through 9.
four on the tenth clock pulse. By applying c. 0 through 10.
clock pulses to the first flip-flop, you saw that d. 0 through 15.
the counter counted up sequentially. You
used LED’s to monitor the set output of each 2. If the first two flip-flops in a decade counter
flipflop and found that a counter generated a are set, the binary number is:
four bit binary count that corresponded to the
numbers 0 through 9. You developed a truth a. 0011
table for the counter Then you demonstrated b. 1100
the operation of a decade counter as a c. 1001
frequency divider. You applied a source of d. 0110
continuous clock pulses to the first flip-flop.
By measuring the frequency of the input 3. In question 2, the decimal number would be:
clock pulses and the frequency in the output
of the last flip-flop you determined that there a. 3
was a frequency division of ten. b. 11
c. 2

VISION MISSION

A leading university in the Philippines recognized for its proactive contribution To develop competitive graduates and empowered community
to Sustainable Development through equitable and inclusive programs and members by providing relevant, innovative and transformative
services by 2030 knowledge, research, extension and production programs and
services through progressive enhancement of its human
resource capabilities and instructional mechanisms
 BATAAN PENINSULA STATE UNIVERSITY
d. 7 COLLEGE OF ENGINEERING AND ARCHITECTURE Telefax: (6347) 2379214
(6347) 2379214
OFFICE OF THE DEAN Website: www.bpsu.edu.ph
Capitol Drive, Capitol Compound
City of Balanga 2100 Bataan
PHILIPPINES

4. Given the binary count 1010, which flip-

flops in a decade counter will be set?

a. 2 and 3.
b. 2 and 4.
c. 1 and 3.
d. None.

5. In a decade counter used as frequency

divider the first three flip-flops produced a
frequency division of 2, 4 and 8. What
frequency division is performed at the
output of the fourth flipflop?

a. 2
b. 10
c. 16
d. 8

6. If the output frequency of a decade frequency

divider id 1kHz, what is the frequency of the clock
pulses?

a. 62.5 Hz
b. 10 kHz
c. 500 Hz
d. 100 Hz

VISION MISSION

A leading university in the Philippines recognized for its proactive contribution To develop competitive graduates and empowered community
to Sustainable Development through equitable and inclusive programs and members by providing relevant, innovative and transformative
services by 2030 knowledge, research, extension and production programs and
services through progressive enhancement of its human
resource capabilities and instructional mechanisms