Chapter 3:

1.Define: Encoder

Encoder is a combinational circuit which accepts N bit digital input and converts it
into an M bit another digital word.
2. Draw the MUX tree for 32:1 MUX using 4:1 MUX only
3. Minimize the following expression using K-map. f(A, B, C, D) = Σ m (0, 1, 2, 4, 5, 7, 8, 9, 10)

4. Draw the full adder circuit's logic diagram, truth table and K-map simplification.

A full adder is a computational logic circuit that performs addition between three
bits, the two input bits A and B, and carry Cin.
Full adder circuit's logic diagram: -

Full adder Truth table :

K- map simplification :-

5. Draw the binary to gray code converter with the help of truth table and its Kmap simplification

K - MAP for G3: -

G3=B3

K - MAP for G3: -

K MAP FOR G1: -

K MAP FOR G0: -

Diagram for Binary to Gray code converter:

6. Draw the 4-Bit adder circuit using IC 7483 and describe its working with suitable examples.

Working:
1. Inputs (A0 to A3 and B0 to B3):
• Connect the four input pins (A0 to A3 and B0 to B3) of the IC 7483
to the corresponding bits of the two 4-bit binary numbers you want to
add.
2. Outputs (S0 to S3 and C4):
• The four sum outputs (S0 to S3) represent the result of the addition of
the two input numbers.
• The carry out output (C4) indicates if there's a carry generated beyond
the 4-bit result.
3. Carry Propagation:
• The IC 7483 internally generates carries as needed while adding the
input bits.
• It performs full binary addition, taking into account the input bits and
any carry from the previous stage.
4. Example:
• Let's say we want to add two 4-bit binary numbers: A = 1010 and B
= 0111.
• Connect A0 to A3 with 1010 and B0 to B3 with 0111.
• The resulting sum (S0 to S3) would be 10001 (binary representation
of 17 in decimal).
• The carry out (C4) would be 1, indicating that there's a carry beyond
the 4-bit result
7. Draw logic diagram of half adder using K-map simplification and write truth table.
8. Draw 16: 1 mux tree using 4:1. Mux
Chapter 4:

1.Write the one application of SR-FF and mention its one drawback

Application of SR-FF:
1) It is used in memory storage devices to store data temporarily such as
registers and registers are used in counters, microprocessors and digital signal
processors.
Drawback of SR-FF:
1) When the inputs of SR-FF are S=0, R=0 or S=1, R=1, the outputs are either
invalid or do not change due to race condition.
2. Name four types of shift register.

Types of shift register:

1) Serial Input Serial Output (SISO)
2) Serial Input Parallel Output (SIPO)
3) Parallel Input Serial Output (PISO)
4) Parallel Input Parallel Output (PIPO)
3. Describe the working of clocked SR flip-flop with preset and clear.

Working of clocked SR flip-flop with preset and clear:

In the flip-flop when the power is switched ON, the state of the circuit is uncertain.
It may come to set (Q=1) or reset (Q=0) state.
In many applications it is desired to Initially set or reset the flip-flop l.e. the initial
state of the flip-flop is to be assigned. This is accomplished by using preset (Pr) and
clear (Cr) Inputs.
These inputs may be applied at any time between clock pulses and are not in
synchronism with the clock. An S-R flip-flop with preset and clear is shown in Fig.
If Pr = Cr = 1, then both the circuit operates in accordance with the truth table of S
R flip-flop given in table.
If Pr = 0 and Cr = 1, the output of G1 (Q) will certainly be 1.
Consequently, all the three inputs to G2 will be 1 which will make Q = 0. Hence
making Pr = 0 sets the flip-flop.
Similarly, if Pr = 1 and Cr = 0 then the flip-flop is reset.
The condition Pr = Cr = 0 must not be used, since this leads to an uncertain state.
Truth Table:
Table: Clocked SR flip-flop with preset and clear

4. Design 4-bit ripple counter and draw output waveform

Since it is 4 bit Ripple up counter , we need to use four Flip Flops .

Initially all the Flip Flops have Zero output QDQCQBQA = 0000
All the Flip Flops are negative edge triggered CLK is applied to the clock input of
FF-A .
Where as Q output of every Flip Flop is applied to the clock input of next Flip Flop.
Truth Table of 4 bit ripple counter:
5. Describe the working of J-K flip-flop and state the race around condition.
6. Describe the operation of R-S flip-flop using NAND gate.

Explanation: When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective of
the values of S and R. That means R’= S’ = 1.Hence the outputs of basic SR/F/F i.e. Q n+1 and will not
change. Thus if clock = 0, then there is no change in the output of the clocked SR flip-flop

Case : S = R = 0, clock = 1: No change If S=R=0 then outputs of NAND gate 3 and 4 are forced to
become 1. Hence R' and S' both will be equal to 1. Since R' and S' are the inputs of the basic S – R
flipflop using NAND gates. There will be no change in the state of outputs.

Case II: S =1, R = 0, clock = 1: Set Now S=0, R=1 and a positive going edge is applied to the clock
Output of NAND 3 i.e. R’ = 0 and output of NAND 4 i.e. S’ = 1. Hence output of SR flip-flop is Q n+1 =
1 and = 0. This is the set condition. Case III: S =0, R = 1, clock = 1: Reset Now S=0, R=1 and a positive
edge is applied to the clock input. Since S=0, output of NAND – 3 i.e. R´= 1. And as R’ = 1 and clock =
1 the output of NAND-4 i.e. S´ = 0. Hence output of SR flip-flop is Q n+1 = 0 and = 1. This is the reset
condition.

Case IV: S =1, R = 1, clock = 1: Undefined/ forbidden As S=1, R=1 and clock = 1, the outputs of NAND
gates 3 and 4 both are 0 i.e. S' = R'=0. So both the outputs Q n+1 = 1 and Hence output is Undefined/
forbidden.

7. Describe the operation of 4 bit serial in serial out shift register.

Diagram: (Use SR or JK or D type flip flop.) Note : Any other data input can be considered. Shift right
or left operation can be considered
Working: The DATA leaves the shift register one bit at a time in a serial pattern, hence the name
Serial-in to Serial-Out Shift Register or SISO. The SISO shift register is one of the simplest of the four
configurations as it has only three connections, the serial input (SI) which determines what enters
the left hand flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop
and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial- in
serial-out shift register, Output of FFA is Q4,FFB Q3,FFC Q2 and FFD is Q

8. Define counter.

Counter is a sequential circuit consisting of a set of flip-flops which can go through sequence of
states. It is used to count the number of clock cycles. Since the clock pulses occur at known intervals,
the counter can be used for measuring time such as period or frequency
Chapter 5:

1.List any two specifications/ features of IC 0809.

Specifications of IC 0809:
1) Input voltage range: 0 to 5 V
2) Power consumption: Less than 15 mW
3) Conversion time:100 µsec
4) Power Supply voltage: 5V
5) Resolution: 28

2. Calculate the analog output of 8 -Bit DAC for digital input 10011100. Assume Vfullscale =5V
3. Describe the working principle of dual slope type of ADC with neat diagram.

Working :
Above Fig. shows the functional block diagram of a Dual-Slope ADC. It consists of
four major blocks: 1. an integrator, 2. a comparator, 3. a binary counter and 4. a
switch driver, 5.T flip-flop.
This circuit is provided with a single-pole double throw electronic switch. The
initial state of the circuit is such that:
1. The output of the integrator is small and positive, so that the output of the
comparator is low. Thus, the AND gate is disabled.
2. The counter is kept reset, so that Y output of all flip-flops in the counter are
reading
3. The toggle mode flip-flop is kept reset.
The conversion process begins at t=0 with the switch S1 position 0 thereby
connecting the analog voltage Vx to the input of the integrator.
The integrator output is:

This results in high Vcr thus enabling the AND gate and the clock pulses reach the
clock (clk) Input terminal of the counter which was initially clear. The counter counts
from 00…. 00 to 11….. 111 when 2N-1 clock pulses are applied.
At the next clock pulse 2N, the counter is cleared and Q becomes 1. This controls the
state of S1 which now moves to position 1 at T1 thereby connecting -VR to the input
of the Integrator. The output of the Integrator now starts to move in the positive
direction. The counter continues to count until V0 < 0 As soon as V0 goes positive at
T2, Vc goes low enabling the AND gate. The counter will counting in the absence of
the clock pulses. The waveforms of voltages V0 and Vc are shown in below Fig

4. Compare weighted resister DAC with R-2R ladder type DAC.

6. List the types of semiconductor memories

1)Read & write memories or Random Access Memories (RWM or RAM)

2)Read only memory(ROM)

3)Programmable read only memory(PROM)

4)Erasable Programmable read only memory(EPROM) 5)Static Random Access Memories(SRAM)

6)Dynamic Random Access Memories(DRAM)

7. Give classification of memory and compare RAM and ROM. (Any four points)