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Assignment 2 (To Be Submitted On 28/3/2019 in The Class)

The document outlines 6 questions on cache memory and memory addressing for an assignment. It asks the student to: 1) Explain the fetch cycle using a data flow diagram and sequence of events. 2) Draw and explain the functioning of a microprogrammed control unit. 3) Explain write-through, write-back policies, hit/miss ratios, and replacement algorithms for cache. 4) Determine block, set, and field sizes for a 2-way set associative cache of 2048 words from a 128K word main memory.

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Lakshya
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30 views1 page

Assignment 2 (To Be Submitted On 28/3/2019 in The Class)

The document outlines 6 questions on cache memory and memory addressing for an assignment. It asks the student to: 1) Explain the fetch cycle using a data flow diagram and sequence of events. 2) Draw and explain the functioning of a microprogrammed control unit. 3) Explain write-through, write-back policies, hit/miss ratios, and replacement algorithms for cache. 4) Determine block, set, and field sizes for a 2-way set associative cache of 2048 words from a 128K word main memory.

Uploaded by

Lakshya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment 2

(To be submitted on 28/3/2019 in the class)

1. Write and explain micro operations for fetch cycle (instruction fetch) by making use of
data flow diagram and sequence of events

2. Explain the functioning of microprogrammed control unit with a neat figure

3. Explain clearly the following with respect to cache:


i) Write through and write back policy
ii) Hit, miss and hit ratio
iii) Why do you need replacement algorithm?

4. A two way set associative cache uses blocks of 4 words. The cache can accommodate a
total of 2048 words from main memory. The main memory size is 128K words.
Determine
i) No. of blocks in the main memory.
ii) No. of blocks and sets in the cache memory
iv) No. of bits in the word, set and tag field of the memory address format

5. Consider a main memory system with 26- bit address, and a cache with 18- bit address that
uses a 32 byte block size. The memory is byte addressable and assume direct mapping.
Determine

i) main memory and cache memory size


ii) number of blocks in the main memory
iii) number of blocks in the cache
Also show the main memory address format.

6. Consider a virtual address space of 16 megabytes. The main memory space is specified by
20 bits. If the page no. field of the virtual address is 10 bits, find the following:
(i) No. of bits needed to specify the virtual address space
(ii) Size of the main memory
(iii) No. of pages
(iv) Size of a page
(v) No. of blocks

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