COA Endsem Questions

1. A two byte relative mode branch instruction is stored in memory location 1000. The branch
is made to the location 87. What is the effective address?
2. A 2 byte long assembly language instruction BR 09 (branch instruction) stored at location
1000 (all no. are in HEX). What is the effective address that the PC holds?
3. In the case of, Zero-address instruction method where the operands are stored? Which
addressing mode/s, uses the PC instead of a general purpose register?
4. What is the hexadecimal equivalent of the binary number 11010011001010100?
5. What is the Octal number conversion of this hexadecimal number (FAFAFA)16 ?
6. What are addressing modes? Write down the names of 5 addressing modes.
7. Convert the following decimal no.s into Hexadecimal no.s. a) 70 b) 130 c) 1348
8. Convert the hexadecimal no.s into Decimal no.s. a) 7A b) 1F c) 13C
9. State the name of the bit is used to signify that the cache location has been updated, during
write-back policy.
10. State what is the minimum time delay between two successive memory read operations
called.
11. State for which cache mapping technique, any memory blocks are mapped to any of the
cache lines.
12. “Associative mapping is costlier than direct mapping.” Justify the validity of the statement
with a one-line reason.
13. “Principle of Inclusion does not hold true if a lower level of cache is split cache, while a
higher level of cache is unified cache.”. Justify the validity of the statement with a one-line
reason.
14. In the context of logical and physical memory addresses, which register maps the logical
addresses generated by the CPU into physical memory addresses ?
15. “The miss penalty can be reduced by improving the mechanisms for data transfer between
the different levels of hierarchy.” Justify the validity of the statement with a one-line reason.
16. While using the direct mapping technique for a system with a 16-bit address, the tag part of
the address is given as least significant bits. State the validity of this statement.
17. If each register is specified by 3 bits and instruction ADD R1, R2, R3 is 2 byte long. Then
what is the length of the op-code field?
18. What is the max number of 0-address, 1-address and 2 –address instructions if the
instruction size is 32 bits and 10 bit is used for an address field?
19. What value remains on the stack after the following sequence of the instruction?
PUSH #3
PUSH #5
PUSH #4
ADD
PUSH #7
SUB
MULT
20. There are 58 processor registers, 7 addressing modes and 16K X 32 main memory. State the
instruction format and the size of each field if each instruction supports one register
operand and one address operand.
21. There are 54 processor registers, 5 addressing modes and 8K X 32 main memory. State the
instruction format and the size of each field if each instruction supports one register
operand and one address operand.
22. Suppose the processor takes 7 ns to read an instruction from memory, 3ns to decode the
instruction, 5ns to read operands from register files, 2ns to perform the computation of the
instruction and 4 ns to write the result into the register. What is the maximum clock rate of
the processor?
23. A computer has 32- bit instructions and 12 bit addresses. If there are 250 two address
instructions how many one address instructions can be formulated?
24. A computer has 64 bit instructions and a 12 bit address. If there are 250 three address
instructions and 525 two address instructions, how many one address instructions can be
possible?
25. Assuming that all registers initially contain 0, what is the value of R1 after the following
instruction sequence is executed?
MOV R1, #6
MOV R2, # 5
ADD R3 , R1, R1
SUB R1, R3, R2
MULT R3, R1, R1
26. Consider a cache of size 32 KB with line size 1024 bytes. The size of the memory is 1 MB. a.
For direct-mapped cache, in which lines will memory block numbers 24 and 240 be placed
respectively? b. For 2-way set-associative cache, in which lines will memory block numbers
24 and 240 be placed respectively?
27. “While principle of inclusion and principles of coherence both are associated with
hierarchical layering of memory modules, they are in no way the same principle.”. Is this
statement True or False? Justify your answer with a proper diagrammatic explanation.
28. A cache memory unit with a capacity of 16 KB is built using a block size of 16 words. The size
of the memory is 8 GB. Assume & find the following: a. If the word length is 8 bits and the
mapping is 4-way set associative, what is the memory address in terms of bits? Also, depict
the various fields of the memory address. b. If the word length is 8 bits and the mapping is
direct-mapped, what is the memory address in terms of bits? Also, depict the various fields
of the memory address.
29. Elucidate on the similarities and difference between RAM & ROM designs using relevant
block diagrams.
30. “Approximate time required to find a specific word is more for direct-mapped cache
memory than k-way set associative cache memory”. Is this statement True or False? Justify
your answer with relevant examples.
31. Elucidate on the principle of locality of reference and its various types using relevant
examples.
32. A computer has a 256 KB, 4-way set associative, write back data cache with block size of 32
bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag
directory entry contains in addition to address tag, 2 valid bits, 1 modified bit and 1
replacement bit. Find the following: a. Number of sets b. Size of tag field c. Size of the tag
directory
33. Evaluate the following arithmetic expression using 0,1,2,3 address instruction:- X= (A+B) /
(C*D)
34. An instruction is stored at location 300 with its address field at 301. The address field has
400 values. A processor register R1 contains the number 200. Evaluate the effective address
if the addressing mode of the instruction is: a) Direct b) Immediate c) Relative d) Register
indirect e) Index with R1 as the index register.
35. Find out the effective address and content of the AC in each of the following cases(content
of PC=1500, content of IR=2,AC=0) Address Memory Content 1500 ADD 1504 1502 50 1504
1508 1506 20 1508 40
1. Direct addressing mode
2. Indirect addressing mode
3. Indexed addressing mode
4. Immediate addressing mode
36. Evaluate the following arithmetic expression using 0,1,2,3 address instructions and identify
the address instruction scheme where the minimum number of LOAD instruction is used. X=
(A+B) – (C+D)
37. Using relevant flowchart and diagram, explain the “Read Cycle” for cache memory
management
38. "Cache write miss policies will employ an extra write policy to resolve the write." Is this
statement true for both "Write-Allocation" and "Write-Around" policies. Justify your
reasoning with an elaborate diagram and explanation.
39. Using relevant flowchart and diagram, elaborate on the cache write cycle with “Write Back”
policy for cache memory management. Is this policy applicable during cache hit or cache
miss?
40. “1-way Set Associative mapping and Direct Mapping are the same”. Is this statement true or
false? Justify the validity of your answer through a brief comparative elaboration of both
mapping techniques.
41. A block-set associative cache memory consists of 128 blocks divided into four block sets .
The main memory consists of 16,384 blocks and each block contains 256 eight bit words. 1.
How many bits are required for addressing the main memory? 2. How many bits are needed
to represent the TAG, SET and WORD fields?
42. Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main
memory is 128 KB. Find 1. Number of bits in tag 2. Tag directory size
43. Explain the working of a 16-megabyte DRAM chip configured as a 1M x 6 memory chip.
44. How many bits would you need to address a memory with 2M 4-byte words if the memory is
byte addressable?
45. How many bits would you need to address a memory with 1024x32 if the memory is word-
addressable?
46. In a 8085 microprocessor based system uses a 4 K x 8 bit RAM whose starting address is
AA00. What is the address of the last byte in this RAM ?
47. To design a 512 * 8 RAM chip by using 128*8 RAM chips what will be the size of the decoder?
48. A computer uses RAM chips of 1024*1 capacity. How many chips are needed to provide a
memory capacity of 16 K bytes?
49. How many address lines is needed for the processor to access 4MB memory?
50. Why is the memory system of a computer organized as a hierarchy?
51. Suppose you are given RAM chips each of size 128x1. Design a 128x8 RAM system using
these chips as the building block. Draw a neat logic diagram of your implementation.
52. Main memory address is 16 bits, no of cache blocks 1024 and block size is 16 words. In
direct mapping technique, find the no of bits required for tag,cache index and word offset
field.
53. Suppose you are given RAM chips each of size 256 x 4. Design a 2 K x 8 RAM system using
these chips as the building block. Draw a neat logic diagram of your implementation.
54. A computer has a main memory of 64 Kx16 and a cache memory of 1 K words. The cache
uses direct mapping with a block size of 4 words. a) Find the no of bits required for word
offset, cache index and tag? b) How many bits are there in each word of the cache? c) How
many blocks can the cache accommodate?
55. Write down the effective addressing mode instruction, MOV 5(R1), LOC.
56. What is the function of the program counter?
57. Explain logical and arithmetic shift instructions with an example.
58. Explain Implied addressing mode with an example?
59. Write the addressing mode of this instruction AC AC + [[R]].
60. In implementing cache memory what are the disadvantages of the direct mapped cache
and the associative cache. How is it overcome in the set associative cache?
61. What is Operation Code (Opcode)?
62. Write down the operation of the control unit?
63. Write the difference between Primary storage and secondary storage.
64. What do you mean by cache coherence? Explain with a diagram.
65. Write a short note on the memory address map.
66. What is a Bus? Write down the types of buses.
67. Convert 10110.001 this number to its decimal value.
68. Discuss different types of registers and its use in computer systems.
69. Describe the functions of major components of a digital computer with a block diagram.
70. Discuss about different types of addressing modes.
71. Explain the basic components of a computer with a neat diagram.
72. How do different registers transfer data with the help of a common bus?
73. A system has a main memory with 16 MB of addressable locations and a 32 KB of direct-
mapped cache with 8 bytes per block. The minimum addressable unit is 1 byte. Find out
how many blocks are in cache and what is the address breakdown for main memory?
74. State the difference between computer organization and architecture.
75. Mention what are the different types of field that are part of an instruction.
76. What do you mean by LOAD and STORE instructions?
77. What is MAR and MDR?
78. What is Three address, Two address, One Address, Zero address instruction? Give examples
for each.
79. Write down the addressing modes that are suitable for program relocation at run time?
80. How many bytes are there in one terabytes.
81. Write down the memory which comes under the primary memory (also called main
memory).
82. Name the memory acts as a buffer between main memory and processor.
83. Write down the property on which the effectiveness of the cache memory is based.
84. Draw a block diagram for 8M X 32 memory using 512 K X 8 memory chips.
85. Explain associative cache mapping with a neat diagram.
86. What is the easiest way to determine cache locations in which to store memory blocks?
Explain with a neat diagram.
87. What is the use of a temporary register (TR).
88. Convert the following instruction into one, two and three address instruction: (A+B*C)/(D –
E*F +G*H)
89. There are 50 registers and a total 55 instructions available in a general purpose computer.
The computer allows only 2-address instructions, where one operand can be a register and
another can be memory location. The memory is byte addressable with 64KB in size. What is
the minimum number of bits to encode the instruction ?
90. Which locality means that the next block of data will be accessed from the adjacent location
in relation to the current block being accessed?
91. Give the example of the smallest entity of memory. The Boot sector files of the system are
stored in which computer memory?
92. Which memory has the fastest speed in the computer memory hierarchy?
93. Which computer memory chip allows simultaneous both read and write operations?
94. What do you mean by stalling in pipelining? Give the example.
95. What do you mean by structural Hazards? Give Example.
96. Define throughput. What is the unit of throughput?
97. What are the four parameters of the pipeline? Name them.
98. What is forbidden latency? Give example.
99. How many Data Hazards are possible? Name them.Which Data Hazard is not possible?
100. Draw the typical ALU design.
101. Multiply the 7*3 using a sequential method for unsigned multiplication.
102. Write down the algorithm for restoring division with an example
103. Explain about the signed and unsigned numbers representation in binary
104. Write the IEEE 754 format for representing floating point numbers in single precision and
double precision format. Represent the decimal number 10.25, using IEEE 754 single
precision floating point format
105. Find 5 divided by 3 using Non-Restoring Division Algorithm
106. Write the 2’s complement of 1011011.
107. How are floating point numbers represented in computer system?
108. What is the advantage of non restoring over restoring division?
109. Perform the arithmetic operation in binary using 2’s complement representation (i) (+42)
+ (-13) (ii) (-42) – (-13).
110. Consider a 4 stage pipeline processor. The number of cycles needed by the four
instructions I1, I2, I3 and I4 in stages S1, S2, S3 and S4 is shown below
111. What is the number of cycles needed to execute the following loop?
for ( i=1 to 2 ) {

I1;

I2;

I3;

I4; }

112. Suppose the time delay of the four stages of a pipeline are 1=60ns, 2=70 ns, 3=90ns and
4=80 ns respectively and the interface latch has a delay d= 10ns. Then i) What would be
the clock frequency of the above pipeline? ii) What is the speed up of the pipeline over its
equivalent non-pipeline Counterpart?
113. Identify all of the RAW, WAR and WAW hazards in the instruction sequence:

DIV R1, R2, R3

SUB R4, R1, R5

ASH R2, R6, R7

MULT R8, R4, R2

BEQ R9, #0, R10

OR R3, R11, R1

114. Explain Control Hazards with example.Consider the

following reservation table and find i) Final state
diagram ii) list all the simple cycles and greedy cycles.
115. Instruction execution in a processor is divided into 5
stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX),
 and Write Back(WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A
pipelined implementation of the processor requires buffering between each pair of
consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor
are contemplated:

(i) a naive pipeline implementation (NP) with 5 stages and

(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and
OF2 with execution times of 12 ns and 8 ns respectively.

116. The speedup (correct to two decimals places) achieved by EP over NP in executing 20
independent instructions with no hazards is ?

117. Consider the reservation table: a. Write down the forbidden latencies and initial collision
vector b. Draw the state transition diagram for scheduling the pipeline.

118. Consider the execution of a program of 20,000 instructions by a linear pipeline processor
with a clock rate 40MHZ. Assume that the instruction pipeline has five stages and that
one instruction is issued per clock cycle. The penalties due to branch instructions and
out-of-order executions are ignored. Calculate the speed up of the pipeline over its
equivalent non pipeline processor, the efficiency and throughput.
119. The stage delays in a 4 stage pipeline are 800, 500, 400 and 300 picoseconds. The first
stage is replaced with a functionally equivalent design involving two stages with
respective delays 600 and 350 picoseconds.How much the throughput will increase (in
percentage) ?
120. Which hazard occurs if the read takes place before the write operation is complete and
why?
121. When does the performance of a pipeline processor suffer?
122. How does pipeline improve CPU performance?
123. Reduced instruction set computer is based on which architecture?
124. If the greedy cycles are (3),(7) and (1,8) What will be the Minimum average latency?

125.

126. (a)List the set of forbidden latencies and collision vector. (b) Draw the state transition
diagram. (c) List all simple cycles from the state diagram. (d) Identify the simple cycles
among greedy cycles.

127. Is a greedy cycle a simple cycle? Justify your answer

128. Convert -32.75 to IEEE 754 single precision floating point and convert this in
hexadecimal number
129. What is the range for numbers using n bit register in signed magnitude? For double
precision floating point number draw the representation of the format
130. Convert the number -0.75 into IEEE 754 single precision format.
131. Assume a 4 segment pipeline system with a clock cycle of 20 nano seconds required in
each segment to execute 100 tasks in sequence. What is the speedup ratio?
132. Consider the following instructions

I1: R1=100

I2: R1=R2+4

I3: R2=R4+25

I4: R4=R1+R3

I5: R1=R1+30

Calculate sum of (WAR,RAW and WAW) dependencies for the above instructions.
133. Consider the following procedures. Assume that the pipeline registers have zero latency.
P1 : 4 stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns
P2 : 4 stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns,
1.5 ns P3 : 5 stage pipeline with stage latencies 0.5 ns, 1 ns, 1
ns, 0.6 ns, 1 ns P4 : 5 stage pipeline with stage latencies 0.5 ns,
0.5 ns, 1 ns, 1 ns, 1.1 ns Which procedure has the highest
peak clock frequency?
134. Consider the reservation table and find the followings: (i) What are the forbidden
latencies? (ii)Draw the state transition diagram. (iii) List all simple cycles and greedy
cycles. (iv) Determine minimum average latency.
135. Explain with example how different types of data hazards can take place in pipelining.
136. A four stage pipeline has the stage delays as 150, 120, 160 and 140 ns respectively.
Registers are used between the stages and have a delay of 5 ns each. Assuming constant
clocking rate, find out the total time taken to process 1000 tasks on both the pipeline and
non-pipeline systems. Determine the speed up ratio
137. Illustrate with diagram the working principles SIMD and MISD computers.
138. How is a multiprocessor is different from a multicomputer?
139. Why does control hazard take place in pipelining?
140. Why do we need to align mantissas in arithmetic pipelining?
141. For a six stage pipeline, how many cycles the initial instruction would require for
execution?
142. Using 5-bit registers, perform the following operations and check whether overflow
occurs or not . a) (+7)+(-6) b) (+7)+(+9)
143. Give the decoded Booth’s multiplier representation for the following. a) 1100 1010, b)
1110 1101
144. How many basic gates are used to design 8-bit Carry propagation adder?
145. If q is the length of divisor then what is the minimum number of restoring operations
used to perform restoring division algorithm?
146. What are the advantages of 2's complement representation over 1's complement
representation?
147. Find out the corresponding decimal numbers for the binary number 111100011
considering (i) Signed magnitude, (ii) 1's complement and (iii) 2's complement
representations respectively
148. a) Which is the best multiplier based on Booth’s algorithm among 11111, 101010,
01010101, 110001? b) Which is the worst multiplier based on Booth’s algorithm among
11111, 101010, 01010101, 110001?
149. Design 4-bit circuit which can perform addition as well as subtraction based on the
control input.
150. “Overflow can be detected by Cn-1 xor Cn where Cn-1 and Cn are the carry input and
carry output respectively for n-bit signed numbers” - Justify the statement.
151. How many AND, OR and XOR gates are used to design n-bit Carry propagation adder?
152. Perform A-B where A = 111001 and B = 101011 where A and B are signed numbers.
153. Define carry propagation delay.
154. Write Fixed point representation of a number -43.625. Assume number is using 32-bit
format which reserve 1 bit for the sign, 15 bits for the integer part and 16 bits for the
fractional part.
155. Convert 418 to a binary number
156. Convert 96010 into hexadecimal number.
157. What is binary underflow?
158. Implement carry generator circuit for 4 bit carry look ahead adder.
159. Write floating-point representation of a number -53.5. Suppose number is using 32-bit
format: the 1 bit sign bit, 8 bits for signed exponent, and 23 bits for the fractional part.
The leading bit 1 is not stored (as it is always 1 for a normalized number) and is referred
to as a “hidden bit”.
160. A 16-bit ripple carry adder is realized using 16 identical full adders. The carry
propagation delay of each full adder is 12 ns and the sum propagation delay of each full
adder is 15 ns. What is the worst case delay of this 16 bit adder?
161. Explain Booth's algorithm using an example and draw the flowchart.
162. Draw the logic diagram for 4-bit Ripple Carry Adder and design its sum and carry
expression for each bit. Write the disadvantages of Ripple Carry Adder.
163. What is cache coherence in a multiprocessor system?
164. What are the advantages of distributed shared memory architecture over centralized
shared memory architecture?
165. What is the difference between loosely coupled architecture and tightly coupled
architecture?
166. What is the difference between SIMD architecture and MIMD architecture?
167. Explain Flynn's classification with proper diagrams
168. Design an interconnection network for a distributed system where the number of nodes
is 8.
169. What do you mean by parallel processing?
170. Write down the equation of speed gained by 'n' segment pipeline executing 'm' task.
171. How can we increase the speed of memory access in pipelining
172. What steps need to be taken when a hazard occurs?
173. What will be the equation if we considering equal processing time for each segment,
speed up 'S' achieved by a 'K' segment instruction pipeline operating on straight
sequence of 'N' instruction.
174. What is the importance of IEEE-754 standard?
175. Represent -38 in 2’s complement form.
176. a) What is difference between ripple carry adder and carry look ahead adder? b) Why
look ahead carry adder is faster than ripple adder?
177. a) For each of the following n-bit binary numbers, show the value, in base 10, if the
number is considered unsigned or signed (2’s complement). i. 110110 unsigned value:
signed value: ii. 1000 unsigned value: signed value: b) Name the three component parts
of a floating point number. Why do we use bias in floating-point representation?
178. Explain unsigned multiplication using hardware design with diagram.
179. Find out the difference between Booth's Algorithm and unsigned multiplication.
180. Comparison between restoring and non restoring division algorithm with example
181. What will be the speedup for a 4 segment linear pipeline when the number of instructions
n=64?
182. Design n-bit Carry look-ahead adder (CLA) using 4-bit carry look ahead adders where
sum and carryout for every bit is evaluated as follows respectively: Si = Ai (+) Bi (+) Ci and
Ci+1 = ((Ai (+) Bi).Ci)+(Ai.Bi) 0<=i<=n-1. Let us consider AND, OR and NOT gates take 1
unit time period. Find out T(Cn).
183. Perform (+35)*(-5) using minimum length registers [the operands should be represented
in 2's complement format].
184. Design n-bit optimal carry propagation adder using 2-input logic gates.
185. Find out the differences between (i) program counter and memory address register, (ii)
1's complement representation and 2's complement representation and (iii) instruction
register and memory data register.