High Speed & Low Power Comparator using

Double-Gate MOSFET Scalable to 20nm

Lijesh L¹, Supriya Sara Mathew²
¹Associate Professor, Department of ECE, Musaliar College of Engineering and Technology, Pathanamthitta, Kerala
²PG Scholar, Department of ECE, Musaliar College of Engineering and Technology, Pathanamthitta, Kerala
Abstract— Power consumption is a major problem in all signal is compared with these generated reference voltages
electronic circuits. In order to achieve the power consumption, using the comparator array and the corresponding
circuit scaling is important. In CMOS based circuits scaling thermometer code will be generated [6]. These thermometer
should be possible up to constrained range after that it will codes are given to the advanced encoder which will change
present short channel impacts. To defeat above disadvantage over them to the relating binary codes.
FINFET has been presented. Comparator is one of the
components most importantly required in analog to digital
converter. Op-Amps are the major constituent of analog and
mixed-signal systems. Speed interest for rapid applications, for
example, ADC and DAC lead to expanded interest for
amplifiers with high gain and speed. FinFET is a standout
amongst the most encouraging advancements to structure
underneath 50nm. FinFET transistors in simple circuit
configuration presents noteworthy enhancement contrasted
with conventional one entryway CMOS structure. In this
paper, we present a FINFET based comparators for high speed
Flash ADC. The main parameters considered in the
performance analysis are delay, frequency and power
consumption. LT-Spice simulation software is used for design
and analysis of the comparator circuits in the above specified
32nm scaling range.
Fig.1. Block Diagram of 3-Bit Flash ADC
Keywords—Flash ADC, FinFET, Comparator, Low Power

I. INTRODUCTION III. FINFET TECHNOLOGY

Multi-gate FETs are an option in contrast to planar
Analog-to-digital converters are used to convert real
MOSFETs, which enhanced the drain potential screening out
world analog signals into digital representations of those of the channel because of quality of extra gates. In all multi-
signals. As we know that the digital signal processing can gate devices, the two gate FETs or tri-gate FETs are
then efficiently extract information from the signals. ADCs increasingly attractive because of littler parasitic
find use in communications, audio, sensors, video and many capacitances and hearty conduct against irregular dopant
other applications [1]. High-speed, low-resolution ADCs are conduct. The Trigate FETs are having decreased fringing
used in oscilloscopes, digital high-speed wire line and capacitances yet at the expense of complex creation process.
wireless communications and radar. Flash and time- The FinFETs are the rising gadgets in this mechanical time
interleaved ADCs architectures are typically used for high- which are having negligible power utilization, insusceptible
speed applications. There are various types ADC to short channel effects, littler area necessity and higher
architecture in which first is pipeline ADC [2]. Its operating speed of activity [7].
speed is high but below flash with medium resolution.
The FinFETs are grouped in fundamental two classes: (a)
Second ADC architecture is SAR ADC [3]. It is appropriate Independent Gate FinFET (IGF) (b) Short Gate FinFET
for low power and medium-to-high goals applications with (SGF). IG FinFETs are having four terminals while SGF are
moderate speed. Third ADC design is Sigma-delta ADC [4]. otherwise called three terminal FinFETs. The entryways are
It is reasonable for high goals and low speed applications. disconnected in IGF structures while the front and the back
Forth ADC architecture is Flash ADC [5]. It can work at fast doors are shorted to one another in SGF structures as
and low goals. So we can say that Flash ADC is the quickest appeared in Fig.2. SGF structures are having higher ON
ADC in correlation with other ADC models. The flash ADC current when contrasted with IGF structure on the grounds
is the best choice in high speed low resolution applications. that SGF structure mutually utilizes both the entryways for
It is highly used in high data rate links, high speed electrostatic control of the channel. Be that as it may, an IGF
instrumentation, radar, digital oscilloscopes and optical structure offers the adaptability to apply distinctive signals
communications. Since flash ADC is working in parallel on the diverse gates however at the expense of bigger chip
change technique, most extreme working recurrence in the territory.
scope of gigahertz is conceivable. Comparator design is also
a challenge for design of Flash ADCs.
II. FLASH ADC
The General block diagram for a 3 bit Flash ADC is given
in below Fig.1. A Flash ADC is framed of mostly three
blocks- Resistor ladder, Comparator array and Thermometer
to Binary code encoder. Resistor ladder is utilized for
producing different reference voltages. The incoming analog Fig.2. Comparison between SGF and IGF
 IV. COMPARATOR This operation amp is so much utilized that is called
Block diagram of an amplifier with a differential input conventional two phase operation amp. Capacitor CC is
utilized for Miller pay to expand the phase margin.
and a single-ended output is shown in Fig.3.
B. Proposed Two Stage Op-Amp
Here, another two-stage single-ended differential
amplifier with FinFET innovation is presented. The past
circuit executed with MOSFET is supplanted by FinFET
transistors [10]. Fig.5 demonstrates the general structure of
the amplifier utilized for planning.

Fig.3. Block Diagram of Two-Stage Op-Amp

Two-stage amplifier is made of four principle parts. This

include a differential amplifier in the input, second gain
circuit, bias circuit and compensation circuit [8]. Given that
the circuit load is capacitive, the buffer stage isn't required in
the enhancer. Differential amplifier at the input obtains a
larger share of the total amplifier gain to improve noise
performance and offset. To have most extreme swing in the
yield, the second stage is generally utilized as a
straightforward common source. Compensation circuit is
additionally used to balance out and the inclination circuit
has the errand of giving the predisposition voltages of the
amplifier circuit.

A. Conventional Two Stage Op-Amp

A customary two phase operational amplifier with
compensation capacitor Cc is exhibited in Fig.4. The
amplifier incorporates the course phases of voltage to current
and current to voltage converters. The primary stage
comprises of a differential amplifier that changes over the
differential information voltages to differential currents. The Fig.5. Proposed Two-Stage FinFET Op-Amp
differential currents are connected to the present current
All transistors are FinFET and as appeared in the figure
mirror stack that recovers the differential voltage. This is
the second gate of every n-FinFET transistors are associated
obviously only a differential voltage amplifier. The second
with GND and the back door of p-FinFET transistors is
stage incorporates a MOSFET regular source that changes
associated with Vdd. Here M1, M2, M3, M4 and M5 frame
over the input voltage of the second stage to the current [9].
the main phase of amplifier. M1 and M2 is differential pair
and M3 and M4 are utilized as the load for the differential
combine transistors. M6 and M7 together assume the job of
common source and frame the second phase of amplifier. M5
assumes the job of current source to the amplifier. M8
together with Ibias assumes the job of bias circuit for the
amplifier. Cc is utilized for Miller pay in the amplifier
structure.
The amplifier open loop gain can be communicated as
the increase of two phases:
𝐴𝑣=(2∗𝑔𝑚2∗ 𝑔𝑚6)/(𝐼5∗𝐼6∗(𝛌𝟐+ 𝛌 3)∗(𝛌 6+𝛌 7)) (1)
Along these lines, the gain depends to transconductance
gm and the channel length modulation parameter λ. FinFET
compelling portability is higher than mass transistors due to
non-doping channels and subsequently builds gm. Channel
length modulation parameter (λ) in FinFET is impressively
limited because of better control of short channel impacts in
double gate structure. Thus, the gain can be expanded by
Fig.4. Conventional Two-Stage CMOS Op-Amp FinFET.
 V. RESULTS AND SIMULATION D. Power Analysis of Two Stage CMOS Op-Amp

A. Schematic of Two Stage CMOS Op-Amp

Fclk = 1/T = 1/0.3 sec = 3.33 Hz

Dynamic Power Dissipation = Fclk * Vdd² * CL
= 3.33 * 1.8² * 100pF = 1.08 nW
Static Power Dissipation = 1.1952 µW
B. Transient Analysis of Two Stage CMOS Op-Amp
E. Propagation Delay of Two Stage CMOS Op-Amp

C. ACAnalysis of Two Stage CMOS Op-Amp

F. Schematic of Two Stage FinFET Op-Amp I. Power Analysis of Two Stage FinFET Op-Amp

Fclk = 1/T = 1/0.3 sec = 3.33 Hz

Dynamic Power Dissipation = Fclk * Vdd² * CL
= 3.33 * 0.8² * 30pF = 0.6393 pW
Static Power Dissipation = 0.268 µW
G. Transient Analysis of Two Stage FinFET Op-Amp
J. Propagation Delay of Two Stage FinFET Op-Amp

H. ACAnalysis of Two Stage FinFET Op-Amp

 TABLE I. COMPARISON BETWEEN CMOS COMPARATOR transfer speeds that are utilized at present for SoC
AND FINFET COMPARATOR
applications require low power ADCs with programmable
reference voltage for simple to advanced transformation. The
speed of a Flash ADC relies upon the speed of the
comparators. FinFET based comparators turned out to be of
low power dispersal and engendering delay than MOSFET
based comparators.

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