Design of a Fully-Differential Double Folded Cascode

Class AB Opamp with Continuous Time Common Mode

Feedback Network for 12-bit Pipeline ADC Applications

Lida Kouhalvandi1, Sercan Aygün1,2, Ece Olcay Güneú1, Mürvet KÕrcÕ1

1
Department of Electronics and Communication Engineering, østanbul Technical University, Maslak, østanbul, Turkey
2
Department of Computer Engineering, YÕldÕz Technical University, Davutpaúa, østanbul, Turkey
kouhalvandi@itu.edu.tr, ayguns@itu.edu.tr, ece.gunes@itu.edu.tr, ucerm@itu.edu.tr

Abstract—This paper deals with a fully differential (FD) Therefore, decreasing the total power dissipation could yield
operational amplifier (opamp) consists of double folded cascode significant power saving [4]. Accuracy and power supply noise
and class AB output with continuous time common mode are two important advantages that fully-differential amplifiers
feedback (CMFB) network. The opamp is designed in 0.18 —m have. In order to obtain higher DC gain, analog designers tend
CMOS technology in Cadence Spectre Circuit Simulator with to design multi-stage topologies and these techniques depend
1.8 V supply. In this single supply, opamp has 117 dB gain, 65- on using cascode structures. In other words, keeping a high DC
degree phase margin, 72 dB common-mode rejection ratio gain, which leads to use multi-stage amplifiers, is done by
(CMRR) for 2pF load with a power consumption of only 1.2 mW. applying cascode technique. Recently, in low power voltage,
This topology is more suitable for high-speed pipeline Analog-to-
class AB output stage is used increasingly when high
Digital converters (ADCs) with foreground calibration, when
efficiency is becoming significant in analog designs, and it has
compared to conventional designs, enabling operation at higher
clock frequencies as the class AB stage causes the slew limiting in high output impedance.
the first stage and power dissipation is decreasing. Our proposed design is based on a fully differential
opamp includes a double folded cascode and class AB output
Keywords—fully differential amplifier; common mode feedback stage with continuous time common mode feedback network
(CMFB); analog-to-digital converter (ADC); class AB; double which is appropriate for driving 12-bit pipeline ADC with
folded cascode.
foreground calibration. The conceptual difference between
double and single processing is that, it requires extra feedback
I. INTRODUCTION to control the output common-mode component in fully
Designing analog-to-digital converters (ADCs) with high- differential amplifiers. This design provides a much smaller
speed (100-300 MS/s), high resolution (10 to 16 bits) and also load capacitance to the output of the amplifier that leads
low power have become important issues to be considered. The higher speed and larger slew rate.
pipeline ADC architectures are used many applications and The organization of this paper is as follows: Section II
they are well-suited for designs in terms of accuracy. The speed describes the proposed opamp, while Section III reports the
of pipeline ADC is close to flash ADC. Additionally, as the simulation results which are achieved in 0.18 —m CMOS
resolution of a pipeline ADC is higher than a flash ADC, it can technology and also comparison with previous works given.
be implemented in wireless communication systems. Speed and The appropriate analysis for testing opamp is explained in
accuracy are two important properties of ADCs, can be Section IV. Suitable opamp application and conclusions are
determined by settling behavior of operational amplifiers, as drawn in Section V and VI respectively.
opamps are integral parts and basic building blocks used in
most analog circuits [1]. Settling speed depends on not only a
single pole settling but also on unity-gain frequency. The II. AMPLIFIER DESCRIPTION
architecture of suitable opamp can be determined regarding the A fully differential amplifier (FDA) has a wide range of
application of it in electronic devices. As integrated circuit (IC) usage because of its innate immunity to common mode signals
technologies are remarkably increasing, high-performance and clock feed through. It is a DC-coupled high gain
opamps are used in ADCs significantly [2]. To fulfill the electronic voltage amplifier both with differential inputs and
required settling-time with minimum current consumption, [3] outputs. FDAs are used to convert an analog signal to digital
proposed an ADC which is based on the recycling folded- signal and is suitable for driving high-precision ADCs that
cascode amplifier with added gain-boosting. ADCs can limit mostly have differential inputs. The common mode feed-back
the performance characteristics of wireless devices as they are (CMFD) is generally needed for two major reasons. One is to
power demanding blocks, especially in receiver systems.

978-1-5386-0930-9/17/$31.00 ©2017 IEEE

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 Fig. 1. A fully differential double folded cascode class AB with CMFD network.

control the common mode voltages at different nodes that Fig. 2 shows the suitable high swing bias network for the
negative differential feedback can stabilize. The other one is to proposed opamp. In order to minimize the systematic
overwhelm the common mode components that tend to mismatch error and to scale the circuit, all the resistors
saturate with the diversity of stages. Fig. 1 shows a fully RP1=RP2=40 kŸ chosen and NMOS transistors have
differential double folded cascode class AB opamp with length=1—M and width=2—M. Also, PMOS transistors have
continuous time common mode feed-back network (CMFD). length=1—M and width=8—M. The current source is 10 —A.
CMFD is not only a simple element but also it has high
common mode rejection ratio (CMRR) which is significantly
important in opamp performance, so flowing current must be
adjusted carefully. Any increment in bias current is fulfilled
by increasing the width of transistors in current source design
and this is also valid for composite transistors.
Significant area savings and a higher cutoff frequency are
two main specifications of this design. As it can be observed
from Fig. 1, common gate transistors are for increasing gain
and to reduce the differential input capacitance. The minimum
size of the capacitors is determined in order to limit the SNR
and for the maximum signal swing limited by the power
supply. In this design, resistors R1=R4=200 Ÿ, R2=R3=100 Ÿ
and all capacitors are 6 pF. VDD=1.8 V, CL=2 pF, and Itail is
160 —A. Table I describes the transistor values of designed
opamp. It can be mentioned that the common mode voltage is
900 mV.

TABLE I. TRANSISTOR SIZES OF PROPOSED OPAMP Fig.2. Biasing circuit of proposed opamp.
Name of Length Width Name of Length Width
Transistor (—M) (—M) Transistor (—M) (—M) III. SIMULATION RESULTS
M1,M2 1 8 M17,M18 0.5 3
M3,M4 0.5 3 M19,M20 0.5 1 Fig. 3 shows the qualified setup for doing AC analysis for
M5,M6 0.18 1 M21,M22 0.5 3 fully differential and common mode path that gain and phase
M7,M8 0.18 10 M23,M24 0.5 1 margin can be obtained. Fig. 4 shows the gain and phase
M25,M26,M27 margin of designed opamp which are 117 dB and 65-degree,
M9,M10 1 2 1 8
M28,M29,M30
M31,M32
respectively. Also, Fig. 5 shows the gain of 82 dB and phase
M11,M12 0.18 0.5 0.28 11 margin of 82-degree for common mode path. The transient
M33,M34
M13,M14 0.5 1 M35 1 2 analysis has been done to Vo+, Vo-, Vdiff, and Vocom. Fig. 6
M15,M16 1 2 M36 1 2 shows transient analysis which illustrates that the settling time

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 is well enough for driving proposed ADC. In this design, the
power consumption is 1.2 mW. The simulation results are
given in Table II, and in order to verify the performance of
proposed design, comparison with other previous works has
been done in Table III which proves it is well suited for ADC
applications as it has high gain, high speed, and low power
dissipation. In the table, even though the supply voltage and
power dissipation in previous works nominated in references 4
to 6 are better than the proposed opamp, their DC gains are
Fig. 3. Experimental AC analysis measurement setup for the proposed opamp.
low. Even when considering the work in reference 7, it can be
observed that supply voltage and phase margin is better than
the proposed opamp, but slew rate is not too appropriate and
DC gain is low with respect to our design.

TABLE III. COMPARISON OUTCOMES WITH OTHER OPAMPS

Parameters Proposed [4] [5] [6] [7] Unit
Supply
1.8 1.2 0.8 0.6 1.2 V
Voltage
Power
1200 36 1 650 1800 —W
Dissipation
Slew Rate 12.5 20 0.12 - 98.7 (V/—s)
DC Gain 117 33.8 51 87 75.4 dB
Fig. 4. Gain and phase of proposed opamp. Phase
65 45 65 75 82.5 deg
Margin

IV. TEST OF THE OPAMP

After designing proposed opamp, some specific tests have
been done in order to verify that under real conditions how
well the proposed opamp is operating.
A. Offset Cancellation Test
In this section, mismatches are generated by differing the
Fig.5. Gain and phase of common mode path.
dimensions of the input transistors of the opamps with the
percentage of 2 and 3. Same analysis is done by modifying
one of input transistor as the ratio 3%. The results show that
3% mismatch did not disrupt the design. Moreover, the bit
error rate is calculated as 0.02%.
B. Monte Carlo Analysis
This analysis is performed at 10 Monte-Carlo points and is
included transient noise analysis for 200 samples where bit
error rate (BER) is calculated that shows well-suited error.
C. Corner Analysis
Fig.6. Transient analysis of opamp.
The corner analysis is performed at 3 different (-40oC,
TABLE II. PERFORMANCE SUMMARY OF THE DESIGNED OPAMP 25 C, 85oC) temperatures and also 3 different models
o

(tt_model, ss_model, ff_model). This analysis shows that the

Parameters Value Unit
Technology 0.18 —m proposed opamp works well and respond correctly with the
Supply 1.8 V overall bit error rate 0.02%.
Total load capacitance 2 pF
Dc gain of proposed opamp 117 dB V. OPAMP APPLICATION
Phase margin of proposed opamp 65 deg To match the input range of the ADC, opamps are used as
Dc gain of common mode path 82 dB
Phase margin of fully differential 82 deg
drivers for enhancing the gain and level shifting. The task of
Power consumption 1.2 mW selecting appropriate opamp is not straightforward and opamp
Slew rate 12.5 V/—s performance must be measured under identical conditions in
Input referred noise 40.05 —Vrms ADC applications. Some important specifications are fast
CMRR >70 dB settling to ADC transient, high bandwidth, low noise, low
PSRR >70 dB distortion, low power, etc. Fig. 7 shows the appropriate 12-bit

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pipeline ADC with foreground calibration. It is a 12-bit VI. CONCLUSION
pipeline ADC using three 4-bit stages and one 4-bit flash A fully differential double folded cascode class AB
ADC. In other words, each stage of a pipeline ADC resolves 4
operational amplifier with continuous time common mode
bits and it has a digital error correction logic. Each of the
identical stages contains a sub-ADC and MDAC. Calibration feedback network is designed and simulated using cadence
parts consist of three 4-bit adders and also three D-Flip flops. simulator in 0.18 —m CMOS process. This design operates on
Pipeline architecture is appropriate and suitable application for 1.8 V supply, achieving a high DC gain of 117 dB, phase
this proposed opamp due to balanced power, speed, and margin of 65-degree and 1.2 mW power dissipation. In order
accuracy. This output result can suffer from errors and the to check and verify the well-performance of the design,
digital data outcome may not represent the real and correct different tests have been done and shown good agreement. In
values because of the presence of offset voltages in the Analog-to-Digital converters, high resolution and high speed
comparators of 4-bit flash ADC. Residue transfer curve for a 4 are two important specifications which our design tries to
bits/stage is shown in Fig. 8. Fig. 9 shows the output of 12-bit achieve these where the proposed opamp can be employed as
pipeline ADC. an efficient pipeline ADC driver.

REFERENCES
[1] S. Zhang, Z. Zhu, H. Zhang, Z. Xiong, and Q. Li, "A 90-dB DC gain
high-speed nested gain-boosted folded-cascode opamp," 2015 11th
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[6] R. Zou, "Design of a Fully Differential GAIN Boosted Operational
Amplifier for High Performance ADC," 2013 Sixth International
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[7] A. D. Sundararajan and S. M. Rezaul Hasan, "Quadruply Split Cross-
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2016.

Fig. 8. Residue transfer curve for a 4 bits/stage.

Fig. 9. Output of 12-bit pipeline ADC.

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