Review: Static Complementary CMOS

‰ High noise margins

z VOH and VOL are at VDD and
GND, respectively
VDD
‰ Low output impedance, high
Transmission Gates In1 input impedance
Pass Transistor Logic In2 PUN

…
‰ No static power consumption
InN
F(In1,In2,…InN) z Never a direct path between
VDD and GND in steady state
In1
In2 PDN ‰ Delay a function of load

…
InN capacitance and transistor on
resistance
‰ Comparable rise and fall
PUN and PDN are dual logic networks times (under the appropriate
relative transistor sizing
conditions)
1 2

Review: Static CMOS Full Adder Circuit NMOS Transistors in Series/Parallel

!Cout = !Cin (!A v !B) v !A !B !Sum = Cout (!A v !B v !Cin) v !A !B !Cin
‰ Primary inputs drive both gate and source/drain
terminals
B
‰ NMOS switch closes when the gate input is high
A B B A B Cin
A
A B
A Cin X = Y if A and B
!Cout !Sum X Y
Cin
A Cin A

A B X = Y if A or B
A B B A B Cin X Y
B
‰ Remember - NMOS transistors pass a strong 0 but a
weak 1
Cout = Cin (A v B) v A B Sum = !Cout (A v B v Cin) v A B Cin

3 4
PMOS Transistors in Series/Parallel Pass Transistor (PT) Logic

‰ Primary inputs drive both gate and source/drain B

terminals B
A A
‰ PMOS switch closes when the gate input is low F B
B
0 F
A B 0
X = Y if A and B = A + B
X Y
A ‰ Gate is static – a low-impedance path exists to both
supply rails under all circumstances
B X = Y if A or B = A • B
X Y ‰ N transistors instead of 2N
‰ No static power consumption
‰ Remember - PMOS transistors pass a strong 1 but a ‰ Ratioless
weak 0 ‰ Bidirectional (versus undirectional)

5 6

Pass Transistor (PT) Logic VTC of PT AND Gate

B
B
B
A A 1.5/0.25
F=A•B B
2
B
0 F=A•B B=VDD, A=0→VDD

Vout, V
0.5/0.25
0
1
A 0.5/0.25
B A=VDD, B=0→VDD
F= A•B
‰ Gate is static – a low-impedance path exists to both A=B=0→VDD
0 0.5/0.25
0
supply rails under all circumstances 0 1 2
Vin, V
‰ N transistors instead of 2N
‰ No static power consumption
z Pure PT logic is not regenerative - the signal
‰ Ratioless gradually degrades after passing through a number
‰ Bidirectional (versus undirectional) of PTs (can fix with static CMOS inverter insertion)
7 8
Differential PT Logic (CPL) CPL Properties
A
A PT Network ‰ Differential so complementary data inputs and outputs
B F are always available (so don’t need extra inverters)
B
F

‰ Still static, since the output defining nodes are always

A tied to VDD or GND through a low resistance path
A Inverse PT F
B Network F
B ‰ Design is modular; all gates use the same topology, only
the inputs are permuted.
B B B B B B
‰ Simple XOR makes it attractive for structures like adders
A A A
‰ Fast (assuming number of transistors in series is small)
B F=AB B F=A+B A F=A⊕B
‰ Additional routing overhead for complementary signals
A A A
F=AB F=A+B F=A⊕B ‰ Still have static power dissipation problems
B B A
AND/NAND OR/NOR XOR/XNOR

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CPL Full Adder CPL Full Adder

B B Cin Cin B B Cin Cin

A !Sum A !Sum

A Sum A Sum

B B Cin Cin B B Cin Cin

A !Cout A !Cout
B Cin B Cin
A Cout A Cout
B Cin B Cin

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 NMOS Only PT Driving an Inverter Voltage Swing of PT Driving an Inverter

3
In = VDD
In
Vx = M2 In = 0 → VDD
VGS
A = VDD VDD-VTn 1.5/0.25 2
D S x = 1.8V

Voltage, V
D
S
x
B M1 VDD Out
0.5/0.25
1
B 0.5/0.25
Out
0
‰ Vx does not pull up to VDD, but VDD – VTn 0 0.5 1 1.5 2
Time, ns
‰ Threshold voltage drop causes static power ‰ Body effect – large VSB at x - when pulling high (B is
consumption (M2 may be weakly conducting forming a tied to GND and S charged up close to VDD)
path from VDD to GND)
‰ So the voltage drop is even worse
‰ Notice VTn increases of pass transistor due to body
effect (VSB) Vx = VDD - (VTn0 + γ(√(|2φf| + Vx) - √|2φf|))
13 14

Cascaded NMOS Only PTs Solution 1: Level Restorer

Level Restorer
B = VDD B = VDD C = VDD
G on
M1 x M2 y Out Mr
M1 A = VDD
A = VDD x = VDD - VTn1 B off
S
G A=1 M2 Out=0
y Mn
x= 0
C = VDD M2 Out A=0 Out =1
S 1
M1

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1

‰ Full swing on x (due to Level Restorer) so no static
power consumption by inverter
z Pass transistor gates should never be cascaded as on
‰ No static backward current path through Level Restorer
the left and PT since Restorer is only active when A is high
z Logic on the right suffers from static power dissipation
and reduced noise margins ‰ For correct operation Mr must be sized correctly (ratioed)

15 16
Transient Level Restorer Circuit Response Solution 2: Multiple VT Transistors
3 W/L2=1.50/0.25 ‰ Technology solution: Use (near) zero VT devices for the
W/Ln=0.50/0.25
NMOS PTs to eliminate most of the threshold drop (body
W/L1=0.50/0.25
effect still in force preventing full swing to VDD)
2 node x never goes below VM
of inverter so output never low VT transistors
switches
W/Lr=1.75/0.25 In2 = 0V A = 2.5V
Voltage, V

on
W/Lr=1.50/0.25
1
Out

W/Lr=1.25/0.25 off but

W/Lr=1.0/0.25 leaking
0 In1 = 2.5V B = 0V

0 100 200 300 400 500 sneak path

Time, ps

‰ Restorer has speed and power impacts: increases the

‰ Impacts static power consumption due to subthreshold
capacitance at x, slowing down the gate; increases tr (but
currents flowing through the PTs (even if VGS is below VT)
decreases tf)
17 18

Solution 3: Transmission Gates (TGs) Solution 3: Transmission Gates (TGs)

‰ Most widely used C
‰ Most widely used
C C C
solution solution
A B A B
A B C A B C

C C

C = GND C = GND
C = GND C = GND

A = VDD B A = GND B
A = VDD B A = GND B

C = VDD C = VDD
C = VDD C = VDD

‰ Full swing bidirectional switch controlled by the gate ‰ Full swing bidirectional switch controlled by the gate
signal C, A = B if C = 1 signal C, A = B if C = 1
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Resistance of TG TG Multiplexer
S S F
W/Lp=0.50/0.25 S
30
0V VDD
25
Rn Rp
In2
20 2.5V Vout
Resistance, kΩ

Rp
15 Rn S F
2.5V
10
Req
In1
W/Ln=0.50/0.25
5

0 S
0 1 2
Vout, V
F = !(In1 • S + In2 • S) GND

In1 S S In2

21 22

Transmission Gate XOR Transmission Gate XOR

weak 0 if !A

off
on A • !B
A A⊕B A A⊕B
off
on B • !A

weak 1 if A
0
B B
an inverter
1

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TG Full Adder Differential TG Logic (DPL)

B A B A B A B A

Cin A
A
B F=AB B F=A⊕B
GND
B A
B
GND
A Sum
VDD A

A F=AB B F=A⊕B
VDD A
Cout B B
AND/NAND XOR/XNOR

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