ECT304 -

VLSI CIRCUIT DESIGN

1
 Module 2
 MOSFET Logic Design – NMOS Inverter
(Static analysis only), basic logic gates
 CMOS logic, Static and transient analysis of
CMOS inverter, Switching power dissipation
and delays.
 Realization of logic functions with static
CMOS logic, Pass transistor logic, and
transmission gate logic

2
CMOS inverter
VDD

Vin Vout

CL

3
n-MOS drain
characteristics
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3
VDS = VGS - VT
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

4
p-MOS drain
characteristics
-4
x 10
0

-0.2

-0.4
ID (A)

-0.6

-0.8

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

5
CMOS inverter DC analysis
VDD VDD

Rp

Vout
Vout

Rn VOL = 0
VOH = VDD

Vin= VDD Vin= 0

6
Voltage Transfer Characteristics(VTC)
of CMOS inverter
The objective is to find the variation in
output voltage (Vout) as a function of
the input voltage (Vin).
 For that various regions of operation
for the n- and p-transistors are to be
considered
Superimpose the current characteristics
of the NMOS and the PMOS devices.
Such a graphical construction is
traditionally called a load-line plot.
7
nMOS operating mode

8
pMOS operating mode

9
Regions of operation

Vtn is +ve, Vtp is -ve

10
Transforming PMOS I-V characteristic to a
common coordinate set to get load line curve

 Assume VDD=2.5

11
Transforming PMOS I-V characteristic to a
common coordinate set to get load line curve

-4
x 10
6
VGS= 2.5 V

ResistiveSaturation
4
VGS= 2.0 V
ID (A)

3
VDS = VGS - VT
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS(V)

nMOS pMOS 12
Load curves for NMOS and PMOS
transistors of the static CMOS inverter
ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1

Vin = 1.5 Vin = 1

Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout
 The dots represent the dc operation points
for various input voltages. Vin = 0, 0.5, 1,
13
CMOS inverter VTC

Vout
NMOS off
PMOS res

2.5
NMOS sat
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2 .5 Vin

14
CMOS inverter VTC/static
characteristics

15
CMOS inverter VTC

We assume Vtp = –Vtn and that

the pMOS transistor is 2–3 times
as wide as the nMOS transistor so
n =p.

16
CMOS inverter regions of
operation
Region A: n device off
Region B:
n device in sat.
p device in linear.
For p device

Equating these two currents

Vo=? 17
CMOS inverter regions of
operation
Region C: Both n and p
devices in sat

If we take

18
The crossover point where Vin = Vout
is called the switching threshold or
inverter threshold voltage.

Vth

 At that point

19
CMOS inverter regions of
operation
Region E: p device off, n device
on :Vo=0
Region D:
p device in sat.
n device in linear.

Equating these two currents

Vo=?
20
Summary of CMOS
inverter
 The circuit consists of one nMOS and one pMOS transistor
 It can be created by connecting a p-channel and a n-channel
transistor.
 The n-channel transistor acts as a pull-down transistor and
the p-channel acts as a pull-up transistor.
 Depending on the input, only one of two transistors conduct.
When
the input is low, the p-channel transistor between VDD and
output is in its “on” state and output is pulled-up to VDD,
thus inverting the input. During this state, the n-channel
transistor does not conduct.
 When input is high, the output goes low. This happens due to
the
“on” state of the n-channel transistor between GND and
output. This pulls the output down to GND, thus inverting the
input. During this state, p-channel transistor does not
conduct.
21
 Switching speed depends on time taken to charge
and discharge the load capacitance.
 An I/p transition results in an o/p transition that either
charges towards Vdd or discharges toward Vss/gnd

22
 CMOS logic- Complementary
CMOS
 The most widely used logic style is static
complementary CMOS.
 The static CMOS style is really an extension of
the static CMOS inverter to multiple inputs.
 At every point in time (except during the
switching transients), each gate output is
connected to either VDD or Vss via a low-
resistance path.
 The primary advantage of the CMOS structure
◦ Robustness (i.e, low sensitivity to noise)
◦ Good performance, and low power consumption
with no static power dissipation.
23
Complementary logic gate as a
combination of a PUN (pull-up
network) and a PDN (pull-down
network).

24
Complementary CMOS-2 i/p
NAND

25
 Complementary CMOS
The pull-up and pull-down networks
of a complementary CMOS structure
are dual networks.
This means that a parallel
connection of transistors in the pull-
up network corresponds to a series
connection of the corresponding
devices in the pull-down.
The number of transistors required
to implement an N-input logic gate
26
Complementary CMOS-2 i/p
AND

27
Complementary CMOS-2 i/p
NOR

28
Complementary CMOS-
compound gate 1

29
Complementary CMOS-
compound gate 2

30
Complementary CMOS-
compound gate 3
Y= ?

31
Complementary CMOS-
compound gate 4

32
Pseudo NMOS logic
 Less number of transistors to implement a
given logic function, at the cost of reduced
robustness and extra power dissipation.
 The entire PUN is replaced with a single
grounded PMOS load.
 Instead of a combination of active pull-
down and pull-up networks, an NMOS pull-
down network that realizes the logic
function, and a simple grounded PMOS
load.
 Ratioed logic

33
Pseudo NMOS logic
At the PU section
there is a PMOS load
device
NMOS pull-down
network realizes the
logic function
PMOS pulls up the
output for a high
output.
34
Pseudo NMOS logic
 The advantage of pseudo-NMOS is the
reduced number of transistors (N+1 versus
2N for complementary CMOS).
 The nominal high output voltage (VOH) for
this gate is VDD since the pull-down devices
are turned off when the output is pulled
high.
 The nominal low output voltage is not 0 V.

(Can be understood from VTC curve of

CMOS inverter)
 This results in reduced noise margins and
causes static power dissipation.
35
Recap of Load curves of the static CMOS
inverter to determine pseudo NMOS VTC
ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1

Vin = 1.5 Vin = 1

Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout
Need to consider the point of intersection of
NMOS curves with PMOS Vin=0 curves (blue
dots) . 36
Recap: CMOS inverter VTC and
effect of beta ratio

Vout
NMOS off
PMOS res

2.5
NMOS sat
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2 .5 Vin

37
Voltage-transfer curves of the pseudo-
NMOS inverter as a function of the
PMOS size

38
Ratioed logic
Since the voltage swing on the
output and the overall
functionality of the gate depends
upon the ratio between the NMOS
and PMOS sizes, the pseudo NMOS
circuit is called ratioed.
(In ratioless logic styles, such as
complementary CMOS, the low
and high levels do not depend
upon transistor sizes.)
Refer Rabaey Text Book for analysis 39
4 i/p NOR using pseudo NMOS

40
Reference
1. Sung –Mo Kang & Yusuf Leblebici, CMOS
Digital Integrated Circuits- Analysis &
Design, McGraw-Hill, Third Ed., 2003
2. Jan M. Rabaey, A. Chandrakasan, B. Nikolic,
Digital Integrated Circuits- A Design
perspective, 2/e, Pearson education
3. Weste and Eshraghian, Principles of CMOS
VLSI Design, A Systems Perspective,2/e,
Pearson Education
4. Neil H. E. Weste, David Money Harris,
CMOS VLSI Design- Circuits and Systems
Perspective, 4/e, Pearson education
41
Gate implementations using
pass transistor

Try yourself : Implement using CMOS transmission

gate logic 42