Jour of Adv Research in Dynamical & Control Systems, Vol.

10, 05-Special Issue, 2018

Optimized 2nd Order Continuous-Time

Sigma-Delta Modulator with 29.92µW
Power, 137.27 dB SNR, and 10MHz
Bandwidth
Anshu Gupta, Maulana Azad National Institute of Technology, Bhopal.
Lalita Gupta, Maulana Azad National Institute of Technology, Bhopal.
R.K. Baghel, Maulana Azad National Institute of Technology, Bhopal.
Abstract--- We present single bit Delta Sigma modulator of continuous time (CTDSM) using dynamic latch
comparator inherit the less delay and high speed and active RC integrator using three stage feed-forward OTA.
Design of the circuit and its simulation results for a 23 bit resolution of modulator is presented. This converter,
implemented in an 180nm CMOS process, obtains a dynamic range of 140 dB in a bandwidth10MHz and consumes
low power 29.92 µW from a supply voltage of 1 V. Analyzed results are incorporated in design of a second order
continuous time delta sigma modulators with resistive DAC which attains a peak Signal to noise ratio of 137.2 dB
and obtains acceptable level of linearity. Simple resistive DAC design, proposed ultra-low power dynamic
comparator and OTA designs are used for minimizing power dissipation and enabling easy performance, at the same
time these methodologies make it suitable to implement a good performance delta sigma modulator with ultra-low
dissipation of power and lesser area, which is desirable in various communication applications.
Index Terms--- ADC, Continuous Time, Ultra-Low Power, Oversampling.

I. Introduction
Continuous – time delta sigma modulation is well accepted for higher resolution ADC due to its adequate
requirements for many applications. To provide shaping to quantization noise using quantizer in band. Over last few
years, many delta sigma modulators of continuous time type have been demonstrated [1]. Usually discrete time delta
sigma modulators were used. Now days, interest towards continuous time DSM has been increased tremendously.
Implicit anti-aliasing, reduced BW requirements of active counterparts and remarkable power savings are some
attractive features over discrete time DSM. To digitize small frequency analog signals, CTDSMs are used due to its
power saving feature which is a key motivator. As shown on fig. 1 interface electronics is nothing but analog to
digital converter or vice versa with different specification as per the required application. Several designs pointing
this range ≥ 10MHz have been investigated in the last few years. After survey, we present the implementation of 23
bit CTDSM for many applications of wireless communication. The proposed DSM is designed using CMOS
process180nm, consumes 29.92µW power from supply of 1 V and attains a 140 dB dynamic range for a 10 MHz
signal bandwidth. Oversampling ratio i.e. OSR of 64 is utilized in this design. This delta sigma modulator having
several techniques to reduce power such as low power comparator and low power OTA has been used in the DSM.

Fig. 1: Block Diagram of Analog to Digital Conversion

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Multi-bit quantizer has many advantages e.g. it increases no. of levels and reduces OSR to get appropriate signal
to noise ratio (SNR). As no. of level increase, step-size decreases which further cause reduction in sensitivity to jitter
due to clock, also the SR needed of the OTA in the analog loop filter. However, circuit design becomes tough and
complex for multi-bit quantizer as no. of bits start increasing. Therefore, comparator in the quantizer must be low
power, low voltage and should be design for less delay for the desired power dissipation.
We demonstrate design methodology to implement a three stage OTA with ultra-low power operates in sub-
threshold mode, which results less area and permitted to drive high capacitive loads. We adopt this approach when
we need ultra-low power and low voltage as the design constraints. Using 1 V supply voltage and having very low
power 296.72nW the implemented three stages OTA can drive upto 200pF. On comparison, three stages OTA
proposed structure shows significant enhancement in small signal and large signal performance. Sub-threshold
Devices achieve low bandwidth which can be compensated by high transition frequency when technologies are
scaled down. Therefore, sub-threshold mode is appropriate in that application where speed is not a concern [20].
These techniques are popular in the designing of Operational Transconductance Amplifiers and other sub-blocks
supplied by 1 V supply and with small consumption of current of the order of nA[21]-[25]
We also present another proposed structure of dynamic comparator. Analysis to calculate delay is presented and
based on the conventional comparator, new one is demonstrated. New proposed methodology doesn’t require
boosting in voltage or stack of many transistors. Only by connecting few transistors of minimum dimensions to the
conventional one, delay has been reduced enormously. Modifying conventional comparator also shows some
improvement such as remarkable power saving.

Fig. 2: Aperture Plane of State-of-the-Art ADC

On comparing to other ADCs, CTDSMs cover wider region of the resolution vs. BW plot as shown in fig. 2,
providing the efficient converter to digitize analog signals in various applications starting from biomedical devices
to WB communications. In fact, CTDSMs can achieve more accurate converter by combining noise shaping and
oversampling despite the use of imprecise components. One more advantage of relaxation in antialiasing filter
requirement makes it suitable as first choice for designing new circuits [26] and [27].
Details of architecture and circuit design of CTDSM are described in this paper, which has been arranged as
follows. Section II describes different architecture possibilities in modulator. In III Section we delve into the
realization part such as different units used in the DSM design. Results of the simulation from the proposed delta
sigma modulator implemented in an 180nm CMOS Technology are displayed in IV section. Lastly, conclusion of
the paper is described in last Section V.

II. Architectural Development

The State of the art on Converters (ADCs) is presently ruled by three types of ADCs, Namely: Delta sigma
modulators, Successive Approximation Register, Pipeline, which every year pushing the energy efficiency.
Moreover, to compare delta sigma modulators with other different converters, different types of analog to digital
converters can also be compared, such as cascade or single quantizer topology; band pass or low pass; multi-bit or

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

single bit ;discrete time DSMs using SC technique or CTDSMs using either active RC or Gm-C techniques. Hybrid
DSMs has been also used where combination of diverse techniques, such as DT and CT, oversampling with nyquist
ADCs, passive and active circuits, etc.
We present single loop topology over MASH topology to reduce the possibility of complexity which comes from
the overhead circuitry required to match the noise transfer function (NTF) and digital noise cancellation filter.
Second order noise transfer function is utilized to obtain peak signal to noise ratio (SNR) above 120dB (Bandwidth
10MHz). Therefore, thermal noise will limit the performance of the design.

III. Circuit Design

Architecture of Modulator
Loop filter is shown in the fig.3. Summing amplifier is used to perform the addition of analog input to the
feedback output from the DAC. The OTA used in the first and second integrator has an input stage of pMOS device
to get lower 1/f noise. The summing amplifier use single stage folded cascode differential pair. Thermal noise from
the analog input, input referred noise of the OTA and DAC resistors dominates the input referred noise of the analog
loop filter.

Fig. 3: System Level Diagram of Second Order DSM

Integrator OTA
As we have various methodologies in literature which are appropriate to design loop filter of CTDSMs.
Integrators used to design loop filters significantly dominate the performance of a CTDSM. Location of the
integrator decides the linearity and noise factor. Second integrator causes some non-idealities which are suppressed
by first integrator; therefore it is the first integrator who decides the performance. Active RC integrator is
implemented using operational Transconductance amplifier as the primary block and this block is power hungry. It
is a big challenge for everyone to make it dissipates less power. To achieve lesser power, we have new technique to
design three stages OTA which operates in sub-threshold region where feed-forward compensation method is used.
Proposed OTA is low power dissipates only 296.72nW and gain bandwidth product is of 159.15 KHz. Proposed
three stages OTA at ultra-low power in sub-threshold region is implemented, which results lesser silicon area and
drives heavy capacitive loads upto 200pF at 1 V supply voltage. Further, we see improvements for Small signal and
large signal analysis.

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Fig. 4: Schematic Circuit Diagram of Three Stage OTA Operating in Sub Threshold Region
Fig.4. represents the topology of the OTA used for the integrator design in this paper. Here, two integrators in
the second order DSM are same with respect to device dimensions.

Fig. 5: Small Signal Model of Three Stage OTA with Feed-Forward Compensation Strategy
Three Stage OTA operates in sub-threshold region is shown in fig.4.P Channel MOS devices M1 and M2 are
forming differential input stage and folded cascade structure is made by transistors M1-M10 which provides high
gain. Devices M5-M8 forms current mirror and this folded cascode operates at extreme low voltage i.e. 1 V supply.
pMOS devices M1 & M2 gives first stage transconductanceg ma . Second inverted stage is formed by common source
transistor M12. Last stage is implemented using M13- M16 transistors and this is non-inverting in nature. Gate of
M16 transistor is coming from output of the first stage and forms class AB stage to drive high capacitive loads and
provides feed-forward transconductanceg mF .
To get stable phase margins from three stages OTA, we need well suited compensation circuit. After surveying
different methods which are reported earlier, we concluded to use feed-forward compensation using two capacitors
to implement miller effect. Since there is no connection from inner capacitor to output stage, henceforth we get
better bandwidth potential. First time investigated proposed compensation strategy has many advantages. Proposed
compensation technique in fig.5 is made by two capacitors C ca and C cb and it also has transconductanceg mf of feed
forward stage.

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Fig. 6: Gain and Phase Plot of Three Stage Operational Transconductance Amplifier
Table I: Simulated Amplifier Performance Parameters
Parameter Value
DC gain (dB) 107.1
GBW (KHz) 159.141
PM ( degrees) 50
Power Dissipation (nWatt) 296.721
Supply Voltage (V) 1
Capacitive Load (pF) 200
Input referred noise@1Kilohertz (pV/√Hz ) 2.2647

IV. Comparator
Comparators having two tail transistors perform much better at low voltages. Important concept in the proposed
comparator is to increase ΔV Gn/Gp voltage so that latch regeneration speed can be improved.
Table II: Simulation Results of Dynamic Comparator
Design Parameter Standard Comparator with two tail and two switch transistors
Technology(nm) 180
Supply voltage (V) 1
Transistor count 16
Offset Voltage (mV) 7.8
Power Dissipation (µW) 10.99
Delay (nS) 0.49
Speed (GHz) 3
SR+/SR- (µV/S)@ CL =1pF 10.96/ 30.26
SR+/SR- (µV/S)@ CL =5pF 2.10/6.19
Settling Time(nS) @ CL = 1pF 148.97
Settling Time(nS) @ CL = 5pF 746.72
Fig. 7 depicts the schematic circuit of the proposed dynamic comparator. Two special transistors acting as
controlled transistors M11 and M12 are connected in parallel to M3 and M4 transistors in first stage but we connect
them in cross coupling manner. Functioning can be explained as follows: during first phase of reset and clock is kept
zero, Tail transistors M15 and M16 are kept off (keep static power to zero) , intermediate nodes Gp and Gn are
further charged to supply voltage via transistors M3 and M4, henceforth M11 and M12 are being off. Eventually
output of the latch is pulled down to ground via transistors MR1 and MR2. We discuss second case when clock is
kept VDD and two transistors M15 and M16 acting as tail transistors are turning on, transistors M4 and M3 are
becoming off at this stage. Sequentially, when decision making stage starts operating, two transistors M11 and
M12are not in conduction (because Gp and Gn nodes are utmost equal to supply voltage). According to the applied
input voltages GpnadGn start falling with different rates. If one input is greater than the other input, then

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

intermediate output node of that branch starts falling faster. When one starts falling faster, the pMOS controlling
transistor M11 here becoming turning on, pulls other intermediate node to the supply voltage; and therefore, other
controlling MOS transistor M12 remains turned off, permit Gn to be discharged completely. Here, when Gn
discharges faster transistor M11 turned on, causes Gp to fully charge upto VDD. Therefore, difference between Gn
and Gp i.e ΔVGn/Gp increases in exponential manner, resulting small regeneration time. Two nMOS transistors are
placed as controlled switches below the MOS transistors M13 and M14 at the input to reduce the static power
dissipation. Table II shows the simulated results of the dynamic comparator.

Fig. 7: Schematic Circuit of Two Tail Dynamic Latch Comparator

Transient response of proposed two tail dynamic comparator is shown in Fig. 8 and Fig. 9 shows transient
response of the proposed two tail comparator with two switch control transistors.

Fig. 8: Response of Latch Comparator without Switch Control Transistor (Transient Analysis)

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Fig. 9: Response of Latch Comparator with Switch Control Transistor (Transient Analysis)

V. Results
The continuous-time DSM of first order and second order were implemented in an 180nm CMOS process. Fig.
10, fig. 11, fig. 12 and fig. 13 show the system level diagrams and its transient responses for first order and second
order DSMs respectively.

Fig. 10: System Level Diagram of First Order DSM

Fig. 11: System Level Diagram of Second Order DSM

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Fig. 12: Transient Response of First Order DSM

Fig. 13: Transient Response of Second Order DSM

Fig. 14 represents the Power Spectral Density of the first order modulator which results in the peak SNR. The
dynamic range (DR) and peak signal to noise ratio (SNR) are 101 dB and 99.5 dB respectively.

Fig. 14: Power Spectral Density of First Order DSM with 4096 Points and Hanning Window

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Fig. 15 depicts the power spectral density of the second order modulator which results in the peak signal to noise
ratio (SNR). The dynamic range (DR) and peak signal to noise ratio (SNR) are 140 dB and 137.2 dB respectively.
Response of the quantizer is shown in shown in fig. 16

Fig. 15: Power Spectral Density of Second Order DSM with 4096 Points and Hanning Window

Fig. 16: Transient Response of 1 bit Quantized Output

Table III: Design Specifications of Sigma Delta Modulator
Parameter Target Specification
Operating Frequency [MHz] 10
Sampling Frequency [GHz] 1.28GHz
SNDR [dB] 140 dB
Resolution [ENOB] 23 bits
Oversampling Ratio 64
Table IV represents a summary of performance results. Table IVshows comparison between this work and other
state of the art designs in the literature. Earlier reported designs [3]–[5], [17]–[20] obtained SNDR greater than 94
dB–using multi-bit quantizer. Our proposed CTDSM design is achieving better Figure of merit and better SNR
(excepting [19]), despite using a single-bit structure. It is demonstrated that the DSM proposed in this paper has a
Schreier FOM better than reported in the table V, a higher dynamic range and signal to noise and distortion ratio at
the simultaneously. This depicts the inherent advantages of using proposed architecture.
Table IV: Summary of Performance Results
Clock rate/Signal Bandwidth 1.28GHz/10MHz
DR/SNR 140 dB/ 137.2 dB
Process/Supply 180nm CMOS/ 1 V
Power Dissipation 29.92µW
FOM Schreier 255.2 dB

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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 05-Special Issue, 2018

Table V: Comparison of Performance with the Previous CT DSM with the Signal Bandwidth ≥10MHz
This Work [6] [11] [15]
Process [nm] 180nm 90 65 65
Fs[MHz] 1280 500 840 900
BW[MHz] 10MHz 25 30 45
DR[dB] 140 72 77.1 82.5
Peak SNR [dB] 137.27 69 75.9 78.5
Operating Voltage [V] 1 1.2 1.1/2.3 1.2/1.8
Power [ µW] 29.92 85000 13000 24700
FOMs[dB] 255.2 166.7 170.7 167.9

VI. Conclusion
We presented optimization and analysis for ultra-low power single bit quantizer continuous-time delta sigma
converters using two tail standard comparator and three stage feed-forward compensated OTA. Active RC integrator
with resistive feedback was selected to lower the noise and power consumption. A cascaded structure of integrators
was chosen to realize loop filter. Comparison to multi-bit quantizer is also demonstrated with same specification.
These two optimized circuit of comparator and OTA were used to the second order CTDSM implemented in an
180nm CMOS Technology. Designed second order DSM has a DR of 140 dB, a peak Signal to noise ratio of 137.2
dB and Schreier figure of merit of 255.2 dB and dissipating 29.92µW from a supply voltage of 1 V. An
experimental prototype of 1 bit second order modulator has proven the productiveness of the proposed techniques,
also achieves very good performance with ultra-low power in the absence of any correction/calibration logic.

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