energies

Article
Reconfiguration of a Multilevel Inverter with
Trapezoidal Pulse Width Modulation
Nataraj Prabaharan 1, * ID , V. Arun 2 , Padmanaban Sanjeevikumar 3, * ID
, Lucian Mihet-Popa 4, * ID

and Frede Blaabjerg 5 ID

1 School of Electrical and Electronics Engineering, Department of Electrical and Electronics Engineering,
SASTRA Deemed University, Thanjavur 613401, Tamil Nadu, India
2 Department of Electrical and Electronics Engineering, Sri Vidyanikethan Engineering College,
Tirupathi 517102, Andhra Pradesh, India; varunpse@yahoo.com
3 Department of Energy Technology, Aalborg University, 6700 Esbjerg, Denmark
4 Faculty of Engineering, Østfold University College, Kobberslagerstredet 5, 1671 Kråkeroy, Norway
5 Center of Reliable Power Electronics (CORPE), Department of Energy Technology, Aalborg University,
Pontoppidanstræde 101, 9220 Aalborg, Denmark; fbl@et.aau.dk
* Correspondence: prabaharan.nataraj@gmail.com (N.P); san@et.aau.dk (P.S); lucian.mihet@hiof.no (L.M)




Received: 16 July 2018; Accepted: 13 August 2018; Published: 17 August 2018


Abstract: This paper presents different multi-carrier unipolar trapezoidal pulse width modulation
strategies for a reduced switch asymmetrical multilevel inverter. The different strategies are phase
disposition, alternative phase opposition and disposition, and carrier overlapping and variable
frequency that involve triangular waves as carriers with a unipolar trapezoidal wave as a reference.
The reduced switch, asymmetrical multilevel inverter operation was examined for generating the
seven-level output voltage using Matlab/Simulink 2009b and the results were verified with a real-time
laboratory-based experimental setup using a field-programmable gate array. Different parameter
analyses, such as total harmonic distortion, fundamental root mean square voltage, and distortion
factor, were analyzed with different modulation indices to investigate the performance of the
selected topology. Unipolar trapezoidal pulse width modulation provides a higher root mean
square voltage value.

Keywords: multilevel inverter; multi-carrier pulse width modulation; FPGA; trapezoidal pulse width
modulation; inverter

1. Introduction
The term multilevel originated from the two-level inverter. The elementary concept of the
multilevel inverter (MLI) is used to achieve high power with several DC voltage sources. In an MLI,
the amplitude of the output voltage is improved, which reduces the overall harmonic content and
switching stress of the device [1,2]. Generally, the flying capacitor multilevel inverter (FCMLI), diode
clamped multilevel inverter (DCMLI), and cascaded multilevel inverter (CHBMLI) are the three main
topologies of the conventional multilevel inverter. The FCMLI is hard to comprehend because it
contains many clamping capacitors and a DC bus capacitor. The DCMLI structure remains the same
as the FCMLI, but clamping diodes are used instead of clamping capacitors. In addition, FCMLI and
DCMLI are difficult to extend the level of the output voltage because of the use of the DC bus capacitor.
The balancing of the DC bus capacitor is the major concern in both topologies [3,4]. The most popular
conventional MLI is CHBMLI, which has many attractive features, such as a simple and modular
design, requires fewer component counts, and averts a unbalance in capacitor voltage. The symmetric
CHBMLI requires isolated DC sources with equal voltage whereas the asymmetric requires isolated

Energies 2018, 11, 2148; doi:10.3390/en11082148 www.mdpi.com/journal/energies

Energies 2018, 11, 2148 2 of 18

DC sources with unequal voltage. The DC source ratios 1:2:4 and 1:3:9 are termed as binary and trinary,
respectively [5].
Subsequently, several reduced switch MLI topologies have been addressed in symmetric,
asymmetric, and hybrid conditions with pros and cons for the different applications. In [6], a stepped
ladder-type cascaded inverter was presented. The presented ladder-type converter circuit consists
on series connection of unit cells and it’s generated the maximum number of levels with fewer
semiconductor devices, and supplied the sources and voltage on the switches. In [7], a lower switching
frequency control pulse width modulation (PWM) technique was applied to MLI-fed AC drives.
Lower switching frequency decreased the switching losses of the power semiconductor devices but
increased the total harmonic distortion. In [8], a new topology for symmetric and asymmetric MLI
was developed. An asymmetric MLI produced a high output voltage level compared to a symmetric
MLI. A nine-level cascade neutral point clamped inverter with low switching frequency pulse width
modulation (PWM) was presented in [9]. The capacitor voltage balancing was the major concern.
Additional control techniques are required to maintain the capacitor voltage. A hybrid MLI based on
a diode clamped type for both symmetrical and asymmetrical configurations was presented in [10].
However, the topology required more number of components. A different elementary division for
CMLI was introduced in [11]. Each elementary division was connected in series, which produced
only a positive level output voltage. An H-bridge was included with the elementary division to
produce the output voltage in both positive and negative sequences. However, the basic unit required
a greater component count. The harmonic investigation for a three-level NPCMLI-fed induction motor
drive was investigated in [12]. In-phase sinusoidal PWM and phase opposition PWM were used to
examine the system. The in-phase PWM method provided better results than the phase opposition.
In addition, conventional PWM was used. An asymmetrical MLI for traction drives was discussed
in [13]. A new hybrid inverter topology with common mode voltage elimination for an induction
motor drive was presented in [14]. This topology has only one DC source and different voltage levels
were generated using the floating capacitors. A reduced switch cascaded multilevel inverter with
several transformers and a single DC source was discussed in [15]. A transformer on the secondary
side was used to increase the output voltage level, but the cost and size of the transformer are very
high. In [16], an effective structure of an MLI that increases the number of output voltage levels with a
reduced number of circuit components was presented. This topology could not prefer a higher power
application because it had the diodes with a combination of switches. A novel PWM modulating
technique for a hybrid multilevel inverter was described in [17]. The carrier waveform originated from
the phase disposition carrier arrangement. Novel carrier-based PWM in neutral-point (NP) balancing
in the three-level inverter was presented in [18]. A hybrid modulation technique for cascaded MLI
for high power applications in renewable energy systems was examined in [19]. A new dual port
asymmetrical MLI with reduced conversion stages to improve the overall conversion efficiency of
the system was discussed in [20]. The neutral point clamped type and T-type three-level cells were
combined to build a dual port asymmetrical MLI. The developed topology provided better efficiency
for various DC/AC power systems [21].
The conventional topology DCMLI requires 6 DC bus capacitors, 12 switches, and 24 clamping
diodes while the FCMLI requires 6 DC bus capacitors, 12 switches, and 12 clamping capacitors to
generate the seven-level output voltage. However, the selected reduced switch asymmetric multilevel
inverter requires only eight switches to generate the same voltage. This paper focuses mainly on the
different multi-carrier strategies with a unipolar trapezoidal reference. The different multi-carrier
arrangements, such as phase disposition (PD), alternative phase opposition and disposition (APOD),
carrier overlapping (CO), and variable frequency (VF) pulse width modulation strategies are involved
for generating the seven-level output voltage. The carrier count of a unipolar method has been
reduced by half compared to the conventional PWM method, which is the main advantage of this
implementation. The reduced switch single-phase MLI was tested with the resistive and inductive (RL)
load using the Matlab/Simulink (2009b). Experimental work was carried out using an FPGA system
Energies 2018, 11, 2148 3 of 18

for strengthening the simulation results. The different parameters were evaluated and compared
with each other at different modulation indices. The VFPWM method indicates a better performance
compared to the other methods. In addition, the topology can be easily integrated with an appropriate
Energies 2018, 11
solar-based converter by replacing the separate DC sources to achieve good performance in the
photovoltaic application.
easily integrated with an appropriate solar-based converter by replacing the separate DC sources to
achieve good performance in the photovoltaic application.
2. Single-Phase Seven-Level Reduced Switch Asymmetrical Inverter
2. Single-Phase
Generally, Seven-Level
the number Reduced Switch
of semiconductor Asymmetrical
device requirement Inverter
for the MLI configurations depends on
the number of output voltage level. However, increasing the number offor
Generally, the number of semiconductor device requirement the MLI
power configurations
semiconductor devices
depends on the number of output voltage level. However,
leads to an increase in the topology design complexity, cost, and control difficulty. An increasing the number of asymmetric
power
semiconductor
multilevel inverter devices
(AMLI)leads can to bean increasetoinachieve
utilized the topology
a higherdesign complexity,
number cost, and
of output control
levels with the
difficulty. An asymmetric multilevel inverter (AMLI) can
minimum number of power semiconductor devices compared to symmetric MLIs [8]. Feedingbe utilized to achieve a higher number of the
output levels with the minimum number of power semiconductor devices compared to symmetric
converters with unequal DC voltages (asymmetrical feeding) increases the number of levels generated
MLIs [8]. Feeding the converters with unequal DC voltages (asymmetrical feeding) increases the
at thenumber
output of voltage without any supplemental complexity to the existing symmetric topology.
levels generated at the output voltage without any supplemental complexity to the
Figure
existing1symmetric
shows the single-phase asymmetric seven-level inverter configuration. The selected
topology.
asymmetric Figure 1 shows the single-phase
inverter consists asymmetric
of sub-multilevel invertersseven-level invertercell)
(low-power configuration.
and H-bridge The (high-power
selected
asymmetricSub-multilevel
cell) inverter. inverter consistsinverters
of sub-multilevel inverters (low-power
are connected in series tocell) and H-bridge
achieve (high-power
the desired number of
cell)levels.
voltage inverter.
Each Sub-multilevel
sub-multilevel inverters
inverterarehas
connected
its owninDC series to achieve
source and two thepower
desired numberThe
devices. of first
voltage levels.
sub-multilevel Each sub-multilevel
inverter consists of one inverter has its (V
DC source own DCDC
) source
and two and two
switches power devices.
designated The
as Sfirst
1 and S2
sub-multilevel inverter consists of one DC source (V DC) and two switches designated as S1 and S2
whereas the switches S3 and S4 and voltage source (2VDC ) are placed in the second sub-multilevel
whereas
inverter. Both thesub-multilevel
switches S3 andinverters
S4 and voltage source (2VDC
are connected in) are placed
series andingenerate
the second thesub-multilevel
required output
inverter. Both sub-multilevel inverters are connected in series and generate the required output
voltage level at positive polarity. To operate as an inverter, it is necessary to change the voltage
voltage level at positive polarity. To operate as an inverter, it is necessary to change the voltage
polarity in every half cycle. For this purpose, an H-bridge inverter is added with the sub-multilevel
polarity in every half cycle. For this purpose, an H-bridge inverter is added with the sub-multilevel
inverters. It is It
inverters. important
is important to to
note
note that
thatthe
theswitches
switches of of the
theH-bridge
H-bridge must
must withstand
withstand the higher
the higher voltage.
voltage.
This should
This should be considered
be considered in in
thethe designofofthe
design the inverter.
inverter. However,
However,these theseswitches
switches are are
turned ON or
turned ON or
OFF only
OFF only one onetimetime during
during a fundamentalcycle.
a fundamental cycle. Therefore,
Therefore, these theseswitches
switches would
would be high-voltage
be high-voltage and and
low-frequency
low-frequency switches.
switches. TheThe zero
zero outputvoltage
output voltage is is obtained
obtained whenwhenthe theswitches
switches S2 and S3 are
S2 and S3turned
are turned
ON, and simultaneously the other voltage levels are generated by
ON, and simultaneously the other voltage levels are generated by the proper switching between the proper switching between the the
switches. Table 1 shows the switching table for generating each
switches. Table 1 shows the switching table for generating each output voltage level. The generalized output voltage level. The
generalized formulas for generating the output voltage level, maximum step output voltage, and the
formulas for generating the output voltage level, maximum step output voltage, and the required
required number of devices and DC source are discussed below.
number of devices and DC source are discussed below.

S1
D1
+

2VDC
_
S2
A1 D2 Db1
Da1
B1

S3
D3 A2
B2 Da2
+ VDC Db2

S4
D4

LOAD

Vout

Figure 1. 1.Single
Figure Singlephase
phaseasymmetric seven-level
asymmetric seven-level inverter.
inverter.

3
Energies 2018, 11, 2148 4 of 18

 
Maximum step of output voltage St = 2 j − 1 Number of DC source j = (1, 2, 3 . . . n) (1)
 
Maximum level of output voltage M = 2( j+1) − 1 (2)

Maximum number of switches and driver circuit required = 2j + 4 (3)

 
Magnitude of DC source Vdc,j = 2( j−1) Vdc (4)
 
Magnitude of maximum output voltage Vout,max = 2 j − 1 Vdc (or) (5)

Vout,max = ( P − 1)Vdc where P = 2 j (6)

Table 1. Switching states for reduced switch multilevel inverter (MLI).

S1 S2 S3 S4 A1 A2 B1 B2 Output Level (Vout )

1 0 0 1 1 1 0 0 +3 Vdc
1 0 1 0 1 1 0 0 +2 Vdc
0 1 0 1 1 1 0 0 +1 Vdc
0 1 1 0 1 1 0 0 0
0 1 0 1 0 0 1 1 −1 Vdc
1 0 1 0 0 0 1 1 −2 Vdc
1 0 0 1 0 0 1 1 −3 Vdc

3. Modulation Strategies for Asymmetrical Multilevel Inverters

MLIs offer several advantages, but the control strategies are quite challenging due to the
complexity of generating the voltage level transition (or steps) [21]. Many PWM strategies are used in
MLIs for different applications [22]. The PWM techniques are usually employed in MLIs, which can
be classified into three main categories: (1) multi-step, fundamental frequency or staircase switching
strategies, (2) space vector PWM strategies, and (3) carrier-based PWM strategies [23]. The first
category needs pre-calculated switching angles for generating the PWM signals [23]. The space
vector method will be very complicated for more than five output voltage levels due to increases in
switching states [24]. The carrier-based PWM methods are simple to use when the number of output
levels is more than five [25,26]. Therefore, the carrier-based PWM method is preferred in this work.
The carrier-based PWM is categorized into three groups: (i) carrier disposition methods where the
reference signal is sampled through the number of carrier signals displaced by increments of the
reference amplitude, (ii) phase shift PWM methods where the multiple carriers are phase shifted
accordingly, and (iii) a combination of carrier disposition and phase shift methods. Control freedom
degree (CFD) exists to design the carriers in multi-carrier PWM strategies [27]. These strategies
have more than one carrier option, which can be triangular, sawtooth, and some new function, etc.
The modulating wave can be a sinusoidal or an advanced reference signal. The CFD technique is
used to determine the carrier type and its frequency, amplitude, the phase of each carrier, and the
offset between carriers. The multi-carrier PWM strategies can also be categorized into two types:
multi-carrier bipolar PWM (MCBPWM) strategies and multi-carrier unipolar PWM (MCUPWM)
strategies. In this work, the unipolar MCPWM strategy is selected for making quality output voltage.
In the unipolar strategy, the reference wave may be a rectified reference wave or two reference waves
with a 180-degree phase shift. The multi-carrier is positioned above the zero level. For the unipolar
multi-carrier technique, the M-level inverter requires (M-1)/2 carriers with the same frequency fc and
same peak-to-peak amplitude Ac . The reference wave has the amplitude Am and frequency fm and
it is placed at the zero reference. The different MCUPWM strategies, such as PDPWM, APODPWM,
COPWM, and VFPWM, are utilized [8]. The carrier arrangement for the PDPWM strategy with
Energies 2018, 11, 2148 5 of 18

unipolar trapezoidal reference is shown in Figure 2. The carriers of the same frequency and same
Energies 2018,
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2018, 11
peak-to-peak amplitude are placed so that the bands they occupy are contiguous [28,29]. The carrier set
Energies 2018, 11
is placed above the zero reference [28]. In the APODPWM strategy, the carriers of the same amplitude
eachsame
carrier is out of are
phase with itsinneighbor by 180 that
degrees.
each Figure
carrier 33isshows
out of the carrier
witharrangement
each carrier
and is out of phase
frequency with its neighbor
arranged by 180 degrees.
such a manner Figure shows the carrier
phase arrangement
its neighbor
for the APODPWM strategy [9]. The principle of COPWM is used to overlap the carriers with a
for
by themodulating
180
single APODPWM
degrees. Figure strategy
3
signal. The [9].
shows the The having
principle
carrier
carriers theofsame
arrangementCOPWM
for the is used
andto
APODPWM
frequency sameoverlap the carriers
strategy [9].
peak-to-peak
The with a
principle
amplitude
single modulating signal. The carriers having the same frequency and same peak-to-peak amplitude
of COPWM is used to overlap the carriers with a single modulating signal. The carriers having the
are placed such andthatsame
the bands they occupy overlap each other [8], astheillustrated in Figure 4.overlap
In the
are
same
VFPWMplacedstrategy,
such that
frequency the bands
varying they occupy
peak-to-peak
the carrier overlap
amplitude
frequency
are
based each
on other
placed such [8], as
the slope
that illustrated
of the
bands in Figure
they
modulating wave4.inIneach
occupy the
VFPWM
each otherstrategy, varying
[8], as illustrated the carrier
in Figure
band is represented in Figure 5. Positioned frequency
4. based
In the VFPWM on the slope
strategy, of
varying the modulating
the wave
carrier frequency in each
based
band
on theisslope
represented in Figure 5.wave
of the modulating Positioned
in each band is represented in Figure 5. Positioned.
3
3
volts
volts
volts

2
in

2
Amplitude
Amplitude
Amplitude inin

1
1

0
00 0.005 0.01 0.015 0.02
0 0.005 0.01
Time in seconds 0.015 0.02
Time in seconds
Figure 2. Carrier arrangement for the PDPWM strategy.
Figure 2.
Figure Carrier arrangement
2. Carrier arrangement for
for the
the PDPWM
PDPWM strategy.
strategy.

3
3
volts
volts
volts

2
in

2
Amplitude
Amplitude
Amplitude inin

1
1

00
0 0.005 0.01 0.015 0.02
0 0.005 Time0.01
in secs 0.015 0.02
Time in secs
Figure
Figure 3.
3. Carrier
Carrier arrangement
arrangement for
for the
the APODPWM
APODPWM strategy.
strategy.
Figure 3. Carrier arrangement for the APODPWM strategy.

3
3
volts
volts
volts
in

2
inin

2
Amplitude
Amplitude
Amplitude

1
1

00
0 0.005 0.01 0.015 0.02
0 0.005 Time0.01
in secs 0.015 0.02
Time in secs
Figure 4.
Figure 4. Carrier
Carrier arrangement for the
arrangement for the COPWM
COPWM strategy.
strategy.
Figure 4. Carrier arrangement for the COPWM strategy.
 Energies 2018, 11, 2148 6 of 18
Energies 2018, 11

Energies 2018, 11
3
3

Amplitude in volts
Amplitude in volts 2
2

1
1

0
0 0.005 0.01 0.015 0.02
0 Time in secs
0 0.005 0.01 0.015 0.02
Figure 5. 5.
Figure Carrier
Carrierarrangement
Time in forthe
secs
arrangement for theVFPWM
VFPWM strategy.
strategy.
Figure 5. Carrier arrangement for the VFPWM strategy.
The main challenge
The main challenge is is to
to reduce
reduce the the switching
switching losses losses of
of the
the inverter
inverter by by reducing
reducing the the switching
switching
frequency
The main of
frequency
of the higher
challenge
the higher
power
is to power
reduce the cells.
cells.
Therefore,
switching
Therefore, lossesinstead of
of theof
instead
using MCUPWM
inverter
using by
MCUPWM
reducing the (high-frequency
switching
(high-frequency
carrier-based
frequency of the PWM)
higher strategies
powerincells. in all the cells, the high-power cells are operated by a square
carrier-based PWM) strategies all theTherefore, instead of cells
cells, the high-power using areMCUPWM
operated by (high-frequency
a square waveform
waveform
carrier-based pattern
PWM) at
pattern switched switched
strategies at low
in all the
low frequency. frequency.
Thus, cells, Thus,
thethe the combination
high-powerofcells
combination of
MCUPWM MCUPWM
are operated
(high by(high a frequency)
frequency)squareand
and
waveform fundamental
pattern
fundamental
frequency
switched(low
frequency at low (low frequency)
frequency.
frequency)
switching
Thus, themodulation
switching
modulation
combination strategies
of MCUPWM
strategies
was selected
(high frequency)
was selected
in this
in this paper.
paper. In
andInfundamental Figures 2–5,
frequency it is noticed that the three triangular carriers and a unipolar trapezoidal
Figures 2–5, it is noticed(low that frequency)
the three triangularswitchingcarriersmodulation strategiestrapezoidal
and a unipolar was selected in thisare
reference
reference
paper. are used to generate the switching pulses. The unipolar trapezoidal wave is continuously
usedInto Figures
generate2–5, it is noticed
the switching that The
pulses. the unipolar
three triangular
trapezoidalcarriers
wave and a unipolar compared
is continuously trapezoidal with
compared
reference
triangular with
are used triangular
to generate
carriers carriers
and generates andBoolean
the switching
the generates
pulses. the
TheBoolean
outputs. unipolaroutputs. The
trapezoidal
The outputs of eachoutputs
wave
carrierisofcontinuously
each
are carrier are
represented
represented
compared
by Pw1with
by Pw1
triangular
to Pw3.
tocarriers
By using
Pw3. By
andusing
the logical generatesthe the
expression
logical expression
Boolean outputs.
with Boolean
with
The Boolean
outputs outputs
based on
outputs
of each basedare
carrier
a switching
on a
table,
switchingby
represented table,
Pw1thetopulses
required
Pw3.are ByPWM usingpulses
the for are generated
logical expressionfor the
with respective
Boolean switches
outputs to
basedgenerate
on athe
the required PWM generated the respective switches to generate the desired output
desired
switching output levels.
table,logical
the required The logical
PWM expression for all switches is given in Equation (7). The switches A1
levels. The expression forpulses are generated
all switches is givenfor the respective
in Equation switches
(7). The switches to generate
A1 and A the
2 are
and
desired A 2 are triggered on when the reference wave is greater than or equal to zero and B1 and B2 are
output
triggered onlevels.
when The logical expression
the reference wave is greaterfor all switches is given
than or equal in Equation
to zero and B1 and (7). The
B2 are switches A1 on
triggered
triggered
andwhen
A2 are on when the reference wave is less than or equal to zero. Figure 6 shows the graphical
thetriggered
referenceon when
wave the than
is less reference
or equalwave to is greater
zero. than
Figure or equal
6 shows theto zero andrepresentation
graphical B 1 and B2 are for
representation
triggered on when for
thegenerating
reference the switching pulses toequal
get the
to desired output.
generating the switching pulseswave to getisthelessdesired
than or
output. zero. Figure 6 shows the graphical
representation for generating the switching pulses 𝑆𝑆1 = 𝑃𝑃𝑃𝑃2
to get the desired output.
⎛

𝑆𝑆 ������
=S1𝑃𝑃𝑃𝑃2
= Pw2 ⎞

𝑆1 =2𝑃𝑤2
⎜𝑆𝑆 (7)
4 = �(𝑃𝑃𝑃𝑃1
𝑆2 = h ̅̅̅̅̅̅
𝑃𝑤2 = Pw2
⊕S2𝑃𝑃𝑃𝑃2) ⊕ 𝑃𝑃𝑃𝑃3�⎟ i 

(7) (7)

𝑆𝑆 =S4[(𝑃𝑃𝑃𝑃1
=⊕( 𝑃𝑤2)Pw1 ⊕⊕Pw2
⊕ 𝑃𝑃𝑃𝑃2) ⊕ Pw3
⊕)𝑃𝑃𝑃𝑃3]
 
𝑆4⎝= 3[(𝑃𝑤1 𝑃𝑤3] ⎠

S3 = [( Pw1 ⊕ Pw2) ⊕ Pw3]
(𝑆3 = [(𝑃𝑤1 ⊕ 𝑃𝑤2) ⊕ 𝑃𝑤3] )
Pw1 S2
S
S2 1
Carrier Pw1
Pw2 S1
Carrier S4
Carrier Pw2
S 4 S3
Carrier
Carrier Pw3
S3
Carrier ≥0 A1,A2 Pw3
abs
≥0 A1,A2
abs <0 B1,B2
Reference signal
(Trapezoidal) < 0 B1,B2
Reference signal
(Trapezoidal)
Figure 6. Logic circuits for pulse width modulation (PWM) generation.
Figure
Figure 6. Logic
6. Logic circuits
circuits for pulse
for pulse width
width modulation
modulation (PWM)
(PWM) generation.
generation.
4. Numerical Simulation Results
A single-phase
4. Numerical reduced
Simulation Resultsswitch AMLI was modeled in Matlab/Simulink (2009a) to generate the
seven-level output
A single-phase voltageswitch
reduced by using
AMLI a power system in
was modeled block set. Switching(2009a)
Matlab/Simulink signalstowere developed
generate the
using different multi-carrier unipolar PWM strategies as discussed in the previous
seven-level output voltage by using a power system block set. Switching signals were developed section. Different
parameters
using different such as Vdc1 = 6unipolar
multi-carrier V, Vdc2 =PWM
12 V, RL(load)
strategies=as
100 Ω, 100 mH,
discussed fc =previous
in the 2000 Hz,section.
and fm =Different
50 Hz were
6 Ω, 100 mH, fc = 2000 Hz, and fm = 50 Hz were
parameters such as Vdc1 = 6 V, Vdc2 = 12 V, RL(load) = 100
6
Energies 2018, 11, 2148 7 of 18

4. Numerical Simulation Results

A single-phase reduced switch AMLI was modeled in Matlab/Simulink (2009a) to generate
the seven-level output voltage by using a power system block set. Switching signals were
developed
Energies 2018, using
11 different multi-carrier unipolar PWM strategies as discussed in the previous section.
Different parameters such as Vdc1 = 6 V, Vdc2 = 12 V, RL(load) = 100 Ω, 100 mH, fc = 2000 Hz,
utilized
and fm = for 50 Hzsimulation to evaluate
were utilized the selected
for simulation to evaluate topology for the
the selected required
topology output
for the voltage.
required outputA
simulation
voltage. model wasmodel
A simulation examined for different
was examined PWM strategies
for different with various
PWM strategies modulation
with various indices
modulation
ranging from 0.8–1.
indices ranging fromThe % Total
0.8–1. The %Harmonic Distortion
Total Harmonic (THD),(THD),
Distortion fundamental root mean
fundamental root square (VRMS)
mean square
values,
(V RMS ) and
values,% distortion
and % factor
distortion (DF)
factorfor the
(DF) output
for the voltage
output with
voltage various
with modulation
various indices
modulation were
indices
measured
were measuredand tabulated. Here,
and tabulated. all the
Here, results
all the resultsareare
displayed
displayed with
withdifferent
differentPWMPWMstrategies
strategies atat the
the
modulation
modulation index indexofof0.9.
0.9. Figure
Figure 7a–b7a–b
showsshows the seven-level
the seven-level output output
voltage voltage waveform
waveform and theand the
current
current waveform
waveform generated generated by the PDPWM
by the PDPWM strategy andstrategy andFourier
its fast its fasttransform
Fourier transform
(FFT) plot(FFT) plot in
is shown is
shown
Figure 8. in The
Figure 8. The
value value is
of %THD of 21.51%.
%THD is 21.51%.
Figure 9a–bFigure
shows 9a–b
the shows the seven-level
seven-level output
output voltage voltage
waveform
waveform
and the currentand waveform
the current waveform
generated generated
by the APODPWM by the APODPWM
strategy strategy
and its FFT plot isand
shownits in
FFT plot 10.
Figure is
shown
The value in of
Figure
%THD 10.isThe value
21.03%. of %THD
Figure is 21.03%.
11a–b shows Figure 11a–b
the seven-level shows
output the seven-level
voltage waveform and output
the
voltage waveformgenerated
current waveform and the current waveformstrategy
by the COPWM generatedandbyits the
FFTCOPWM strategy
plot is shown and its
in Figure 12.FFT
Theplot
valueis
shown
of %THD in is
Figure 12.Figure
25.63%. The value
13a–bofshows
%THD theisseven-level
25.63%. Figureoutput 13a–b shows
voltage the seven-level
waveform output
and the current
voltage waveform
waveform generatedandbythethecurrent
VFPWM waveform
strategygenerated
and its FFT byplot
the VFPWM
is shownstrategy
in Figure and
14.its FFT
The plot of
value is
shown is
%THD in 20.06%.
Figure 14. The value of %THD is 20.06%.

(a)

(b)
Figure
Figure 7.
7. Output
Output waveform
waveform for
for the
the PDPWM
PDPWM strategy.
strategy. (a)
(a) Voltage; (b) Current.
Voltage; (b) Current.

Fundamental (50Hz) = 17.01 , THD= 21.51%

100
Mag (% of Fundamental)

80 30

60 20

10
40
0
20 0 50 100 150 200

0
0 50 100 150 200
 (b)
Energies 2018, 11, 2148 8 of 18
Figure 7. Output waveform for the PDPWM strategy. (a) Voltage; (b) Current.

Fundamental (50Hz) = 17.01 , THD= 21.51%

100

Mag (% of Fundamental)
80 30

60 20

10
40
0
20 0 50 100 150 200

0
0 50 100 150 200
Harmonic order

Figure11 8. Fast Fourier transform (FFT) plot for the output voltage of the PDPWM strategy.
Figure
Energies 2018,
8. Fast Fourier transform (FFT) plot for the output voltage of the PDPWM strategy.

7
20
Voltage in volts

10

-10

-20
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(a)
0.2
Current in Amps

0.1

-0.1

-0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)
Figure
Figure 9. Output
9. Output waveform
waveform forfor
thethe APODPWM
APODPWM strategy.
strategy. (a)(a) Voltage;
Voltage; (b)(b) Current.
Current.

Fundamental (50Hz) = 17.05 , THD= 21.03%

100
Mag (% of Fundamental)

80 30
60 20

40 10

20 0
0 50 100 150 200
0
0 50 100 150 200
Harmonic order

Figure 10. FFT plot for the output voltage of the APODPWM strategy.
 -0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)
Energies 2018, 11, 2148 9 of 18
Figure 9. Output waveform for the APODPWM strategy. (a) Voltage; (b) Current.

Fundamental (50Hz) = 17.05 , THD= 21.03%

100

Mag (% of Fundamental)
80 30
60 20

40 10

20 0
0 50 100 150 200
0
0 50 100 150 200
Harmonic order

Energies 2018, 11 Figure 10. FFT plot for the output voltage of the APODPWM strategy.
Figure 10. FFT plot for the output voltage of the APODPWM strategy.

20
Voltage in volts

10

-10

-20
0 0.02 0.04 0.06 0.08 0.1
Time in secs

(a)
0.2 8
Current in Amps

0.1

-0.1

-0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)

Figure
Figure 11.
11. Output
Output waveform
waveform for
for the
the COPWM
COPWM strategy. (a) Voltage;
strategy. (a) Voltage; (b)
(b) Current.
Current.

Fundamental (50Hz) = 17.74 , THD= 25.63%

100
Mag (% of Fundamental)

80 30

60 20

40 10

20 0
0 50 100 150 200
0
0 50 100 150 200
Harmonic order

Figure 12. FFT plot for the output voltage of the COPWM strategy.
 -0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)
Energies 2018, 11, 2148 10 of 18
Figure 11. Output waveform for the COPWM strategy. (a) Voltage; (b) Current.

Fundamental (50Hz) = 17.74 , THD= 25.63%

100

Mag (% of Fundamental)
80 30

60 20

40 10

20 0
0 50 100 150 200
0
0 50 100 150 200
Harmonic order

Energies 2018, 11 Figure

Figure 12.
12. FFT
FFT plot
plot for
for the
the output
output voltage
voltage of
of the
the COPWM
COPWM strategy.
strategy.

20
Voltage in volts

10

-10

-20
0 0.02 0.04 0.06 0.08 0.1
9 in secs
Time
(a)
0.2
Current in Amps

0.1

-0.1

-0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)

Figure
Figure 13.
13. Output
Output waveform
waveform for
for the
the VFPWM
VFPWM strategy. (a) Voltage;
strategy. (a) Voltage; (b)
(b) Current.
Current.

Fundamental (50Hz) = 17.15 , THD= 20.06%

100
Mag (% of Fundamental)

80 30
60 20

40 10
0
20 0 50 100 150 200

0
0 50 100 150 200
Harmonic order
 -0.2
0 0.02 0.04 0.06 0.08 0.1
Time in secs
(b)
Energies 2018, 11, 2148 11 of 18
Figure 13. Output waveform for the VFPWM strategy. (a) Voltage; (b) Current.

Fundamental (50Hz) = 17.15 , THD= 20.06%

100

Mag (% of Fundamental)
80 30
60 20

40 10
0
20 0 50 100 150 200

0
0 50 100 150 200
Harmonic order

Figure 14. FFT plot for the output voltage of the VFPWM strategy.
Figure 14. FFT plot for the output voltage of the VFPWM strategy.

Table 2. %THD for different modulation indices.

Table 2. %THD for different modulation indices.
Simulation Results Experimental Results
ma PD APOD
Simulation CO
Results VF PD APOD
Experimental CO
Results VF
1 ma 15.33 PD 15.78
APOD 21.11
CO 14.51
VF 16.5
PD 16.8
APOD CO21.7 VF14.8
0.95 1 19.1315.33 15.78
19.09 21.11
23.56 14.51
17.96 16.5
20.0 16.8
19.4 21.7
23.8 14.8
18.2
0.95 19.13 19.09 23.56 17.96 20.0 19.4 23.8 18.2
0.9 21.51 21.03 25.63 20.06 21.6 21.5 25.8 21.2
0.9 21.51 21.03 25.63 20.06 21.6 21.5 25.8 21.2
0.850.85 23.5323.53 23.44
23.44 28.33
28.33 23.18
23.18 23.8
23.8 2424 28.7
28.7 23.8
23.8
0.8 0.8 24.7024.70 24.84
24.84 30.46
30.46 25.26
25.26 24.9
24.9 25.1
25.1 3131 25.6
25.6

10 modulation indices.
Table 3. VRMS for different

Simulation Results Experimental Results

ma PD APOD CO VF PD APOD CO VF
1 12.734 12.8 13.54 13.36 13.1 13.0 13.7 13.5
0.95 12.72 12.72 13.03 12.75 12.9 12.8 13.2 12.8
0.9 12.03 12.06 12.54 12.13 12.1 12.3 12.9 12.4
0.85 11.37 11.36 11.88 11.42 11.7 11.6 12.0 11.8
0.8 10.72 10.69 11.32 10.71 10.9 10.8 11.5 10.9

Table 4. %Distortion factor for different modulation indices.

Simulation Results Experimental Results

ma PD APOD CO VF PD APOD CO VF
1 0.1798209 0.1747 0.3098 0.2333 0.181 0.183 0.291 0.272
0.95 0.1719129 0.1714 0.3401 0.2119 0.180 0.181 0.311 0.217
0.9 0.1564152 0.1716 0.4262 0.2092 0.160 0.178 0.399 0.210
0.85 0.1612577 0.1698 0.5707 0.1892 0.165 0.171 0.491 0.191
0.8 0.1783759 0.1681 0.7031 0.1539 0.181 0.170 0.575 0.165

The %THD comparison of the output voltage for different PWM switching strategies with various
modulation indices is shown in Table 2 and the corresponding graphical representation is shown in
Figure 15a. The %THD depends on the range of switching frequencies. The frequency modulation
index mf is defined as the ratio between the frequencies of the carrier fcr and modulating wave fm .
When mf is a small number (i.e., less than 21), its output spectrum contains low-frequency harmonics
(sub-harmonics) causing high currents in transformers and inductors. Note that in the case of mf
being a large number, the amplitudes of the sub-harmonics are highly reduced and do not pose
critical problems with the currents by inductors and transformers [6]. Therefore, the selected topology
Energies 2018, 11, 2148 12 of 18

generates low order harmonics with the obtained high frequency, but the order harmonic values have
considerable limits, i.e., within the IEEE 519 standard. Hence, low order harmonics do not affect
the system. From Figure 15a and Table 2, it is observed that the harmonic content of the output
voltage is lower for the VFPWM strategy than the other strategies. The RMS comparison of the
output voltage for different PWM switching strategies with various modulation indices is shown in
Table 3 and the corresponding graphical representation is shown in Figure 15b. From Table 3 and
Figure 15b, it is observed that the CO strategy provides the highest DC bus utilization compared
with the other strategies. The %DF comparison of the output voltage for different PWM switching
strategies with various modulation indices is shown in Table 4 and the corresponding graphical
representation is shown in Figure 15c. It is further visualized from Table 4 and Figure 15c that the
VFPWM strategy has relatively lower harmonics after second order attenuation, indicated by the
%DF. Figure 15d shows the harmonic content (amplitude values) for individual harmonic order. From
Figure 15d, it is noted that the lower and upper sidebands (mf ± 1 and 2mf ± 1) appear in all strategies.
In addition, the third-order harmonic is not dominant in all strategies. Harmonics corresponding to
the center frequency mf , 2mf are minimum in all strategies. It is observed that the significant number
of harmonics is avail by the VFPWM strategy using a trapezoidal reference carrier from the presented
numerical
Energies 2018,results.
11

30 14 PD
APOD
CO
Fundamental RM S voltage

12 VF
25

10
20
% (T HD)

8
15 PD
APOD 6
10 CO
VF 4
5
2
0
0.80 0.85 0.90 0.95 1.00 0
0.80 0.85 0.90 0.95 1.00
M odulation indices M odulation indices
(a) (b)
1.0
14

0.8
PD 12 PD
APOD APOD
% (Harmonic Magnitude)
Distortion Factor

CO 10 CO
0.6 VF VF
8

0.4 6

4
0.2
2

0.0 0
0.80 0.85 0.90 0.95 1.00 0 5 10 15 20 25 30 35 40
M odulation indices Harmonic Order
(c) (d)
Figure
Figure 15.
15. Different
Differentparameters
parametersfor
fordifferent
differentmodulation
modulationindices byby
indices simulation results:
simulation (a) %THD;
results: (b)
(a) %THD;
VRMS; (c) %DF; (d) %Harmonic content for different harmonic orders.
(b) V ; (c) %DF; (d) %Harmonic content for different harmonic orders.
RMS

5. Implementation of Reduced Switch AMLI Using FPGA for Experimental Results

This section describes the experimental results for reduced switch asymmetric multilevel to
examine seven-level output voltage using the SPARTAN-3 FPGA system. FPGA was used for
real-time implementation, which usually includes an on-chip PWM controller to reduce the
complexity of PWM signal generation. Multi-carrier PWM strategies with a unipolar trapezoidal
reference were used for generating the PWM signal to the selected topology. The simulation part
Energies 2018, 11, 2148 13 of 18

5. Implementation of Reduced Switch AMLI Using FPGA for Experimental Results

This section describes the experimental results for reduced switch asymmetric multilevel to
examine seven-level output voltage using the SPARTAN-3 FPGA system. FPGA was used for real-time
implementation, which usually includes an on-chip PWM controller to reduce the complexity of PWM
signal generation. Multi-carrier PWM strategies with a unipolar trapezoidal reference were used
for generating the PWM signal to the selected topology. The simulation part was implemented in
Matlab/Simulink (2009a) ((PWM signal generation)) and converted into an input signal of FPGA
through the Xilinx software (compiled and converted into bits and then downloaded into FPGA for
execution in the real-time process). Figure 16 depicts the laboratory-based experimental setup for
reduced switch AMLI. The experimental setup consists of power converter module MLI and gate
terminals are trigger through FPGA digital processor and is programme through Xilinx software.
The hardware parameters includes the voltage value of the DC sources Vdc1 = 6 V and Vdc2 = 12 V,
the load11values are 100 Ω, 100 mH, and the switching carrier frequency (fc ) as 2000 Hz.
RL 2018,
Energies

DSO
Power Quality Analyzer
Reduced switch AMLI topology
DC sources
Computer with xilinx software
FPGA Board

Figure
Figure 16.
16. Laboratory-based
Laboratory-based experimental
experimental setup
setup for
for asymmetric
asymmetric reduced
reduced switch multilevel inverter.
switch multilevel inverter.

Figures 17–20 represent the experimental output voltage, output current waveform and its
Figures 17–20 represent the experimental output voltage, output current waveform and its
corresponding voltage FFT plot for PDPWM, APODPWM, COPWM, and VFPWM strategies. All
corresponding voltage FFT plot for PDPWM, APODPWM, COPWM, and VFPWM strategies.
output waveforms are portrayed for ma = 0.9. From Figures 17a–20a, it is observed that the
All output waveforms are portrayed for ma = 0.9. From Figures 17a, 18a, 19a and 20a, it is observed
peak-to-peak output voltage is 36 V, which is identical to the simulation results. An amplitude of
that the peak-to-peak output voltage is 36 V, which is identical to the simulation results. An amplitude
each level is 6 V. From Figures 17b–20b, it is evident that the experimental and simulation output
of each level is 6 V. From Figures 17b, 18b, 19b and 20b, it is evident that the experimental and
currents are identical. The %THD values for different strategies are observed in Figures 17c–20c. The
simulation output currents are identical. The %THD values for different strategies are observed in
value of %THD for PD, APOD, CO, and VF PWM are 21.6%, 21.5%, 25.8%, and 17.3%, respectively.
Figures 17c, 18c, 19c and 20c. The value of %THD for PD, APOD, CO, and VF PWM are 21.6%, 21.5%,
Table 2 and Figure 21a show the comparison results of the %THD output voltage with various
25.8%, and 17.3%, respectively. Table 2 and Figure 21a show the comparison results of the %THD
modulation indices for different PWM strategies. Table 3 and Figure 21b show the comparison
output voltage with various modulation indices for different PWM strategies. Table 3 and Figure 21b
results of the VRMS output voltage with various modulation indices for different PWM strategies.
show the comparison results of the VRMS output voltage with various modulation indices for different
Table 4 and Figure 21c show the comparison of the %DF output voltage with various modulation
PWM strategies. Table 4 and Figure 21c show the comparison of the %DF output voltage with various
indices for different PWM strategies. From the results and comparison table, it is evident that the
modulation indices for different PWM strategies. From the results and comparison table, it is evident
harmonic content of the output voltage is comparatively lower for the VFPWM strategy and the VRMS
that the harmonic content of the output voltage is comparatively lower for the VFPWM strategy and
output voltage for the COPWM strategy is higher than the other PWM strategies. In addition, from
the VRMS output voltage for the COPWM strategy is higher than the other PWM strategies. In addition,
the results, the %DF is lower in the PDPWM strategy than the other PWM strategies.
from the results, the %DF is lower in the PDPWM strategy than the other PWM strategies.
 modulation indices for different PWM strategies. Table 3 and Figure 21b show the comparison
results of the VRMS output voltage with various modulation indices for different PWM strategies.
Table 4 and Figure 21c show the comparison of the %DF output voltage with various modulation
indices for different PWM strategies. From the results and comparison table, it is evident that the
harmonic content of the output voltage is comparatively lower for the VFPWM strategy and the VRMS
output
Energies voltage
2018, 11, 2148 for the COPWM strategy is higher than the other PWM strategies. In addition, from
14 of 18
the results, the %DF is lower in the PDPWM strategy than the other PWM strategies.

Energies 2018, 11
Energies 2018, 11 (a) (b)

(c)
13
(c)
Figure 17. Experimental output waveform for the PDPWM strategy. (a) Voltage; (b) Current; (c) FFT
Figure 17. Experimental output waveform for the PDPWM strategy. (a) Voltage; (b) Current;
Figure
plot for17.
theExperimental output waveform for the PDPWM strategy. (a) Voltage; (b) Current; (c) FFT
output voltage.
(c) FFT plot for the output voltage.
plot for the output voltage.

(a) (b)
(a) (b)

(c)
(c)
Figure 18. Experimental output waveform for the APODPWM strategy. (a) Voltage; (b) Current; (c)
Figure 18.for
FFT plot Experimental output waveform for the APODPWM strategy. (a) Voltage; (b) Current; (c)
the output voltage.
Figure 18. Experimental output waveform for the APODPWM strategy. (a) Voltage; (b) Current;
FFT plot for the output voltage.
(c) FFT plot for the output voltage.
 (c)
EnergiesFigure 18.2148
2018, 11, Experimental output waveform for the APODPWM strategy. (a) Voltage; (b) Current; (c)
15 of 18
FFT plot for the output voltage.

Energies 2018, 11
Energies 2018, 11
(a) (b)
14

(c)
(c)
Figure
Figure 19. 19. Experimental
Experimental output
output waveform
waveform forfor
thethe COPWM
COPWM strategy.
strategy. (a) (a) Voltage;
Voltage; (b) (b) Current;
Current; (c) (c)
FFTFFT
Figure
plot 19. the
for Experimental
output output waveform for the COPWM strategy. (a) Voltage; (b) Current; (c) FFT
voltage.
plot for the output voltage.
plot for the output voltage.

(a) (b)
(a) (b)

(c)
(c)
Figure 20. Experimental output waveform for the VFPWM strategy. (a) Voltage; (b) Current; (c) FFT
Figure 20.Experimental
plot 20.
Figure for Experimental
the output waveform
output voltage.
output waveformfor
forthe
theVFPWM
VFPWM strategy.
strategy.(a)
(a)Voltage;
Voltage;(b)
(b)Current;
Current;(c)
(c)FFT
FFT
plot for the output voltage.
plot for the output voltage.
Energies 2018, 11, 2148 16 of 18
Energies 2018, 11

30

25 14 PD
APOD
CO
12
% (THD)

VF
20

Fundamental RMS voltage

10
15
PD 8
APOD
10 6
CO
VF
5 4

2
0
0.80 0.85 0.90 0.95 1.00 0
0.80 0.85 0.90 0.95 1.00
Modulation indices Modulation indices

(a) (b)
1.0
PD
APOD
0.8 CO
Distortion Factor

VF
0.6

0.4

0.2

0.0
0.80 0.85 0.90 0.95 1.00
Modulation indices
(c)
Figure 21. Different
Figure 21. Differentparameters
parameters for different
for different modulation
modulation indicesindices using experimental
using experimental results: (a)results:
%THD;
(a) %THD;
(b) V (b) VRMS; (c) %DF.
; (c) %DF.
RMS

6. Conclusions
6. Conclusions
Asymmetric MLIs produce a higher output voltage level than symmetric MLIs. The selected
Asymmetric MLIs produce a higher output voltage level than symmetric MLIs. The selected
reduced switch asymmetric MLI requires fewer components than conventional MLI topologies such
reduced switch asymmetric MLI requires fewer components than conventional MLI topologies such
as DCMLI and FCMLI. It requires only eight switches for generating the seven-level output voltage.
as DCMLI and FCMLI. It requires only eight switches for generating the seven-level output voltage.
The working principle of the selected topology and its mathematical expressions with respect to the
The working principle of the selected topology and its mathematical expressions with respect to the
maximum possible steps, the level of an output voltage, the magnitude value of the DC source, and
maximum possible steps, the level of an output voltage, the magnitude value of the DC source, and the
the magnitude value of the maximum output voltage have been discussed. The sub-multilevel
magnitude value of the maximum output voltage have been discussed. The sub-multilevel inverter of
inverter of the reduced switch topology operated at a higher switching frequency whereas the H
the reduced switch topology operated at a higher switching frequency whereas the H bridge operated
bridge operated at the fundamental switching frequency. The topology was examined with the
at the fundamental switching frequency. The topology was examined with the different multi-carrier
different multi-carrier unipolar trapezoidal PWM strategies, such as PDPWM, APODPWM,
unipolar trapezoidal PWM strategies, such as PDPWM, APODPWM, COPWM, and VFPWM for
COPWM, and VFPWM for generating the seven-level output voltage. By using the unipolar method,
generating the seven-level output voltage. By using the unipolar method, the carrier count was
the carrier count was reduced by half compared with the conventional PWM method. The logic
reduced by half compared with the conventional PWM method. The logic diagram for generating
diagram for generating the switching pulses for the topology has been presented. The topology was
the switching pulses for the topology has been presented. The topology was examined with different
examined with different modulation index values from 0.8 to 1 for checking the potential of the
reduced switch topology. It was designed using Matlab/Simulink (2009b) and implemented using

16
Energies 2018, 11, 2148 17 of 18

modulation index values from 0.8 to 1 for checking the potential of the reduced switch topology. It was
designed using Matlab/Simulink (2009b) and implemented using the SPARTAN-3 FPGA system for
the laboratory-based experimental results. Various performance parameters such as %THD, VRMS ,
and %DF were evaluated for different strategies and compared with each other. From the results
and discussion, it is evident that the VFPWM strategy produces less harmonic content than the other
strategies. The COPWM strategy provides higher VRMS than the other strategies. The simulation and
experimental results were found to be satisfactory.

Author Contributions: All authors contributed to the research investigation equally and presented in the current
version of the full article.
Funding: There is no funding resources for the presented research work.
Conflicts of Interest: The authors declare no conflict of interest.

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