Chapter One

Processing unit & I/O Organization

This chapter covers basic characteristics of uni-processor. It discusses the CPU
structure, data movement within a CPU chip, I/O organisation interfacing with
external world. The differences between single bus CPU and dual-bus CPU will be
presented. The control gates within a CPU can be controlled by either a hardwired
control unit or Microprogrammed Control unit. The former control unit is static
and cannot be programmable by ordinary users. The design in CPU is then
followed to take the heat dissipation as one of the factors. That is why for high
speed CPU chip, an internal FAN is used to remove the heat generated. Another
factor to take into account is the CPU size when the number of buses increases as
the CPU power increases. On completion of this chapter, students should
understand  

Single and Two bus structure

Different Control Units - hardwired and programmable
Different I/O methods and CPU chip design

Terminology

Term

Description

ALU

Arithmetic Logic Unit

MAR

Memory Address Register

MDR

Memory Data Register

Memory mapped I/O

Treat Input/Output device as a memory location and uses the equivalent command
to execute data movement.

PC
Programme Counter used to keep track the location of programme

PDP11

Manufactured by Digital Computer, very old computer model

[R1]

Content of Register 1

R2 <- [R1]

Transfer of data in R1 to R2

Virtual Memory

An operating system, which uses limited memory storage to execute a programme

that is larger than the working memory. Win3.1, Win95, Win98 and Unix uses this
approach.

Output Register

The processing Unit

Figure is a flowchart showing the steps required to generate an executable machine

codes from a high-level language. Computer executes each individual machine
instruction by carrying out a sequence of operations.  The organization and
operation of the different building blocks that comprise the computer hardware and
the control sequence for instruction execution is shown in Figure . It is a single-bus
organization of data paths inside the CPU. The rudimentary (rudimentary means
basic) operations performed by the CPU are:

Fetch data of specific memory location and load them into a CPU register
Store the data from a CPU register into a specific memory location
Transfer data from one CPU register to another register
Perform an arithmetic or logic operation and store the result in a CPU register

Fetching a word from memory

The example below demonstrates how to fetch a word from memory location,
whose address is specified in R1, and place the word fetched in R2

MAR <- [R1]

Request memory READ and put the data to the address register
 Wait for the Memory Fetch Cycle (MFC) signal and put the result from [MDR]
to R2.
R2 <- [MDR]

Both 2 and 3 are regarded as asynchronous data transfer.

Storing a word into memory

The example below shows how the machine store a word in R2 into a memory
location, whose address is specified in R1

MAR <- [R1]

MDR <- [R2]
Request memory write
Wait for MFC signal

Both steps 3 and 4 are regarded as asynchronous data transfer.

Register transfer
Data transfer between 2 CPU registers is via the input and output gating control as
shown in Figure .

Example  : R2  <- [R1]

The register transfer R2 <- [R1] can be denoted by the control sequence R1out,
R2in

Performing and arithmetic/Logic operation

Figure shows a single bus CPU which has three registers, namely, R1, R2 and R3,
and one Z register output. The following simple assemble language is carried out
by this CPU.

Example : R3 <- [R1] + [R2]

Control sequence for instruction for

ADD  R1, R2, R3 # to add R1 and R2 together and put the result to R3

Step Action Comment

1 R1out, Yin Y <-[R1]
2 R2out, Add, Zin Z <- [Y] + [R2]
3 Zout, R3in R3 <- [Z]
For a two-bus structure inside the CPU as shown in Figure . To carry out the
following instruction using one(single) bus structure

ADD R1, R2, R3 #to add R1 and R2 together and put it to R3

It takes 2 steps as shown in the following table. This demonstrates that dual-bus
CPU takes less internal steps to complete an instruction.

Step Action Comment

1 R1out, Gout, Yin Y <- [R1]
R2out, Yout, Add, ALUout,
2 R3 <- [Y] + [R2]
R3in

The organization of data paths inside the CPU can affect its cost and speed (i.e.
instruction execution time)

Execution of a complete instruction

Using the single-bus organization, the control sequence for executing the PDPD 11
instruction ( You can find the details of this instruction from Structured Computer
Organization.)

ADD @#A, R1    (assume this instruction occupies 1 word)

Step Action Comment

PCout, MARin, Read, Clear Y, Set
1 MAR <- [PC], Z <-[PC] +1
Carry-in, Add, Zin
2 Zout, PCin, Wait for MFC PC <- [Z], Wait for MFC
3 MDRout, IRin IR <- [MDR]
4 Addr-field(IRout), MARin, Read MAR <- Addr_field(IR), Read
5 R1out, Yin, Wait for MFC Y <- [R1]
6 MDRout, Yout, Add, Zin Z <- [Y] + [MDR]
7 Zout, R1in R1 <- [Z]

This time uses a two-bus organization to execute the same instruction

ADD @#A, R1

The format of this instruction is shown in Figure . This format is equivalent to

ADD @(R7)+, R1 (You don’t have to memorise the following sequences)

Step Action Comment

1 PCout, G, MARin, Read MAR <- [PC], Read
  A=2, Add, Zin Z <- [PC] + 2
2 Zout, PCin, Wait for MFC PC <- [Z], wait for MFC
3 MDRout, G, IRin IR <- [MDR]
R7out, G, MARin, Read MAR <- [PC], Read
4
A = 2, Add, Zin Z <- [PC] + 2
5 Zout, PCin, Wait for MFC PC <- [Z], wait for MFC
6 MDRout, G, MARin, Read MAR <- [MDR], Read
7 Wait for MFC Wait for MFC
8 MDRout, G, Yin Y <- [MDR]
9 R1out, Add, Zin Z <- [Y] + [R1]
10 Zout, R1in R1 <- [Z]

Sequencing of control signals

To execute an instruction, the CPU must have some means of generating the
control signals discussed above. Two techniques are used to design the control
unit:

Hardwired control
Microprogrammed Control

A Hardwired Control unit organization

Figure is the diagram showing the components required to form a control unit. The
function of each component is as follows:

Component Function

Microprogrammed Control Unit

Microprogrammed Control Unit is:

Each machine instruction is executed by means of interpreting a microprogram

subroutine.
Each instruction of the microprogram subroutine is called a microinstruction
All microprogram subroutines are stored in a special microprogram memory,
Control Storage.

A typical format of microinstruction is:

R1in R1out R2in R2out..... Yin Yout Zin Zout MDRin MDRout
T he major hardware of microinstruction is usually implemented by means of bit-
sliced microprocessor. This microprocessor is a self-contained single chip
microprocessor with the capability of cascading several chips together to form
larger bit size such as 64 bits or 128 bits. The instruction speed is faster than any
single chip processor, like 80386.

Figure shows a typical organization of a microprogrammed control unit. Here, the

programme is stored in the memory and the instruction is decoded by IR. The
control signals will be used to control the control gates such as Zin, Zout, R1in etc.
This will generate a correct sequence to operate the control gates in order to
indirectly control the data movement as discussed in section 1.

C an you list the function of each component?

The function is similar to hardwired control unit except that it is configurable only.

I/O Organization

The I/O architecture defines the interface a program uses to move data between a
processor or memory and the I/O devices of the computer system. There are a few
considerations for designing such a device such as

The source of data

The function of the I/O device
The amount of data
The method of handshaking the device

There are many kinds I/O devices with different properties as shown below:

Type Description
Disk Use special commands to move the disk arm to read/write data
Magnetic Tape Use special commands to back space the tape
Printers Special form feed or graphics commands that prints Text
Terminals Special commands for drawing lines, figures, pictures etc.
Optical
Read documents created by humans into a computer system.
Scanner

There are a few I/O operations common to all devices listed above:
 Read (Transfer data from I/O device to RAM)
Write (Transfer data from RAM to I/O device)
The location in the processor-memory complex data are to be taken from write
or placed into read. Also indicates how much data is to be transferred between
the processor-memory and the I/O device
Synchronization method to indicate whether or not an interrupt is desired and
when the interrupt should occur
The recording format to be used from the device.

Virtual Memory vs. I/O instructions

Both are techniques for moving data or code between disk and memory.The
differences are shown in the following table.

Type Advantages Disadvantages

Explicit I/O Programmers control I/O Programmers must perform each
Instructions including when and where I/O
Invisible to programmer Potential for performance
Virtual problems if not enough memory to
Memory Easy to add more memory without hold working set of program
reporgramming pages

The issues of

How data is transferred and ;

How to know when the I/O is finished are related?

There are four I/O schemes being used to deal with these issues

Programmed I/O with busy waiting

Interrupt-driven I/O
Direct Memory Access I/O
I/O using data channels

Programmed I/O with busy waiting

The characteristics of this type are :-

The simplest I/O scheme and is used on very low-end microprocessor

Each I/O device has a 1 byte register for input and 1 for output
The CPU transfers data to/from the I/O device 1 byte at a time. After each byte
is transferred, the CPU waits for the device to become ready for the next
transfer
Memory-mapped I/O
The memory interprets certain reserved memory locations as belonging to various
I/O devices. This method is quite common on Microcomputers and Minicomputers
such as 80x86, 680x0, VAX etc.

If an instruction uses these reserved memory locations, an I/O is started when

the instruction is executed.
If the address is a destination in the instruction, data is written to the I/O device
If the address is a source in the instruction, data is read from the I/O device

Other reserved memory locations are for device control such as backspace for
magnetic tape, form feed for printer.

For the single bus configuration, the following command

MOVE   R1, P

As shown in Figure , it will move the data from the register to the reserved
memory address, P, for the printer. When the address P is put on the address lines
of the bus, the memory ignores it and the printer reserves the data. (From R1 in
this case.) Other special memory locations are used for advancing to next print
line, etc.

F or the printer device, we can only write to it, as read causes an error.

Advantages of Memory-mapped I/O

There are many advantages of using memory-mapped I/O such as:

Any instruction can start an I/O.

All address modes are valid. For example, we can use indirect mode to step
through several I/O devices such as Figure .

Microprocessor I/O operations

Figure indicates the structure of Microprocessor. The operation of such

configuration works as follows:

The I/O read and I/O write are used to move the data on the data bus.
READY is used to signify the completion of operation
PORT SELECT is used to select the appropriate device. This is equivalent to an
address bus for I/O devices
The INTERRUPT REQUEST signals are used by the microprocessor that an
 I/O device is ready for service
The INTERRUPT ACKNOWLEDGE is used for acknowledgment purpose

Using this configuration, the typical requirements for pins on the microprocessor
are :-

Type Number
Memory address 16
Memory Data 8 or 16
I/O Port select 6 to 8
I/O data 8
Memory Control 3
I/O control 5
Total pins 40 - 50

The total number of pins is between 40 to 50 without taking into account the
power, clock etc. As, the cost for the circuit board is related to pin count and also
the Integrated Circuit packages is in standard size of 16, 24, 40 and pins, it is
therefore beneficial to reduce pin count to one of the critical number.

The modified configuration by multiplexing the number of address and data

together is shown in Figure .

C an you point out the advantage of using address/data multiplexing?

One of the advantages is to reduce the number of pins. This will reduce the CPU’s
size and as a result will reduce the heat dissipation (heat generated due to the
movement of electronics at high speed).

Summary

This chapter discussed the CPU internal structure. Dual-bus structure has the
advantage of moving data from one bus while processing another data. This
operation outperforms the single-bus CPU. Students also understand the
development of CPU chip starting from 8088 to Pentium Pro (600MHz). The
CPU’s pin layout was designed from one-dimensional to three dimensional. The
signals of controlling the gates to on or off state are from the control unit, which
can be implemented by hardwired control or microprogrammed control units.
Microporgammed control unit has the advantage of being configurable by ordinary
users. To reduce the number of pins, multiplexed address and data buses are widely
adopted. This can, of course, be achieved as a result of high speed CPU.
Self-test Question

The advantage of dual-bus CPU over single bus-CPU is _________(execution

speed, complex instruction, less heat generated).
The advantage of generating high-level language directly to machine code is
_________(execution speed, portability, security).
Assume R1, R2 are 4 and 2 respectively. After executing the instruction R2 <-
[R1], R1 is ____(1, 2, 4).
PC in a CPU stands for _____________(Programme Control, Personal
Computer, Programme Counter).
The advantage of microprogrammed control unit over hardwired control unit is
____________(flexible in programming, configurable.)