Chapter 3 :

Interconnection of
Processor, Memory, I/O
through system Bus
3. System Bus

3.1. Computer Components :

CPU Memory

MAR 0 ...
1 Instruction
MBR 2 Instruction
Cache Instruction
I/O AR Memory
...
I/O BR
Data
I/O Module Data
Data

n
Buffers
3.2. The Computer Function

• Basic function : program execution

• Program : Set of instructions stored in memory
• CPU fetches the instructions, one at a time and executes
them one by one, according to the operation code
• Simple way of thinking : two steps of instruction
processing, fetch and execute
• Actually, instruction execution may involve a number of
steps
• The processing time required for execution of a single
instruction is called an instruction cycle time
3.2 Computer Function : Basic Instruction Cycle

START

Fetch
Next
Fetch Cycle
Instruction

Execute
Instruction Execute Cycle

HALT
3.2 Function - Fetch and Execute Cycles
• An instruction is fetched to CPU using the address in PC
(Program Counter)
• Unless told otherwise, CPU always increment PC by one
after fetching an instruction. PC points to next instruction.
• Example : For instance PC is set to 300. After a fetch
cycle, the PC is incremented by 1. PC points to location
301. This activity happens at PC unless CPU execute a
jump instruction.
• The fetched instruction is loaded into IR (Instruction
Register) in the CPU. The instruction is in the form of
binary code.
3.2. Function - Fetch and Execute Cycle, continued

• Then CPU interprets the instruction and perform the

required action
• In General these actions fall into four categories :
CPU - Memory, data is transferred to and from memory
CPU-I/O, data may be transferred to and from the outside
world
Data Processing. CPU performs some Arithmetic and
Logic operation on data
Control. An instruction may specify that the sequence of
execution is to be altered (e.g. jump).
3.2 Function - Instruction format & codes
• Consider a hypothetical machine :
0 3 4 15
OpCode Address
a. Instruction Format

0 1 15
S Magnitude
b. Integer Format
Program Counter (PC) = Address of Instruction
Instruction Register (IR) = Instruction being Executed
Accumulator (AC) = Temporary Storage
c. Inter CPU Registers
0001 = Load AC from Memory
0010 = Store AC to Memory
0101 = Add to AC from Memory
d. Partial List of Opcodes
3.2 Function - Example of program execution
Word length = 16 bit, divided into 4 bit op-code (24
different op-codes) and 12 bit address (212 memory
locations).
1. Assume PC contains 300. This content of location 300 is loaded
into IR (First PC to MAR, READ, Memory xfer to MBR and
finally MBR to IR).
2. The first 4 bit in IR indicate that AC is to to be loaded. The next
12 bits (940) specify operand address.
3. PC is incremented, next instruction is fetched
4. Old content of AC & content of location 940 are added, stored
in AC.
5. PC is incremented, next instruction is fetched.
6. The content of AC are stored in location 941.
3.2 Function - execution in hypothetical machine

0001 1001 0100 0000

0010 1001 0100 0001

3.2. Function - example, continued
• The previous execution, needs 3 instructions to complete.
Can’t it be faster ?
• Yes, PDP-11 instruction like ADD A,B does the same
thing. Add contents of locations A and B, store the result
in location A. Just one instruction.
• But is it faster then the previous instruction ?
• If we look deeper, the steps of execution could be
described like :
1. Instruction Address Calculation (iac). Determine the
address of next instruction to be executed.
2. Instruction Fetch (if). Read instruction from memory.
3.2. Function : execution, continued
3. Instruction operation Decoding (iod). Analyze
instruction to determine type of operation to be performed.
4. Operand Address Calculation (oac). This is true if it
involves operand in memory or available via I/O.
5. Operand Fetch (of). Fetch operand from memory or
read it from I/O.
6. Data Operation (do). Perform operation indicated in the
instruction.
7. Operand Store (os). Write result into memory or out to
I/O.
The operation described above is visualized in the next page.
Instruction Cycle State Diagram
Let’s analyze instruction cycle
the other way of thinking
Using the register transfer
language
 Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
Instruction Format

Memory to Memory Instruction Format

ADD A,B
0 7 8 19 20 31

“ADD” “A” “B”

Op-Code address of op-1 (12 bit) address of op-2 (12 bit)

Instruction Steps - “microscopic view”
For instance, we analyze the execution of : ADD A,B

• Instruction Fetch : MAR  PC

Read (fetch an instruction, WAIT)
IR  MBR
• Operand Fetch : MAR  [Addr-op-1-IR]
Read (operand-1, WAIT)
ALU1  MBR
MAR  [Addr-op-2-IR]
Read (operand-2, WAIT)
ALU2  MBR
• Arithmetic ADD
MBR  ALU3
MAR  [Addr-op-1-IR]
Write
 Control
Unit
PC
MAR (1)

IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Wait for Memory (3)
Read (2) Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
R1
MBR
(4)

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
Addr-op1 Addr2-op2 (5)
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Wait for Memory (7)
Read (6)
Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
R1
MBR
(8)

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
Addr1-op1 Addr2-op2
(9) R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
Read (10) Wait for Memory (11)
Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
R1
MBR
(12)

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU: ADD (13)

MAR : Memory Addres Register

ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2 (14)

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 Control
Unit
PC
MAR

R1
MBR
(15)

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
Write (16) Control
Unit
PC
MAR
IR
R1
MBR

R2

ALU1 ALU2

R3

ALU
MAR : Memory Addres Register
ALU3 MBR : Memory Buffer Register
IR : Instruction Register
PC : Program Counter
BUS
 3.2. Interrupt
• Interrupt is a mechanism whereby a
particular computer system component (I/O
devices, Real Time Clock, Memory Unit,
etc) could ask for CPU attention due to
some very important condition occuring
3.2 Interrupts
Table 3.1 : Classes of Interrupts
--------------------------------------------------------------------------
Program Generated by some condition that occurs as a result
of an instruction execution, such as arithmetic
overflow, division by zero, attempt to execute illegal
instruction, reference outside user’s allowed memory
space.
Timer Generated by timer within the processor. This
allows the O/S to perform certain function on regular
basis.
I/O Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of
error conditions
Hardware Failure Generated by failure, such as power or memory
parity.
-----------------------------------------------------------------------------------------
Interrupts - continued :

• How interrupt process actually carried-out :

by transfer control of execution from main program to
interrupt handler
• In a way, it looks like “subroutine”
• Actually, an interrupt forces the OS to stop CPU from
running “current” program
• Then, CPU runs the interrupt handler
• May cause “context switching”
• This may have a relation with “priority of scheduling”
interrupt handler
Interrupts : transfer of command
What happen with instruction cycle ?
Instruction cycle with interrupt
Instruction Cycle State diagram with interrupts
Multiple interrupts - a visualization
 Example of Interrupt chain
Disk Printer Floppy Keyboard

0 1 2 3 Interrupt register

I0
To CPU
I1 VAD
Priority x
I2 Encoder y
0
I3
0 Bus
0 Buffers
0
0
Mask
0 1 2 3 register 0

Bus Buffer
Enable line

IST IEN Signal line From CPU

Signal line tp CPU

Mask Register could be set to 0, which disable the possibility of accepting interrupt signal from devices (0 through 3)
IEN is a latch, that may be set by the CPU to enable/disable the acceptance of any interrupt form all devices
 Example of Interrupt chain
Disk Printer Floppy Keyboard

0 1 2 3 Interrupt register

1 1
I0
1
0 I1 VAD
1 Priority 1
0
I2 Encoder 1
1
0
0 I3
0 Bus
1
0 Buffers
0
0
Mask
0 1 2 3 register 0

IST IEN

Interrupt to CPU
Device 0 interrupt, mask-bit is 1.
Interrupt signal reach Priority Encoder, going out with device code 11 (in VAD)
Interrupt signal goes further to CPU, using the bottom side of the circuit (red lines)
 Example of Interrupt chain
Disk Printer Floppy Keyboard

0 1 2 3 Interrupt register Interrupt

Address (VAD)
(Vector)
1 1
I0 To CPU
1
0 I1 VAD
1 Priority 1
0
I2 Encoder 1
1
0
0 I3
0 Bus
1
0 Buffers
0
0
Mask
0 1 2 3 register 0
Enable

IE
IST IEN INTACK from CPU

Interrupt Acknowledged by the CPU (INTACK)

Interrupt enable latch is set on (IEN)
Interrupt signal, IEN signal and INTACK set the IE AND gate to pass interrupt enable signal to BUS Buffers
Enabled by this signal, Bus Buffers send the interrupt address to CPU (the address of interrupt handler)
Interrupt Circuit
Occasion of interrupt

• Interrupt could only happen after an instruction is

completely executed, not within the execution cycle of
an instruction (!)
• Why ?
• What if a device interrupts when an instruction is
being executed ?
• What are the risks ?
• If we design the instruction, what is the most important
principle (considering the possibility of interrupt may
happen at any time) that must be taken into account ?
3.3. Interconnection Structures

• A computer system consists of a set of components (CPU,

memory and I/O).
1. Memory, typically consists of a number of locations (n
locations, addressed 0 to n-1). Valid operations on memory
are Read and Write.
2. I/O Module. From inside the computer, I/O module is
just another memory. I/O module may control more than
one I/O devices (0, ….,M-1). Each device has an interface
called the port. Devices may send interrupts signal to CPU.
3. CPU, reads instruction and data, write out data after
processing, using control signal to manage the system.
3.3. Interconnection Structures - continued

• The interconnection structures, support the following type

of transfers :
Memory to CPU. CPU read instruction/data from memory.
CPU to Memory. CPU writes unit of data to memory.
I/O to CPU. CPU reads data from I/O device (via I/O
module).
CPU to I/O. CPU sends data to I/O.
I/O to or from Memory. I/O module allowed to exchange
data directly with memory (DMA)
 Memory Operation - Read

Read
2
Memory

Write N words
3
0
1 Data

Address

Data N-1
 Memory Operation - Write

Read Memory

Write 3 N words
0
1

Address

Data N-1

2
3.3. Interconnection Structures - Diagram
3.4 Bus Interconnection
• A bus is a communication pathway connecting two devices
or more.
• Each line in a bus, carries one bit of information
• In the case of single bus, at one one instant, only one
device may transmit information. The information is
available at the bus to be accepted by other devices
(connected to the bus).
• Computer systems contain a number of different buses,
that provide pathways between various components.
• A bus connects CPU, Memory and I/O is called the system
bus.
3.4 Bus Interconnection : Bus Structure
• A system bus, typically consists of 50 - 100 lines. Each
line is assigned a particular meaning or function.
• The lines can be classified into three functions : data,
address and control
• The data line, which carries data in it, may consists of 8,
16, 32 bit or even more (bus width).
• The address lines are used to designate the source or
destination of the data on the bus (also 8, 16 or 32 bits).
• The address width determines the maximum possible
locations in memory can be reached.
• Typically, high-order bit is used to select memory module
3.4 Bus interconnection : Bus Structure, continued
• Example in 8 bit address : 01111111, meaning that it
chooses memory module 0 and address 127 within that
module.
• The control lines, are used to control the access and the use
of data and address lines.
• Typical control lines include : memory read and write, I/O
read and write, transfer ACK,bus request, bus grant,
interrupt, interrupt ACK, clock and reset.
• The operation of the bus : If one module wishes to send
data to another, then (1) obtain the use of bus then (2)
transfer data. If one module to request, then it must (1)
obtain the bus, (2) request the other module to send
3.4 Bus interconnection : Multiple Bus Hierarchy

• If a great number of devices are connected to the bus,

performance will suffer.
• The greater the number of devices, the greater the
propagation delay.
• Also the bus may experience bottleneck
• That’s why most modern computers implements multiple
bus, structured in a hierarchy (of component’s importance)
• Figure 3.18.a in the next page, is an example of traditional
bus architecture
• Figure 3.18.b shows a more advanced bus architecture.
3.4 Bus Interconnection : Multiple Bus Hierarchy
3.5 Contemporary Bus Structure - PCI
• PCI (Peripheral Component Interconnect) is a high
bandwidth independent processor bus available on the
market.
• PCI may be configured as a 32 or 64 bit bus.
• It has various commands (see table 3.3 in the reference
book).
• Another bus is FUTUREBUS (ANSI/IEEE Std 896) and
FUTUREBUS+
• FUTUREBUS was a 32 bit bus (originally). Since 1987,
the design was revised to 32, 64, 128 and 256 bit bus,
called the FUTUREBUS+