7 Series FPGA Overview

Part 1
Objectives

After completing this module, you will be able to:

 Identify and differentiate the members of the 7 series families

7 Series FPGA Overview - 2 © Copyright 2011 Xilinx

 7 Series FPGA Families

Lowest Power Industry’s Best Industry’s Highest

Maximum Capability and Cost Price/Performance System Performance

7 Series FPGA Overview - 3 © Copyright 2011 Xilinx

Virtex-7 Devices

 The Virtex-7 family has several devices

– Virtex-7: General logic
– Virtex-7XT: Rich DSP and block RAM, higher serial bandwidth
– Virtex-7HT: Highest serial bandwidth

Virtex-7 Virtex-7XT Virtex-7HT

Logic
Block RAM
DSP
Parallel I/O
Serial I/O

• High Logic Density • High Logic Density • High Logic Density

• High-Speed Serial • High-Speed Serial • Ultra High-Speed
Connectivity Connectivity Serial Connectivity
• Enhanced DSP

7 Series FPGA Overview - 4 © Copyright 2011 Xilinx

Architecture Alignment

 Common elements enable easy IP reuse for quick

design portability across all 7 series families
– Design scalability from low-cost to high-performance Artix™-7 FPGA

– Expanded eco-system support

– Quickest TTM
Logic Fabric Precise, Low Jitter Clocking
LUT-6 CLB MMCMs
Kintex™-7 FPGA
On-Chip Memory Enhanced Connectivity
36Kbit/18Kbit Block RAM PCIe® Interface Blocks

DSP Engines Hi-perf. Parallel I/O Connectivity

DSP48E1 Slices SelectIO™ Technology

Hi-performance Serial I//O Connectivity

Transceiver Technology

Virtex®-7 FPGA

7 Series FPGA Overview - 5 © Copyright 2011 Xilinx

Strong Focus on Power Reduction

Reducing
Static Power
Additional
Power Saving High performance,
Features Integrated Analog Front End
low power process Transistor choice
optimization
VCCAUX

Config Reduced from BRAM

5th gen. partial Memory 2.5V to 1.8V
reconfiguration

Unused BRAM
Power Savings
Before After Process Shrink
Reducing
Dynamic Power

Fine grain clock and logic gating

Optimized Hard
IO Design & Blocks
User Power VCCO
Saving Modes

Lower device -1 L + Pad

core voltage Xilinx In
-
7 Series
FPGAs Out Reducing
I/O Power
7 Series FPGA Overview - 6 © Copyright 2011 Xilinx
7 Series Lower Power Differentiation

 50% lower total power

– 65% lower static power enabled by 28nm High-Performance, Low-Power (HPL)
HKMG process
– 25%+ lower dynamic power via architectural evolution Increase Usable
50% Lower Performance
– 30% lower I/O power with Power OR and Capacity

enhanced capability
 System design flexibility
– 50% lower power budget
OR
– Take advantage of additional
usable performance and capacity
at the previous power budget

7 Series FPGA Overview - 7 © Copyright 2011 Xilinx

Summary

 Rich set of families to address all areas of the FPGA market

– Artix-7 family: Lowest price and power
– Kintex-7 family: Best price/performance
– Virtex-7 family: Highest performance/capacity
 Unified architecture reduces learning curve for new designs
 Builds on the strengths of the Virtex-6 and Spartan-6 families
 Strong focus on power reduction
 New architectural features for the highest performance and lowest power

7 Series FPGA Overview - 8 © Copyright 2011 Xilinx

Where Can I Learn More?

 Xilinx Education Services courses www.xilinx.com/training

– Designing with 7-Series Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
 Free Video Based Training
– Part 1,2, and 3 of the 7 Series FPGA Overview
– How Do I Plan to Power My FPGA?
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– Basic FPGA Configuration, Parts 1 and 2
7 Series FPGA Overview - 9 © Copyright 2011 Xilinx
Trademark Information

Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate
on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,
downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark
laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE
ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications.
You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.

7 Series FPGA Overview - 10 © Copyright 2011 Xilinx

7 Series FPGA Overview

Part 2
Objectives

After completing this module, you will be able to:

 Describe the architecture of the 7 series FPGAs

7 Series FPGA Overview - 12 © Copyright 2011 Xilinx

Fourth-Generation ASMBL Architecture

SelectIO SelectIO
Serial Transceiver
 Optimized FPGA feature mix for different & CMT DSP Logic & CMT

families/members
– FPGA comprises columns of different
resources
• Clocking, I/O, BRAM, DSP, HSSIO
 Enables the unified architecture between
the different 7 series families
 Enables different resource ratios within
the different devices

BRAM
Clock Buffers
and Routing
PCI Express

7 Series FPGA Overview - 13 © Copyright 2011 Xilinx

7 Series FPGA Layout

 All devices contain two I/O columns

– Contains parallel I/O resources
 Clock Management Tile (CMT)
columns are adjacent to I/O columns
– Enables high speed I/O interfaces
 Clock routing resources are in the
center column
 High-speed serial I/O replace I/O
banks in smaller devices or are
contained in additional
I/O Clock Routing HSSIO
columns in larger devices
CMT CLB, BRAM, DSP

7 Series FPGA Overview - 14 © Copyright 2011 Xilinx

Clock Regions and I/O Banks

 Each clock region is 50 CLBs tall

– An increase from 40 CLBs in previous
technologies 50 CLB
– Regional clock resources remain in the
center of the clock region 50 IOB

• 25 rows of CLBs above and below the

clock routing
 I/O banks are 50 IOBs tall
– An increase from 40 IOBs in previous technologies
– I/O banks and clock regions are aligned, like in previous technologies

7 Series FPGA Overview - 15 © Copyright 2011 Xilinx

CLB Structure

SLICE
 Two side-by-side slices per CLB
LUT
– Slice_M are memory-capable
SLICE
– Slice_L are logic and carry only
LUT

 Four 6-input LUTs per slice

– Consistent with previous architectures
– Single LUT in Slice_M can be a 32-bit
shift register or 64 x 1 RAM

 Two flip-flops per LUT

– Excellent for heavily pipelined designs

CLB
–
7 Series FPGA Overview - 16 © Copyright 2011 Xilinx
Block RAM

 36K/18K block RAM

– All Xilinx 7 series FPGA families use ADDRA Port A 36
36 DOA
same block RAM as Virtex-6 FPGAs 4
DIA
WEA
CLKA
 Configurations same as Virtex-6 FPGAs
36 Kb
– 32k x 1 to 512 x 72 in one 36K block Memory
Array
– Simple dual-port and true dual-port 36
ADDRB
36
DIB DOB
configurations 4 WEB
CLKB
– Built-in FIFO logic Port B

– 64-bit error correction coding per 36K

block
– Adjacent blocks combine to 64K x 1
without extra logic

7 Series FPGA Overview - 17 © Copyright 2011 Xilinx

DSP Slice

• All 7 series FPGAs share the same DSP slice

• 25x18 multiplier
• 25-bit pre-adder
• Flexible pipeline
• Cascade in and out
• Carry in and out
• 96-bit MACC
• SIMD support
• 48-bit ALU
• Pattern detect
• 17-bit shifter
• Dynamic operation
(cycle by cycle)

7 Series FPGA Overview - 18 © Copyright 2011 Xilinx

Clocking Resources

 Based on the established Virtex-6 FPGA

clocking structure
– All 7 series FPGAs use the same unified
architecture

Buffers
Clock
MMCM
 Low-skew clock distribution
– Combination of paths for driving clock signals PLL
to and from different locations
 Clock buffers
– High fanout buffers for connecting clock signals
to the various routing resources
 Clock regions
Clock Automatic
– Device divided into clock regions with Wizard HDL code
dedicated resources
 Clock management tile (CMT)
– One MMCM and one PLL per CMT
– Up to 24 CMTs per device

7 Series FPGA Overview - 19 © Copyright 2011 Xilinx

Input/Output Blocks

 Two distinct I/O types

– High range: Supports standards up to 3.3V
– High performance: Higher performance
with more I/O delay capability
• Supports I/O standards up to 1.8V
 Extension of logic layer functionality IO
FIFO
– Wider input/output SERDES
– Addition of independent ODELAY
 New hardware blocks to address
highest I/O performance
Phaser
– Phaser, IO FIFO, IO PLL IO PLL
Ø Shift

7 Series FPGA Overview - 20 © Copyright 2011 Xilinx

Stacked Silicon Interconnect Technology

 Largest Virtex-7 device is almost three times the size of the largest Virtex-6
device
– Growth is higher than Moore’s Law dictates
 Enabled by Stacked Silicon Interconnect (SSI) technology
– Multiple FPGA die on a silicon
interposer
– Each die is referred to as a
Super Logic Region (SLR)
– Vast quantity of interconnect
between adjacent SLRs are
provided by the interposer

65% 130% 163%

7 Series FPGA Overview - 21 © Copyright 2011 Xilinx
Stacked Silicon Implications

 Enables substantially larger devices

 Device is treated as a single monolithic device
– Tool chains place and route complete device as if it was one die
 Minor design considerations around clocking and routing

28nm 28nm 28nm 28nm

FPGA Die FPGA Die FPGA Die FPGA Die Micro-bump
TSV
Si Interposer
C4 Bump

Package
Package

7 Series FPGA Overview - 22 © Copyright 2011 Xilinx

Summary

 Rich set of families to address all areas of the FPGA market

– Artix-7 family: Lowest price and power
– Kintex-7 family: Best price/performance
– Virtex-7 family: Highest performance/capacity
 Unified architecture reduces learning curve for new designs
 Builds on the strengths of the Virtex-6 and Spartan-6 families
 Strong focus on power reduction
 New architectural features for the highest performance and lowest power

7 Series FPGA Overview - 23 © Copyright 2011 Xilinx

Where Can I Learn More?

 Xilinx Education Services courses www.xilinx.com/training

– Designing with 7-Series Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
 Free Video Based Training
– Part 1,2, and 3 of the 7 Series FPGA Overview
– How Do I Plan to Power My FPGA?
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– Basic FPGA Configuration, Parts 1 and 2
7 Series FPGA Overview - 24 © Copyright 2011 Xilinx
Trademark Information

Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate
on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,
downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark
laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE
ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications.
You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.

7 Series FPGA Overview - 25 © Copyright 2011 Xilinx

7 Series FPGA Overview

Part 3
Objectives

After completing this module, you will be able to:

 Identify the dedicated IP in the 7 series FPGAs
 Identify some of the differences between the 7 series and Virtex-6 FPGAs

7 Series FPGA Overview - 27 © Copyright 2011 Xilinx

High-Speed Serial I/O Transceivers

 Available in all families

 GTP transceivers – up to 3.75 Gbps
– Ultra high volume transceiver
– Wire bond package capable
 GTX transceivers – up to 12.5 Gbps
– Support for the most common 10 Gbps protocols
 GTH transceivers – up to 13.1 Gbps
– Support for 10 Gbps protocols with high FEC
overhead
 GTZ transceivers – up to 28 Gbps
– Enables next generation 100–400Gbps system line cards

7 Series FPGA Overview - 28 © Copyright 2011 Xilinx

PCI Express

 Features
– Compliant to PCIe Revision 2.1 GTX Transceivers
– Endpoint & root port
– AXI user interface
– <100 ms configuration* PCI Express Block
– FPGA configuration over PCI Express*
Data
– End-to-end CRC* Transaction
Link
Layer
– Advanced error reporting* Layer Physical
– 100-MHz clocking Layer
 New wrappers
Configuration module
– Multi-function*
– Single-root I/O virtualization*
 Configurations
– Lane widths: x1-8
– Data rates: Gen1 & Gen2 (2.5/5.0 Gbps)
– Dependent on GT and fabric speed *New features in 7 series

7 Series FPGA Overview - 29 © Copyright 2011 Xilinx

XADC: Dual 12-Bit 1-MSPS ADCs

17
17 External
External
Analog
Analog Inputs
Inputs
XADC ADC
ADC Results
Results

Status
Registers
ADC 1
MUX Define
Define XADC
XADC
Control Operation
Operation
On-Chip Registers
Sensors Initialize
Initialize with
with
ADC 2 Attributes
Attributes
DRP
22 xx 12
12 Bits
Bits JTAG
11 MSPS
MSPS Arbitrator
On-Chip
On-Chip Sensors
Sensors
Supplies
Supplies ±1%
±1%
Temperature
Temperature ±4°C
±4°C Interconnect
Dynamic
Dynamic
Reconfiguration
Reconfiguration Port
Port

7 Series FPGA Overview - 30 © Copyright 2011 Xilinx

Cost, Power, and Performance

 The different families in the 7 series provide solutions to address the different
price/performance/power requirements of the FPGA market
– Artix-7 family: Lowest price and power for high volume and consumer applications
• Battery powered devices, automotive, commercial digital cameras
– Kintex-7 family: Best price/performance
• Wireless and wired communication,
medical, broadcast
– Virtex-7 family: Highest performance
and capacity
• High-end wired communication,
test and measurement, advanced
RADAR, high performance
computing

7 Series FPGA Overview - 31 © Copyright 2011 Xilinx

I/O Composition

 Each 7 series I/O bank contains one type of I/O

– High Range (HR)
– High Performance (HP)
 Different devices have different mixtures of I/O banks

Virtex-7
I/O Types Artix-7 Family Kintex-7 Family Virtex-7 Family
XT/HT Family

High Range All Most Some

High Performance Some Most All

7 Series FPGA Overview - 32 © Copyright 2011 Xilinx

 Multi-Gigabit Transceiver

 Different families have different MGT devices

– Artix-7 family: GTP
– Kintex-7/Virtex-7 family: GTX
– Virtex-7 XT family: Mixture of GTX and GTH
– Virtex-7 HT family: Mixture of GTH and GTZ
Artix GTP Kintex Virtex Virtex Virtex
Speed GTX GTX GTH GTZ
Grade min max min max max min max min max min max
(FF)

1LC/I 0.612 3.125 0.612 5.0 6.6 0.612 6.6 0.612 10.3125 N/A N/A
1C/I 0.612 3.125 0.612 5.0 6.6 0.612 6.6 0.612 10.3125 TBD TBD
2C/I 0.612 3.75 0.612 6.6 10.3125 0.612 10.3125 0.612 13.1 28.05 28.05
3C N/A N/A 0.612 6.6 12.5 0.612 12.5 0.612 13.1 28.05 28.05

7 Series FPGA Overview - 33 © Copyright 2011 Xilinx

Packaging – Artix-7 Family

 Ultra low-cost wire bond technology

 Small form factor
 Fourth generation sparse chevron pin
pattern
 Speeds up to 1.066 Gbps for parallel I/O
 Speeds up to 3.75 Gbps for MGT

7 Series FPGA Overview - 34 © Copyright 2011 Xilinx

Packaging – Kintex-7 Family

 Kintex-7 devices are available in two different packages

– Low cost bare die flip chip (FB) and conventional flip chip (FF)
– Small form factor packaging available
 Fourth generation sparse chevron pin pattern
 Speeds up to 2.133 Gbps for Exposed Exposed Bare Die Flip Chip
parallel I/O Silicon Die Decoupling Package (FB)
Solder Capacitors
 Speeds up to 12.5 Gbps for Bumps Package
MGT in FF package, and Substrate
6.6 Gbps in FB package ooooo
 FB package has discrete
Solder Balls
substrate decoupling
capacitors for MGT power
supplies

7 Series FPGA Overview - 35 © Copyright 2011 Xilinx

Packaging – Virtex-7 Family

 High performance flip chip (FF) package

 Fourth generation sparse chevron pin pattern
 Speeds up to 2.133 Gbps for parallel I/O
 Speeds up to 28.05 Gbps for MGT
 Discrete substrate decoupling capacitors:
– MGT power supplies
– Block RAM power supplies
– I/O pre-driver power supplies

7 Series FPGA Overview - 36 © Copyright 2011 Xilinx

Summary

 Rich set of families to address all areas of the FPGA market

– Artix-7 family: Lowest price and power
– Kintex-7 family: Best price/performance
– Virtex-7 family: Highest performance/capacity
 Unified architecture reduces learning curve for new designs
 Builds on the strengths of the Virtex-6 and Spartan-6 families
 Strong focus on power reduction
 New architectural features for the highest performance and lowest power

7 Series FPGA Overview - 37 © Copyright 2011 Xilinx

Where Can I Learn More?

 Xilinx Education Services courses www.xilinx.com/training

– Designing with 7-Series Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
 Free Video Based Training
– Part 1,2, and 3 of the 7 Series FPGA Overview
– How Do I Plan to Power My FPGA?
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– Basic FPGA Configuration, Parts 1 and 2
7 Series FPGA Overview - 38 © Copyright 2011 Xilinx