Design of AMBA AXI4 protocol for System-on-Chip communication

Design of AMBA AXI4 protocol for System-on-Chip communication

Shaila S Math and Manjula R B

Dept. of ECE,
REVA Institute of Technology and Management, Bangalore, India.
shaila.s.math@gmail.com and manjularb@rediffmail.com

Abstract— Advanced microcontroller bus architecture (AMBA) address channel, write data channel, read data channel, read
protocol family provides metric-driven verification of protocol address channel, and write response channel. The AXI4
compliance, enabling comprehensive testing of interface protocol supports the following mechanisms:
intellectual property (IP) blocks and system-on-chip (SoC) • Unaligned data transfers and up-dated write response
designs. The AMBA advanced extensible interface 4 (AXI4)
requirements.
update to AMBA AXI3 includes the following: support for burst
lengths up to 256 beats, updated write response requirements, • Variable-length bursts, from 1 to 16 data transfers per
removal of locked transactions and AXI4 also includes burst.
information on the interoperability of components. AMBA AXI4 • A burst with a transfer size of 8, 16, 32, 64, 128, 256,
protocol system supports 16 masters and 16 slaves interfacing. 512 or 1024 bits wide is supported.
This paper presents a work aimed to design the AMBA AXI4 • Updated AWCACHE and ARCACHE signalling
protocol modeled in Verilog hardware description language details.
(HDL) and simulation results for read and write operation of
Each transaction is burst-based which has address
data and address are shown in Verilog compiler simulator (VCS)
tool. The operating frequency is set to 100MHz. Two test cases and control information on the address channel that describes
are run to perform multiple read and multiple write operations. the nature of the data to be transferred. The data is transferred
To perform single read operation module takes 160ns and for between master and slave using a write data channel to the
single write operation it takes 565ns. slave or a read data channel to the master. Table 1[3] gives the
information of signals used in the complete design of the
Keywords- System-on-chip(SoC), Intellactual Property (IP), protocol.
AMBA, AXI, VCS, Verilog. The write operation process starts when the master
sends an address and control information on the write address
I. INTRODUCTION
channel as shown in fig. 1. The master then sends each item of
In recent years due to the miniaturization of semiconductor write data over the write data channel. The master keeps the
process technology and computation for survival in the current VALID signal low until the write data is available. The master
market conditions constant customization is required. The sends the last data item, the WLAST signal goes HIGH. When
semiconductor process technology is changing at a faster pace the slave has accepted all the data items, it drives a write
during 1971 semiconductor process technology was 10µm, response signal BRESP[1:0] back to the master to indicate that
during 2010 the technology is reduced to 32nm and future is the write transaction is complete. This signal indicates the
promising for a process technology with 10nm. Intel, Toshiba status of the write transaction. The allowable responses are
and Samsung have reported that the process technology would OKAY, EXOKAY, SLVERR, and DECERR.
be further reduced to 10nm in the future. So with decreasing After the read address appears on the address bus, the
process technology and increasing consumer design data transfer occurs on the read data channel as shown in fig.
constraints SoC has evolved, where all the functional units of 2. The slave keeps the VALID signal LOW until the read data
a system are modelled on a single chip. is available. For the final data transfer of the burst, the slave
asserts the RLAST signal to show that the last data item is
SoC buses [1] are used to interconnect an Intellectual being transferred. The RRESP[1:0] signal indicates the status
Property (IP) core to the surrounding interface. These are not of the read transfer. The allowable responses are OKAY,
real buses, but they reside in Field Programmable Gate Array EXOKAY, SLVERR, and DECERR.
(FPGA). The AMBA [2] data bus width can be 32, 64, 128 or
256 byte, address bus width will be 32bits wide. The AMBA
AXI4 [3] specification to interconnect different modules in a
SoC was released in March 2010.
A. AMBA AXI4 architecture
AMBA AXI4 [3] supports data transfers up to 256 beats
and unaligned data transfers using byte strobes. In AMBA
AXI4 system 16 masters and 16 slaves are interfaced. Each
master and slave has their own 4 bit ID tags. AMBA AXI4 Figure 1: Write address and data burst.
system consists of master, slave and bus (arbiters and
decoders). The system consists of five channels namely write

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International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882
 Design of AMBA AXI4 protocol for System-on-Chip communication

B. Comparison of AMBA AXI3 and AXI4

AMBA AXI3 protocol has separate address/control
and data phases, but AXI4 has updated write response
requirements and updated AWCACHE and ARCACHE
signaling details. AMBA AXI4 protocol supports for burst
lengths up to 256 beats and Quality of Service (QoS)
signaling. AXI4 has additional information on Ordering
Figure 2: Read address and data burst. requirements and details of optional user signaling. AXI3 has
the ability to issue multiple outstanding addresses and out-of-
TABLE 1: Signal descriptions of AMBA AXI4 protocol. order transaction completion, but AXI4 has the ability of
Source: removal of locked transactions and write interleaving. One
Input/
Signal master/ Description
slave
Output major up-dation seen in AXI4 is that, it includes information
Global clock on the use of default signaling and discusses the
Aclk Global Input
signal. interoperability of components which can’t be seen in AXI3.
AResetn Global Input Global reset signal In this paper features of AMBA AXI4 listed above
AWID[3:0] Master Input Write address ID.
are designed and verified. The rest of the paper is organized as
AWADDR[31:0] Master Input Write address.
AWLEN[3:0] Master Input Write burst length. follows: Section 2 discusses related work. Section 3 of this
AWSIZE[2:0] Master Input Write burst size. paper, discusses proposed work. In Section 4, simulation
AWBURST[1:0] Master Input Write burst type. parameters are discussed. Section 5 discusses results. Future
AWLOCK[1:0] Master Input Write lock type. scope and concluding remarks are given in Section 6.
AWCACHE[3:0] Master Input Write cache type.
Write protection II. RELATED WORK
AWPROT[2:0] Master Input
type.
WDATA[31:0] Master Input Write data. In a SoC, it houses many components and electronic
ARID[3:0] Master Input Read address ID. modules, to interconnect these a bus is necessary. There are
ARADDR[31:0] Master Input Read address. many buses introduced in the due course some of them being
ARLEN[3:0] Master Input Read Burst length. AMBA [2] developed by ARM, CORE CONNECT [4]
ARSIZE[2:0] Master Input Read Burst size.
ARLOCK[1:0] Master Input Read Lock type.
developed by IBM, WISHBONE [5] developed by Silicore
ARCACHE[3:0] Master Input Read Cache type. Corporation, etc. Different buses have their own properties the
Read Protection designer selects the bus best suited for his application.
ARPROT[2:0] Master Input
type. The AMBA bus was introduced by ARM Ltd in 1996
RDATA[31:0] Master Input Read data. which is a registered trademark of ARM Ltd. Later advanced
WLAST Master Input Write last.
RLAST Slave Output Read last.
system bus (ASB) and advanced peripheral bus (APB) were
Write address released in 1995, AHB in 1999, and AXI in 2003[6].
AWVALID Master Output
valid. AMBA bus finds application in wide area. AMBA
Write address AXI bus is used to reduce the precharge time using dynamic
AWREADY Slave Output
ready. SDRAM access scheduler (DSAS) [7]. Here the memory
WVALID Master Output Write valid.
RAVLID Slave Output Read valid.
controller is capable of predicting future operations thus
WREADY Slave Output Write ready. throughput is improved.
Write Response Efficient Bus Interface (EBI) [8] is designed for
BID[3:0] Slave Output
ID. mobile systems to reduce the required memory to be
RID[3:0] Slave Output Read response ID. transferred to the IP, through AMBA3 AXI. The advantages of
BRESP[1:0] Slave Output Write response.
RRESP[1:0] Slave Output Read response.
introducing Network-on-chip (NoC) within SoC such as
Write response quality of signal, dynamic routing, and communication links
BVALID Slave Output
valid. was discussed in [9].
BREADY Master Output Response ready. To verify on-chip communication properties rule based
RVALID Slave Output Read valid. synthesizable AMBA AXI protocol checker [10] is used.
The protocol supports 16 outstanding transactions, so
each read and write transactions have ARID[3:0] and AWID III. PROPOSED WORK
[3:0] tags respectively. Once the read and write operation gets The work carried out in this project is the achievement of
completed the module produces a RID[3:0] and BID[3:0] tags. communication between one master and one slave. AMBA
If both the ID tags match, it indicates that the module has AXI4 slave is designed with operating frequency of 100MHz,
responded to right operation of ID tags. ID tags are needed for which gives each clock cycle of duration 10ns. To access slave
any operation because for each transaction concatenated input interconnect is needed, hence interconnect signals are also
values are passed to module. studied. Master block functions are assumed to be available
and the slave characteristics are studied. The AMBA AXI4
system components consists of

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International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882
 Design of AMBA AXI4 protocol for System-on-Chip communication

1) Master Pending read address register stores the remaining read

2) AMBA AXI4 Interconnect addresses to be sent; pending write address register which
2.1) Arbiters stores the remaining write addresses to be sent and pending
2.2) Decoders write data register which stores the remaining write data to be
3) Slave sent. The read/write state machines receive internal inputs from
the read/ write buffer. The AXI4 slave test bench initiates the
The master is connected to the interconnect using a slave read or write transaction and the output from the AXI4 slave
interface and the slave is connected to the interconnect using a are standard read/write channel signals. The AXI4 slave
master interface as shown in fig. 3. The AXI4 master gets receives the write data in the same order as address.
connected to the AXI4 slave interface port of the interconnect Signals used to design slave module is shown in fig. 5. The
and the AXI slave gets connected to the AXI4 Master test layer shown in the fig. 5 has 2 test cases. The test case 1:-
interface port of the interconnect. The parallel capability of for multiple read operations and case 2:- for multiple write
this interconnects enables master M1 to access one slave at the operations.
same as master M0 is accessing the other.

Figure 4: AMBA AXI4 slave Read/Write block Diagram.

Figure 3: Block diagram of AMBA AXI4 bus interconnect.

A. AMBA AXI4 master

To perform write address and data operation the
transaction is initiated with concatenated input of [awaddr,
awid, awcache, awlock, awprot, awburst]. On the same lines
for read address and data operations the concatenated input is
[araddr, arid, arcache, arlock, arprot, arburst]. The addresses
of read and write operations are validated by VALID signals
and sent to interface unit.
B. AMBA AXI4 Interconnect
The interconnect block consists of arbiter and decoder.
When two masters initiate a transaction simultaneously, the
arbiter gives priority to access the bus. The decoder decodes
the address sent by master and the control goes to one slave
out of 16. The AMBA AXI interface decoder is centralized
digital block. The decoder decodes the address sent by master
and goes to one slave out of 16. 0-150 locations are meant for Figure 5: Signals used to design AMBA AXI4 interconnect and slave.
slave-1, next 151-300 addressable locations are meant for IV. SIMULATION
slave-2,… and so on till slave-16.
Simulation is being carried out on VCS tool [11] which is
trademark of Synopsys, using Verilog [12] as programming
C. AMBA AXI4 slave read/write block diagram language. The test case is run for multiple operations and the
The AXI4 slave consists of common read/ write buffer waveforms are visible in discovery visualization environment
which stores the read/ write address and data as shown in fig. 4. (DVE).

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International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882
 Design of AMBA AXI4 protocol for System-on-Chip communication

A. Simulation inputs identification tag of the write response. The BID[3:0] value is
To perform multiple write and read operations, the matching with the AWID[3:0] value of the write transaction
concatenated input format and their values passed to invoke a which indicates the slave is responding correctly. BRESP[1:0]
function is shown in the fig. 6 and 7 respectively. Here the signal that is write response signal from slave is 0 which
normal type of the burst is passed to module. Internal_lock indicates OKAY. Simulation result of slave for multiple write
value is 0, internal_burst value is 1 and internal_prot value is data operation is shown in fig. 10.
1,for both read and write operations, which indicate that the
burst is of normal type. For write operation address locations
passed to module are 40, 12, 35, 42 and 102; for read
operations 45, 12, 67 and 98.

Figure 6: Interface declaration and write function invocation.

Figure 8: Simulation result of slave for write address operation.

Figure 7: Interface declaration and read function invocation.

B. Simulation outputs
The simulation output signals generated are as follows:
• From input side the validating signals
AWVALID/ARVALID signals are generated by
Figure 9: Simulation result of slave for single write data operation.
interconnect which gives the information about valid
address and ID tags.
• For write operations BRESP[1:0] response signal
generated from slave indicates the status of the write
transaction. The allowable responses are OKAY,
EXOKAY, SLERR, and DECERR.
• For read operations RLAST signal is raised by slave
for every transaction which indicates the completion
of operation.
V. RESULTS
Simulation is carried out in VCS tool and Verilog is used as
programming language.
A. Simulation result for write operation
Figure 10: Simulation result of slave for multiple write data operation.
The AResetn signal is active low. Master drives the
address, and the slave accepts it one cycle later. B. Simulation result for read operation
The write address values passed to module are 40, 12, 35, The read address values passed to module are 45, 12, 67,
42 and 102 as shown in fig. 8 and the simulated result for 98 as shown in fig. 11 and the simulated result for single read
single write data operation is shown in fig. 9. Input data operation is shown in fig. 12.
AWID[3:0] value is 11 for 40 address location, which is same
as the BID[3:0] signal for 40 address location which is

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International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882
 Design of AMBA AXI4 protocol for System-on-Chip communication

FIXED burst types remain constrained to a maximum burst

length of 16 beats. These are the drawbacks of AMBA AXI4
system which need to be overcome.

B. Conclusion
AMBA AXI4 is a plug and play IP protocol released
by ARM, defines both bus specification and a technology
independent methodology for designing, implementing and
testing customized high-integration embedded interfaces. The
data to be read or written to the slave is assumed to be given
by the master and is read or written to a particular address
Figure 11: Simulation result of slave for read address operation. location of slave through decoder. In this work, slave was
modeled in Verilog with operating frequency of 100MHz and
Input ARID[3:0] value is 3 for 12 address location, which simulation results were shown in VCS tool. To perform single
is same as the RID[3:0] signal for 12 address location which is read operation it consumed 160ns and for single write
identification tag of the write response. The RID[3:0] and operation 565ns.
ARID[3:0] values are matching, which indicates slave has
responded properly. RLAST signal from slave indicates the REFERENCES
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The AMBA AXI4 has limitations with respect to the

burst data and beats of information to be transferred. The burst
must not cross the 4k boundary. Bursts longer than 16 beats
are only supported for the INCR burst type. Both WRAP and

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International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882