Variables

F wire
Ì Connects components together

F reg
Ì Saves a value
Á Part of a behavioral description
Ì Does NOT necessarily become a register when you synthesize
Á May become a wire

F The rule
Ì Declare a variable as reg if it is a target of an assignment statement
Á Continuous assign doesn’t count

CSE467, Sequential Verilog 1

Continuous assignment
F Assignment is continuously evaluated
Ì Corresponds to a connection or a simple component
Ì Target is not a reg variable
Boolean operators
(~ for bit-wise negation)
assign A = X | (Y & ~Z);
bits can assume four values
assign B[3:0] = 4'b01XX; (0, 1, X, Z)

assign C[15:0] = 4'h00ff; variables can be n-bits wide

(MSB:LSB)
assign #3 {Cout, Sum[3:0]} = A[3:0] + B[3:0] + Cin;

arithmetic operator

multiple assignment (concatenation)

Gate delay (only used by simulator, not during synthesis)

CSE467, Sequential Verilog 2

Example: A comparator

module Compare1 (A, B, Equal, Alarger, Blarger);

input A, B;
output Equal, Alarger, Blarger;

assign Equal = (A & B) | (~A & ~B);

assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule

CSE467, Sequential Verilog 3

Comparator example (con’t)
// Make a 4-bit comparator from 4 1-bit comparators

module Compare4(A4, B4, Equal, Alarger, Blarger);

input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3;

Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0);

Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1);
Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2);
Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3);

assign Equal = (e0 & e1 & e2 & e3);

assign Alarger = (Al3 | (Al2 & e3) |
(Al1 & e3 & e2) |
(Al0 & e3 & e2 & e1));
assign Blarger = (~Alarger & ~Equal);
endmodule

CSE467, Sequential Verilog 4

always block
F A procedure that describes a circuit’s function
Ì Can contain multiple statements
Ì Can contain if, for, case
Ì Statements execute sequentially
Á Continuous assignments execute in parallel

F begin/end groups statements

CSE467, Sequential Verilog 5

always example
F always triggers at the specified conditions
Ì Example: A D-type register

module register(Q, D, clock);

input D, clock;
output Q;
reg Q;

always @(posedge clock) begin

Q = D;
end
endmodule

CSE467, Sequential Verilog 6

always example

module and_gate(out, in1, in2); Not a real register!!

input in1, in2; Holds assignment in
always block
output out;
reg out;
The compiler will not use a register
always @(in1 or in2) begin when it synthesizes this gate, because
out = in1 & in2; out changes whenever the inputs
end change. Can omit the module and write
endmodule wire out, in1, in2;
and (out, in1, in2);

specifies when block is executed

i.e. triggered by changes in in1 or in2

CSE467, Sequential Verilog 7

Incomplete trigger or incomplete assignment
F What if you omit an input trigger (e.g. in2)
Ì Compiler will insert a register to hold the state
Á Becomes a sequential circuit — NOT what you want

module and_gate (out, in1, in2);

input in1, in2;
output out;
reg out;

always @(in1) begin

out = in1 & in2;
end 2 rules:
1) Include all inputs in the trigger list
endmodule
2) Use complete assignments
fi Every path must lead to an assignment for out
fi Otherwise out needs a state element

CSE467, Sequential Verilog 8

A better way...
F Use functions for complex combinational logic
Ì Functions can’t have state
module and_gate (out, in1, in2);
input in1, in2;
output out;

assign out = myfunction(in1, in2);

function myfunction;
input in1, in2;
Benefits:
begin
Functions force a result
myfunction = in1 & in2;
fi Compiler will fail if function does not
end
generate a result
endfunction
If you build a function wrong, the circuit
will not synthesize
endmodule
fi If you build an always block wrong,
you get a register
CSE467, Sequential Verilog 9
if
F Same as C if statement
Ì Single if statements synthesize to multiplexers
Ì Nested if /else statements usually synthesize to logic
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel == 2’b00) Y = A;
else if (sel == 2’b01) Y = B;
else if (sel == 2’b10) Y = C;
else if (sel == 2’b11) Y = D;

endmodule
CSE467, Sequential Verilog 10
if: Another way

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel[0] == 0)
if (sel[1] == 0) Y = A;
else Y = B;
else
if (sel[1] == 0) Y = C;
else Y = D;
endmodule

CSE467, Sequential Verilog 11

case
F Sequential execution
Ì Executes only first case that matches (don’t need a break)
Ì case statements synthesizes to multiplexers

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
case (sel)
2’b00: Y = A;
2’b01: Y = B;
2’b10: Y = C;
2’b11: Y = D;
endcase
endmodule

CSE467, Sequential Verilog 12

case: A better way
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;

assign out = mymux(sel, A, B, C, D);

function mymux;
input [1:0] sel, A, B, C, D;
begin
case (sel)
2’b00: mymux = A;
2’b01: mymux = B;
2’b10: mymux = C;
2’b11: mymux = D;
endcase
end
Note: You can define a function in a file
endfunction
endmodule Then include it into your Verilog module

CSE467, Sequential Verilog 13

default case
// Simple binary encoder (input is 1-hot)
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (A)
8’b00000001: Y = 0; If you omit the default, the compiler will create
8’b00000010: Y = 1; a latch for Y
8’b00000100: Y = 2; fi Or you can list all 256 cases
8’b00001000: Y = 3; Better way: Use a function
8’b00010000: Y = 4; fi Compiler will warn you of missing cases
8’b00100000: Y = 5;
8’b01000000: Y = 6;
8’b10000000: Y = 7;
default: Y = 3’bx; // Don’t care when input isnt 1-hot
endcase
endmodule

CSE467, Sequential Verilog 14

case (con’t)
// Priority encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (1’b1)
A[0]: Y = 0;
A[1]: Y = 1; Case statements execute sequentially
A[2]: Y = 2;
A[3]: Y = 3;
fi Take the first alternative that matches
A[4]: Y = 4;
A[5]: Y = 5;
A[6]: Y = 6;
A[7]: Y = 7;
default: Y = 3’bx; // Don’t care when input is all 0’s
endcase
endmodule

CSE467, Sequential Verilog 15

casez and casex
// 2-bit priority encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [1:0] Y; // 3-bit encoded output
reg [1:0] Y; // target of assignment

always @(A)
casez (A)
8’bzzzz0001: Y = 0;
8’bzzzz0010: Y = 1;
8’bzzzz0100: Y = 2;
8’bzzzz1000: Y = 3;
default: Y = 2’bx; // Don’t care when input isnt 1-hot
endcase
endmodule

casez: alternatives can include z

fi z bits are not used in the evaluation

CSE467, Sequential Verilog 16

casex example
// Priority encoder
module encode (A, valid, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
output valid; // Asserted when an input is not all 0’s
reg [2:0] Y; // target of assignment
reg valid;

always @(A) begin

valid = 1;
casex (A)
8’bXXXXXXX1: Y = 0;
8’bXXXXXX10: Y = 1; casex: alternatives can include x and z
8’bXXXXX100: Y = 2;
8’bXXXX1000: Y = 3; fi x and z bits are not used in the evaluation
8’bXXX10000: Y = 4;
8’bXX100000: Y = 5;
8’bX1000000: Y = 6;
8’b10000000: Y = 7;
default: begin
valid = 0;
Y = 3’bx; // Don’t care when input is all 0’s
end
endcase
end
endmodule
CSE467, Sequential Verilog 17
for
// simple encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

integer i; // Temporary variables for program only

reg [7:0] test;

always @(A) begin

test = 8b’00000001;
Y = 3’bx;
for (i = 0; i < 8; i = i + 1) begin
if (A == test) Y = i;
test = test << 1; // Shift left, pad with 0s
end
end
endmodule
for statements synthesize as cascaded
combinational logic
fi Verilog unrolls the loop

CSE467, Sequential Verilog 18

Sequential Verilog
F Sequential circuits: Registers & combinational logic
Ì We will use positive edge-triggered registers
Á Avoid latches and negative edge-triggered registers

F Register is triggered by “posedge clk”

module register(Q, D, clock);
input D, clock;
output Q;
reg Q;

always @(posedge clock) begin

Q = D;
end
endmodule

CSE467, Sequential Verilog 19

8-bit register with synchronous reset

module reg8 (Q, reset, CLK, D);

input reset;
input CLK;
input [7:0] D;
output [7:0] Q;
reg [7:0] Q;

always @(posedge CLK)

if (reset)
Q = 0;
else
Q = D;

endmodule // reg8

CSE467, Sequential Verilog 20

N-bit register with asynchronous reset
module regN (Q, reset, CLK, D);
input reset;
input CLK;
parameter N = 8; // Allow N to be changed
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;

always @(posedge CLK or posedge reset)

if (reset)
Q = 0;
else if (CLK == 1)
Q = D;

endmodule // regN Parameters are constants

fi Not variables
fi Parameter values are inserted at compile time

CSE467, Sequential Verilog 21

Shift-register
// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted

module shiftReg (CLK, clr, shift, ld, Din, SI, Dout);

input CLK;
input clr; // clear register
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output [7:0] Dout;
reg [7:0] Dout;

always @(posedge CLK) begin

if (clr) Dout <= 0;
else if (ld) Dout <= Din;
else if (shift) Dout <= { Dout[6:0], SI };
end

endmodule // shiftReg

CSE467, Sequential Verilog 22

Blocking and non-blocking assignments
F Blocking assignments (Q = A)
Ì Variable is assigned immediately
Á New value is used by subsequent statements

F Non-blocking assignments (Q <= A)

Ì Variable is assigned after all scheduled statements are executed
Á Value to be assigned is computed but saved for later
Ì Usual use: Register assignment
Á Registers simultaneously take new values after the clock edge

F Example: Swap
always @(posedge CLK) always @(posedge CLK)
begin begin
temp = B; A <= B;
B = A; B <= A;
A = temp; end
end

CSE467, Sequential Verilog 23

Swap (cont’d)
F The following code executes incorrectly
Ì One block executes first
Ì Loses previous value of variable
always @(posedge CLK) always @(posedge CLK)
begin begin
A = B; B = A;
end end

F Non-blocking assignment fixes this

Ì Both blocks are scheduled by posedge CLK
always @(posedge CLK) always @(posedge CLK)
begin begin
A <= B; B <= A;
end end

CSE467, Sequential Verilog 24

Non-blocking assignment
F Non-blocking assignment is also known as RTL assignment
Ì If used in an always block triggered by a clock edge
Ì Mimics register-transfer–level semantics: All flip-flops change together
// this implements 3 parallel flip-flops
always @(posedge clk)
begin
B = A; // this implements a shift register
D = C; always @(posedge clk)
F = E; begin
end {D, C, B} = {C, B, A};
end
// this implements a shift register
always @(posedge clk)
begin
B <= A;
C <= B;
D <= C;
end

CSE467, Sequential Verilog 25

Counter

// 8-bit counter with clear and count enable controls

module count8 (CLK, clr, cntEn, Dout);
input CLK;
input clr; // clear counter
input cntEn; // enable count
output [7:0] Dout; // counter value
reg [7:0] Dout;

always @(posedge CLK)

if (clr) Dout <= 0;
else if (cntEn) Dout <= Dout + 1;

endmodule

CSE467, Sequential Verilog 26