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DSD Lab (CEN-422) : Spring 2021

The document discusses procedural assignments in Verilog, which assign values to registers or variables under certain conditions. It explains that procedural assignments must be encapsulated in procedural blocks like "always" blocks. The document provides examples of using blocking and non-blocking assignments in Verilog code for sequential circuits. It also outlines four tasks to implement different examples of sequential circuits using procedural assignments in Verilog.

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25 views31 pages

DSD Lab (CEN-422) : Spring 2021

The document discusses procedural assignments in Verilog, which assign values to registers or variables under certain conditions. It explains that procedural assignments must be encapsulated in procedural blocks like "always" blocks. The document provides examples of using blocking and non-blocking assignments in Verilog code for sequential circuits. It also outlines four tasks to implement different examples of sequential circuits using procedural assignments in Verilog.

Uploaded by

Wasif Ijaz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DSD lab (CEN-422)

Spring 2021
AMNA WAHEED
DEPARTMENT OF COMPUTERS ENGINEERING, BUIC
Lab 05: Implementing
Sequential Circuits in
Verilog
Procedural assignment
 Procedural assignment assigns values to registers or variables under a certain
condition.
 The RHS of the assignment change multiple times, the LHS will only update
when this condition is met.
 In synchronous sequential circuits, this condition will most likely be the
changing edge of clock, but it doesn’t have to be
 The register or variable will then hold its value until this condition is met again
 In Verilog, procedural assignments must be encapsulated in procedural blocks
of code
Procedural Blocks– Always
 reg a
always @(posedge clk)
begin

end
Procedural Blocks - Always
always @ (sensitivity list)

begin
….. do something….
end
Procedural blocks--Always
always @ (posedge clk) always @ (b)
begin begin
a < = ~a; a < = b;
end b < = c;
end
always @ (negedge rst_n)
begin
a < = 1’b 00;
end
Procedural blocks--Always
Procedural Blocks- Rules
Procedural Blocks- Rules
Procedural Blocks- Rules
Initial statement
Example
Output
There are two types of Procedural
statements
 Blocking statements
 Non-Blocking statements
Non-blocking assignments
Blocking/ Non-blocking assignments
Blocking assignments
Blocking/ Non-blocking assignments
Blocking and non-blocking
assignments
Application of non-blocking
assignments
Task 1
GENERATE A CLOCK WHOSE LOW AND HIGH TIME CHANGES AFTER EVERY 50 TIME UNITS.
Next Tasks
Implement all examples one by one.
Example 1
Verilog code
module Task01(reg1, reg2, reg3, in1, in2, in3, clock);
input in1, in2, in3, clock;
output reg1, reg2, reg3;
reg reg1, reg2, reg3;

// Blocking assignment
always @(posedge clock)
begin
reg1 = #1 in1;
reg2 = @(negedge clock) in2 ^ in3;
reg3 = #1 reg1;
end

endmodule
//Test_bench

module tb_Task01();
initial
reg in1, in2, in3, clock;
begin
wire reg1, reg2, reg3;
in1 = 1'b1;
in2 = 1'b0;
Task01 a1(reg1, reg2, reg3, in1, in2, in3, clock);
in3 = 1'b1;
end
initial
clock=1'b0;
initial
#1000 $finish;
always
#10 clock = ~clock;

endmodule
Example 2
Example 3
always @(negedge clk)
begin
a1 <= #5 in1;
a2 <= #10 in2^in3;
a3<= @(posedge clk ) a2;
a4 <=#1 in1;
end
endmodule
module assigment(x,y,z,b1,b2,b3,clock);

Example 4 input x,y,z,clock;


output [2:0] b1,b2,b3;
reg [2:0] b2;
reg [2:0] b3;
initial
begin
#10 b3 ={x,y,z};
end
always @(posedge clock)
b2= {x,y,z};
assign b1= {x,y,z};
wire [2:0] b1,b2,b3;

reg x,y,z,clock;
Test bench
assigment a1(x,y,z,b1,b2,b3,clock);

initial

clock =1'b0;

always

# 10 clock =~clock;

initial begin

x=0; y=1;z=1;

#10 x=1;

y=0;

z=0;

#20 x=1;

y=0;

z=1;

end

initial

#1000 $finish;
Output

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