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Sync Vs Async Resets

Reset is used to force the hardware design into a known state for simulation. Asynchronous Resets can be used to correct a hardware design for system operation. Synchronous resets make a circuit completely synchronous.

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171 views4 pages

Sync Vs Async Resets

Reset is used to force the hardware design into a known state for simulation. Asynchronous Resets can be used to correct a hardware design for system operation. Synchronous resets make a circuit completely synchronous.

Uploaded by

n.tarakaram9414
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Asynchronous Resets vs Synchronous Resets

The primary purpose of reset is to


-force the ASIC design into a known state for simulation.
-correctly initialize a hardware design for system operation

-For simulation purposes it is advantageous to have reset applied to all


elements that have state.

Synchronous resets - Basic idea


-Based on the premise that the reset signal will only affect or reset the
state of the flip-flop on the active edge of the clock.

-Reset is applied as is any other input to the state machine.

D Q
combinatorial output
input0 logic cloud
input0
reset
D Q

clk

A synchronous reset is applied to


the logic cloud as the inputs are

Synchronous and Asynchronous Resets 1


Synchronous resets - Advantages
-Since the flip-flop has less functionality, it is smaller.

-But the added combinatorial logic grows and may cancel out the benefit.

-With the availability of gates today, does it make any difference?

-Synchronous resets make a circuit completely synchronous.

-Synchronous resets provide some filtering for the reset line such that
it is not effected by glitches unless they occur right at the clock edge.

-The reset buffer tree may be pipelined to keep all the resets occurring
within the same clock cycle.

Synchronous resets - Disadvantages


-May need a pulse stretcher to guarantee that a reset pulse is wide enough
to be present during a clock rising edge.

-Requires a clock to be present if reset is to occur. If internal


tri-state buffers are present a separate asynchronous reset may still
be required to prevent bus contention.

-Unless care is taken with logic synthesis, the reset signal may take the fastest path to the
D input making worse case timing hard to meet.

logic
cloud
D Q
logic output
input0 cloud’
input0

reset D Q

clk

Sometimes reset can get the fastest path!

Synchronous and Asynchronous Resets 2


Asynchronous Resets
-Reset has priority over any other signal. When asserted, reset occurs no matter what.

-Biggest problem is not assertion but deassertion of reset.

-Must be added to sensitivity list.

Asynchronous resets - Advantages


-Data paths are always clean, clear of clutter for reset signals.

-Higher speeds may be possible at the cutting edge.

-Circuits can be reset without clock present.

-Usually no coercion of tools needed for correct synthesis.

Asynchronous resets - Disadvantages


-Deactivation of reset to all flip-flops must occur within less than
a clock cycle. How much less is dependent on the reset recovery time.

-No filtering of reset line is available for inputs coming directly from

Synchronous and Asynchronous Resets 3


external reset pins. A solution is possible however. See below.

-Reset synchronization circuit is required on ASICs with asynchronous reset!

-Circuit shown will provide asynchronous reset and synchronous deassertion.

-These flip-flops must be kept out of the DFT scan chain.

Vdd
D Q D Q master_reset_n

reset_n_dly R R
clk
delay flt_reset_n
reset_n
reset glitch filter

Reset Distribution Tree


-Routing and buffering of the reset tree is almost as critical as the clock
tree.

-However the allowed skew is greater because it is only necessary for reset
to be removed sometime prior to the next clock edge.

Synchronous and Asynchronous Resets 4

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