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SCL Logic Synthesis Report

This document contains area, timing, power, and constraint reports for a design called newmodfinal. It provides key details such as: 1. The design has 1997 cells including 1352 combinational and 552 sequential cells. Total cell area is 56370.719965. 2. The critical path has a slack of 232.79 ns, meeting the required time of 236.65 ns. It goes from clock clk to output y. 3. Total dynamic power is 72.2860 uW and leakage power is 77.4281 nW. Register cells use 91.35% of internal power. 4. The constraint file defines I/O and clock constraints including

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Aishwarya a nair
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4K views10 pages

SCL Logic Synthesis Report

This document contains area, timing, power, and constraint reports for a design called newmodfinal. It provides key details such as: 1. The design has 1997 cells including 1352 combinational and 552 sequential cells. Total cell area is 56370.719965. 2. The critical path has a slack of 232.79 ns, meeting the required time of 236.65 ns. It goes from clock clk to output y. 3. Total dynamic power is 72.2860 uW and leakage power is 77.4281 nW. Register cells use 91.35% of internal power. 4. The constraint file defines I/O and clock constraints including

Uploaded by

Aishwarya a nair
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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AREA REPORT:

****************************************
Report : area
Design : newmodfinal
Version: O-2018.06-SP4
Date : Mon Jan 28 11:21:46 2019

Library(s) Used:

tsl18fs120_scl_ff (File:
/home/synopsys/pdk/scl_pdk/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120
_scl_ff.db)

Number of ports: 433


Number of nets: 2338
Number of cells: 1997
Number of combinational cells: 1352
Number of sequential cells: 552
Number of macros/black boxes: 0
Number of buf/inv: 239
Number of references: 55

Combinational area: 22837.419923


Buf/Inv area: 1708.599994
Noncombinational area: 33533.300041
Macro/Black Box area: 0.000000
Net Interconnect area: 1488.695276

Total cell area: 56370.719965


Total area: 57859.415240
TIMING REPORT:

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : newmodfinal
Version: O-2018.06-SP4
Date : Mon Jan 28 11:21:46 2019
****************************************

Operating Conditions: tsl18fs120_scl_ff Library: tsl18fs120_scl_ff


Wire Load Model Mode: segmented

Startpoint: a3/clk1_reg
(rising edge-triggered flip-flop clocked by clk)
Endpoint: y (output port clocked by clk)
Path Group: clk
Path Type: max

Des/Clust/Port Wire Load Model Library


------------------------------------------------
newmodfinal 8000 tsl18fs120_scl_ff
newrom 4000 tsl18fs120_scl_ff

Point Incr Path


-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 1.00 1.00
a3/clk1_reg/CP (dfnrq1) 0.00 1.00 r
a3/clk1_reg/Q (dfnrq1) 0.43 1.43 r
U1166/Z (mx02d1) 0.19 1.62 f
U1372/ZN (inv0d0) 0.35 1.97 r
U1517/ZN (nd03d0) 0.12 2.09 f
U1518/ZN (inv0d0) 1.01 3.10 r
U1587/ZN (aoi22d1) 0.06 3.16 f
U1588/ZN (nd04d0) 0.14 3.30 r
U1589/ZN (aoi22d1) 0.06 3.36 f
U1590/ZN (oaim31d1) 0.05 3.41 r
U1591/ZN (aon211d1) 0.04 3.44 f
U1592/ZN (aon211d1) 0.05 3.50 r
U1594/ZN (aoi22d1) 0.06 3.55 f
U1595/ZN (inv0d0) 0.12 3.67 r
U1596/ZN (nd02d0) 0.12 3.79 f
U1601/ZN (oai21d1) 0.06 3.86 r
y (out) 0.00 3.86 r
data arrival time 3.86
clock clk (rise edge) 520.80 520.80
clock network delay (ideal) 1.00 521.80
clock uncertainty -0.15 521.65
output external delay -285.00 236.65
data required time 236.65
-----------------------------------------------------------
data required time 236.65
data arrival time -3.86
-----------------------------------------------------------
slack (MET) 232.79

POWER REPORT:

****************************************
Report : power
-analysis_effort low
Design : newmodfinal
Version: O-2018.06-SP4
Date : Mon Jan 28 11:21:46 2019
****************************************

Library(s) Used:

tsl18fs120_scl_ff (File:
/home/synopsys/pdk/scl_pdk/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120
_scl_ff.db)

Operating Conditions: tsl18fs120_scl_ff Library: tsl18fs120_scl_ff


Wire Load Model Mode: segmented

Design Wire Load Model Library


------------------------------------------------
newmodfinal 8000 tsl18fs120_scl_ff
newrom 4000 tsl18fs120_scl_ff

Global Operating Voltage = 1.98


Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1pW

Cell Internal Power = 67.6784 uW (94%)


Net Switching Power = 4.6076 uW (6%)
---------
Total Dynamic Power = 72.2860 uW (100%)

Cell Leakage Power = 77.4281 nW

Internal Switching Leakage


Total
Power Group Power Power Power
Power ( % ) Attrs
----------------------------------------------------------------------
----------------------------
io_pad 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
register 6.5740e-02 3.1037e-04 5.5079e+04
6.6106e-02 ( 91.35%)
sequential 1.8500e-05 0.0000 104.8000
1.8684e-05 ( 0.03%)
combinational 1.9198e-03 4.2972e-03 2.2245e+04
6.2392e-03 ( 8.62%)
----------------------------------------------------------------------
----------------------------
Total 6.7678e-02 mW 4.6077e-03 mW 7.7428e+04 pW
7.2363e-02 mW

CONSTRAINT FILE :
set sdc_version 2.0
create_clock -period 520.8 [get_ports clk]
set_clock_latency -source -max 0.7 [get_clocks clk]
set_clock_latency -max 0.3 [get_clocks clk]
set_clock_uncertainty -setup 0.15 [get_clocks clk]
set_clock_transition 0.12 [get_clocks clk]

set_input_delay -max 208.32 -clock clk [get_ports data_in]


set_input_delay -max 208.32 -clock clk [get_ports enable]
set_input_delay -max 208.32 -clock clk [get_ports reset]

set_output_delay -max 234.36 -clock clk [get_ports sel]


set_output_delay -max 234.36 -clock clk [get_ports j]
set_output_delay -max 234.36 -clock clk [get_ports k]
set_output_delay -max 234.36 -clock clk [get_ports en]

set_output_delay -max 234.36 -clock clk [get_ports data_bits]


set_output_delay -max 234.36 -clock clk [get_ports trcal]
set_output_delay -max 234.36 -clock clk [get_ports rtcal]
set_output_delay -max 234.36 -clock clk [get_ports data]

set_output_delay -max 234.36 -clock clk [get_ports op_code_ready]


set_output_delay -max 234.36 -clock clk [get_ports data_ready]
set_output_delay -max 234.36 -clock clk [get_ports op_code]
set_output_delay -max 234.36 -clock clk [get_ports counter]

set_output_delay -max 234.36 -clock clk [get_ports load]


set_output_delay -max 234.36 -clock clk [get_ports op_code_counter]
set_output_delay -max 234.36 -clock clk [get_ports sid]

set_output_delay -max 234.6 -clock clk [get_ports count]


set_output_delay -max 234.36 -clock clk [get_ports sq]
set_output_delay -max 234.36 -clock clk [get_ports out]
set_output_delay -max 234.36 -clock clk [get_ports cq]
set_output_delay -max 234.36 -clock clk [get_ports crc5]
set_output_delay -max 234.36 -clock clk [get_ports crc16]
set_output_delay -max 234.36 -clock clk [get_ports clk1]
set_output_delay -max 234.36 -clock clk [get_ports y]
set_output_delay -max 234.36 -clock clk [get_ports t]
AREA REPORT:
Library(s) Used:

tcb018gbwp7ttc (File:
/home/synopsys/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcb0
18gbwp7t_270a/tcb018gbwp7ttc.db)

Number of ports: 433


Number of nets: 2134
Number of cells: 1960
Number of combinational cells: 1400
Number of sequential cells: 552
Number of macros/black boxes: 0
Number of buf/inv: 271
Number of references: 59

Combinational area: 17047.922966


Buf/Inv area: 1791.283173
Noncombinational area: 23310.829090
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)

Total cell area: 40358.752056


Total area: undefined

CONSTRAINT REPORT:
****************************************
Report : constraint
Design : newmodfinal
Version: O-2018.06-SP4
Date : Tue Feb 26 13:17:05 2019
****************************************

Weighted
Group (max_delay/setup) Cost Weight Cost
-----------------------------------------------------
clk 0.00 1.00 0.00
default 0.00 1.00 0.00
-----------------------------------------------------
max_delay/setup 0.00

Total Neg Critical


Group (critical_range) Slack Endpoints Cost
-----------------------------------------------------
clk 0.00 0 0.00
default 0.00 0 0.00
-----------------------------------------------------
critical_range 0.00

Weighted
Group (min_delay/hold) Cost Weight Cost
-----------------------------------------------------
clk (no fix_hold) 0.00 1.00 0.00
default 0.00 1.00 0.00
-----------------------------------------------------
min_delay/hold 0.00
Constraint Slack
----------------------------------------------------
max_leakage_power -128.71 (VIOLATED)

Constraint Cost
-----------------------------------------------------
max_transition 0.00 (MET)
max_capacitance 0.00 (MET)
max_delay/setup 0.00 (MET)
sequential_clock_pulse_width 0.00 (MET)
critical_range 0.00 (MET)
max_leakage_power 128.71 (VIOLATED)

TIMING REPORT

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : newmodfinal
Version: O-2018.06-SP4
Date : Tue Feb 26 13:17:05 2019
****************************************

Operating Conditions: NCCOM Library: tcb018gbwp7ttc


Wire Load Model Mode: segmented

Startpoint: a3/clk1_reg
(rising edge-triggered flip-flop clocked by clk)
Endpoint: y (output port clocked by clk)
Path Group: clk
Path Type: max

Des/Clust/Port Wire Load Model Library


------------------------------------------------
newmodfinal ZeroWireload tcb018gbwp7ttc
newrom ZeroWireload tcb018gbwp7ttc

Point Incr Path


-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 1.00 1.00
a3/clk1_reg/CP (DFQD0BWP7T) 0.00 1.00 r
a3/clk1_reg/Q (DFQD0BWP7T) 0.30 1.30 f
U1863/ZN (INVD0BWP7T) 0.32 1.62 r
U1306/Z (MUX2D0BWP7T) 0.41 2.03 r
U1342/ZN (INVD0BWP7T) 0.11 2.14 f
U1992/ZN (NR3D0BWP7T) 0.44 2.57 r
U2069/ZN (AOI22D0BWP7T) 0.11 2.68 f
U2072/ZN (ND4D0BWP7T) 0.11 2.79 r
U2073/ZN (AOI22D0BWP7T) 0.08 2.87 f
U2074/ZN (OAI222D0BWP7T) 0.24 3.10 r
U2075/ZN (OAI32D0BWP7T) 0.13 3.24 f
U2079/ZN (AOI22D0BWP7T) 0.12 3.35 r
y (out) 0.00 3.35 r
data arrival time 3.35

clock clk (rise edge) 520.80 520.80


clock network delay (ideal) 1.00 521.80
clock uncertainty -0.15 521.65
output external delay -234.36 287.29
data required time 287.29
-----------------------------------------------------------
data required time 287.29
data arrival time -3.35
-----------------------------------------------------------
slack (MET) 283.94

POWER REPORT
****************************************
Report : power
-analysis_effort low
Design : newmodfinal
Version: O-2018.06-SP4
Date : Tue Feb 26 13:17:05 2019
****************************************

Library(s) Used:
tcb018gbwp7ttc (File:
/home/synopsys/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcb0
18gbwp7t_270a/tcb018gbwp7ttc.db)

Operating Conditions: NCCOM Library: tcb018gbwp7ttc


Wire Load Model Mode: segmented

Design Wire Load Model Library


------------------------------------------------
newmodfinal ZeroWireload tcb018gbwp7ttc
newrom ZeroWireload tcb018gbwp7ttc

Global Operating Voltage = 1.8


Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1nW

Cell Internal Power = 95.7206 uW (99%)


Net Switching Power = 1.2421 uW (1%)
---------
Total Dynamic Power = 96.9626 uW (100%)

Cell Leakage Power = 119.5342 nW

Internal Switching Leakage


Total
Power Group Power Power Power
Power ( % ) Attrs
----------------------------------------------------------------------
----------------------------
io_pad 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000
0.0000 ( 0.00%)
register 9.4165e-02 7.2088e-05 71.8484
9.4309e-02 ( 97.14%)
sequential 1.6244e-05 0.0000 0.1413
1.6421e-05 ( 0.02%)
combinational 1.5393e-03 1.1700e-03 47.5445
2.7568e-03 ( 2.84%)
----------------------------------------------------------------------
----------------------------
Total 9.5721e-02 mW 1.2421e-03 mW 119.5342 nW
9.7082e-02 mW

Comparisons of Various of Library:

Library Saed90nm SCL Library TSMC Library


Area 28455.820737 57859.415240 undefined
Dynamic Power 1.0577uW 72.2860 uW 96.9626 uW
Slack 285.72 32.79 283.94
Supply Voltage 1.2 V 1.8V 1.8V

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