EX.

NO: DESIGN ENTRY, SIMULATION AND IMPLEMENTATION OF

AIM:
To design, Simulate and Implement STATEMACHINE using XILINX ISE Software
and FPGA Board.

TOOLS REQUIRED:
1. Personal Computer
2. XILINX Software
3. FPGA Spartan-3E Starter Board(XC3S250E TQ144)

PROCEDURE
1. Open xilinx and create new project.
2. Add source and select state diagram, add state machine diagram.
3. Set shape as geometric and add transitions for every state.
4. In every transitions of the state double click it and edit the condition.
5. Edit the condition for input and output.
6. Save the state diagram and click generate HDL.
7. Add source and add the saved diagram and the program is generated.
8. And we can do further simulation using Xilinx Software.

STATE DIAGRAM(STATEMACHINE):

Reg.No:61072112113
SIMULATION PROGRAM(STATE MACHINE):

module machine1(CLK,RESET,xin,z);
input CLK;
input RESET,xin;
output z;
reg z,next_z;
reg STATE0,next_STATE0,STATE1,next_STATE1;

always @(posedge CLK)

always @ (RESET or STATE0 or STATE1 or xin)

if ( ~xin & STATE0 | xin & STATE1 | RESET ) next_STATE0=1;

if ( ~RESET & xin & STATE0 | ~RESET & ~xin & STATE1 )
next_STATE1=1;
else next_STATE1=0;

if ( ~RESET & xin & STATE0 | ~RESET & ~xin & STATE1 ) next_z=1;
else next_z=0;
end
endmodule

Reg.No:61072112113
RTL SCHEMATIC(STATE MACHINE):

TECHNOLOGY SCHEATIC(STATE MACHINE):

Reg.No:61072112113
SYNTHESIS SUMMARY(STATE MACHINE):
Device utilization summary:

---------------------------

Selected Device : 3s500efg320-4

Number of Slices: 1 out of 4656 0%

Number of Slice Flip Flops: 2 out of 9312 0%

Number of IOs: 4

Number of bonded IOBs: 4 out of 232 1%

Number of GCLKs: 1 out of 24 4%

---------------------------

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

Reg.No:61072112113
------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

CLK | BUFGP |2 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

Minimum period: 1.346ns (Maximum Frequency: 742.942MHz)

Minimum input arrival time before clock: 2.576ns

Maximum output required time after clock: 4.310ns

Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default period analysis for Clock 'CLK'

Clock period: 1.346ns (frequency: 742.942MHz)

Total number of paths / destination ports: 2 / 2

Reg.No:61072112113
-------------------------------------------------------------------------

Delay: 1.346ns (Levels of Logic = 0)

Source: z (FF)

Destination: STATE0 (FF)

Source Clock: CLK rising

Destination Clock: CLK rising

Data Path: z to STATE0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDRE:C->Q 2 0.591 0.447 z (STATE1)

FDSE:D 0.308 STATE0

----------------------------------------

Total 1.346ns (0.899ns logic, 0.447ns route)

(66.8% logic, 33.2% route)

=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'

Total number of paths / destination ports: 4 / 4

-------------------------------------------------------------------------

Offset: 2.576ns (Levels of Logic = 1)

Source: RESET (PAD)

Destination: z (FF)

Destination Clock: CLK rising

Data Path: RESET to z

Gate Net

Reg.No:61072112113
 Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 2 1.218 0.447 RESET_IBUF (RESET_IBUF)

FDRE:R 0.911 z

----------------------------------------

Total 2.576ns (2.129ns logic, 0.447ns route)

(82.6% logic, 17.4% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------

Offset: 4.310ns (Levels of Logic = 1)

Source: z (FF)

Destination: z (PAD)

Source Clock: CLK rising

Data Path: z to z

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDRE:C->Q 2 0.591 0.447 z (STATE1)

OBUF:I->O 3.272 z_OBUF (z)

----------------------------------------

Total 4.310ns (3.863ns logic, 0.447ns route)

(89.6% logic, 10.4% route)

=========================================================================

Reg.No:61072112113
Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 4.44 secs

-->

Total memory usage is 4497404 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 1 ( 0 filtered)

Reg.No:61072112113
SIMULATION OUTPUT:

RESULT:
Thus Statemachine is designed and Simulation is done using XILINX ISE
Software and Implementation is done using FPGA Spartan-3E Starter Board.

Reg.No:61072112113