3.

MOS TWO INPUT NOR GATE

AIM: Design and verification of two input NOR gate operation using cmos implementation.

THEORY:

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its
transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors
connected to Vdd and two series-connected sinking (lower) transistors connected to ground,
the NOR gate uses two series-connected sourcing transistors and two parallel-connected
sinking transistors like this:

Fig 4.1: 2-input CMOS NOR gate

As with the NAND gate, transistors Q1 and Q3 work as a complementary pair, as do transistors
Q2 and Q4. Each pair is controlled by a single input signal. If either input A or input B are “high”
(1), at least one of the lower transistors (Q3 or Q4) will be saturated, thus making the output
“low” (0). Only in the event of both inputs being “low” (0) will both lower transistors be in cut
off mode and both upper transistors be saturated, the conditions necessary for the output to go
“high” (1). This behaviour, of course, defines the NOR logic function.
TRUTH TABLE:

The circuit output should follow the same pattern as in the truth table for different input
combinations.

Case-1 : VA – Low & VB – Low

As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So the
output Vout will get two paths through two ON pMOS to get connected with Vdd. The output will
be charged to the Vdd level. The output line will not get any path to the GND as both the nMOS
are off. So, there is no path through which the output line can discharge. The output line will
maintain the voltage level at Vdd; so, High.

Case-2 : VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 – ON

pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a path
through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As nMOS1 is
OFF, so Vout will not be able to find a path to GND to get discharged. This in turn results the
Vout to be maintained at the level of Vdd; so, High.

Case-3 : VA –High & VB –Low

VB – Low: pMOS2 – ON; nMOS2 – OFF

Case-4 : VA – High & VB – High

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – High: pMOS2 – OFF; nMOS2 – ON

In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with Vdd.
As both the nMOS are ON, the series connected nMOS will create a path from Vout to GND.
Since, the path to ground is established, Vout will be discharged; so, Low.

In all the 4 cases we have observed that Vout is following the exact pattern as in the truth table for
the corresponding input combination.

SCHEMATIC CIRCUIT DIAGRAM:

Fig.4.2: Schematic for two input NOR gate

LAYOUT:

Fig.4.4: Layout of 2-input NOR gate

Fig.4.5: LVS result

Fig.4.6: PEX result

Delay=τPHL+τPLH

=-50.05ps -6.68ns=-50.05ns
 4. CMOS TWO INPUT NAND GATE

AIM: Design and verification of two input NAND gate operation using cmos
implementation.

THEORY: The schematic diagram for a CMOS NAND gate:

Fig 5.1: 2-input CMOS NAND gate

Notice how transistors Q 1 and Q3 resemble the series-connected complementary pair from the
inverter circuit. Both are controlled by the same input signal (input A), the upper transistor
turning off and the lower transistor turning on when the input is “high” (1), and vice versa.
Notice also how transistors Q2 and Q4 are similarly controlled by the same input signal (input B),
and how they will also exhibit the same on/off behaviour for the same input logic levels. The
upper transistors of both pairs (Q1 and Q2) have their source and drain terminals paralleled, while
the lower transistors (Q3 and Q4) are series-connected. What this means is that the output will go
“high” (1) if either top transistor saturates, and will go “low” (0) only if both lower transistors
saturate. The following sequence of illustrations shows the behavior of this NAND gate for all
four possibilities of input logic levels (00, 01, 10, and 11).

TRUTH TABLE:
The circuit output should follow the same pattern as in the truth table for different input
combinations.

Case-1 : VA – Low & VB – Low

As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So the
output Vout will get two paths through two ON pMOS to get connected with Vdd. The output will
be charged to the Vdd level. The output line will not get any path to the GND as both the nMOS
are off. So, there is no path through which the output line can discharge. The output line will
maintain the voltage level at Vdd; so, High.

Case-2 : VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 – ON

pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a path
through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As nMOS1 is
OFF, so Vout will not be able to find a path to GND to get discharged. This in turn results the
Vout to be maintained at the level of Vdd; so, High.

Case-3 : VA – High & VB – Low

VB – Low: pMOS2 – ON; nMOS2 – OFF

The explanation is similar as case-2. Vout level will be High.

Case-4 : VA – High & VB – High

VB – High: pMOS2 – OFF; nMOS2 – ON

In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with Vdd.
As both the nMOS are ON, the series connected nMOS will create a path from Vout to GND.
Since, the path to ground is established, Vout will be discharged; so, Low.

In all the 4 cases we have observed that Vout is following the exact pattern as in the truth table for
the corresponding input combination.

SCHEMATIC CIRCUIT DIAGRAM:

Fig 5.2: Schematic for two input NAND gate

LAYOUT:

Fig 5.4: Layout of 2-input NAND gate

RESULT:
 Fig.5.5: LVS result

Fig.5.6: PEX result

DELAY:
Delay=τPHL+τPLH

= 24.980ns -19.2407ps =20.49ns