CMOS

CMOS or Complementary Metal Oxide Semiconductor is a combination

of NMOS and PMOS transistors,
The importance of CMOS in semiconductor technology is its low power dissipation and low
operating currents; this allows integrating more CMOS gates on an IC than in NMOS or bipolar
technology, resulting in much better performance.
CMOS transistors are used in various applications, such as, Integrated circuit chips,
microprocessors, ASIC designing etc.

NMOS

NMOS consists of N-type Source and Drain diffused on an P-type substrate. The majority of
carriers are electrons.
When a high voltage is applied to the gate, the NMOS will conduct. Similarly, when a low
voltage is applied to the gate, NMOS will not conduct.
NMOS is considered to be faster than PMOS, since the carriers in NMOS, which are electrons,
travel twice as fast as the holes.
NMOS VI CHARACTERISTIC

Current through the device will be zero until the VGS exceeds the value of threshold voltage VT.
Under this condition, even an increase in VDS will result in no current flow, As a result this state
represents nothing but the cut-off region of MOSFET’s operation.
Once VGS exceeds VT, the current increases with IDS initially (Ohmic region) Linear region and
then saturates at a value determined by VGS (saturation region). As VGS increases, the saturation
current also increases.
PMOS
PMOS consists of P-type Source and Drain diffused on an N-type substrate. The majority of
carriers are holes.
When a high voltage is applied to the gate, the PMOS will not conduct. When a low voltage is
applied to the gate, the PMOS will conduct.
The PMOS devices are more immune to noise than NMOS devices.
PMOS VI CHARACTERISTIC
IDS remains zero (cutoff state) until VGS becomes equal to -VT.This is because; only then the
channel will be formed to connect the drain terminal of the device with its source terminal.
After this, the IDS is seen to increase in reverse direction with the decrease in the value of VDS.
This means that the device is functioning in its (ohmic region) Linear region.
As VDS becomes equal to –VP, the device enters into saturation region during which a saturated
amount of current (IDSS) flows through the device, as decided by the value of VGS

CMOS Working Principle

When the input voltage (A) = 0V, the PMOS conducts, and NMOS will remain in the OFF.
It means that the output voltage is considered as logic 1 because the PMOS switch is closed and
the NMOS switch at the bottom is open.
Similarly, when the input voltage A = 1. In such a state, the PMOS will be OFF, and NMOS
will conduct.
The output voltage is considered as logic 0 because the PMOS switch at the top is open and the
NMOS switch is closed.

In CMOS logic gates a collection of NMOS is arranged in a pull-down network between the
output and the ground.
CMOS logic gates have a collection of PMOS in a pull-up network between the output and the
Vdd.
CMOS Inverter
When a high voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes
an open circuit(OFF), and NMOS switched ON so the output will be pulled down to Vss.
When a low-level voltage (<Vdd, ~0v) applied to the inverter, the NMOS switched OFF and
PMOS switched ON. So the output becomes Vdd or the circuit is pulled up to Vdd.

INPUT LOGIC INPUT OUTPUT LOGIC OUTPUT

0v 0 Vdd 1
Vdd 1 0v 0

Voltage Transfer Characteristics (VTC) of CMOS Inverter

CMOS NAND Gate

The below figure shows a 2-input CMOS NAND gate. It consists of two series NMOS
transistors between Y and Ground and two parallel PMOS transistors between Y and VDD.
If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking the
path from Y to Ground and one of the pMOS transistors will be ON, creating a path from Y to
VDD.

A B Pull-Down Network Pull-up Network OUTPUT Y

0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

CMOS NOR Gate

The NMOS transistors are in parallel to pull the output low when either input is high. The
PMOS transistors are in series to pull the output high when both inputs are low

A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Advantages of CMOS

 Very low power dissipation  Produces very less heat

 Reduced circuit complexity  Improved Noise immunity

VLSI Design Flow

1) Specification and Architecture

This is the initial stage where the requirements for the IC or SoC are defined, including
the functionality, performance, power consumption, and area constraints.
The specifications can include the size of the integrated circuit, maximum power
consumption, velocity of current flow, performance of transistors, and more

2) Design Entry
Design entry involves creating a high-level design representation of the IC or
SoC using a hardware description language (HDL), such as Verilog or VHDL.

3) Functional Verification
This step involves verifying that the high-level design meets the specifications by
simulating it using a hardware simulator. These include formal verification, functional
simulation, and timing analysis.

4) Synthesis
In this step, the high-level design is translated into a gate-level netlist, a collection of
logic gates and flip-flops that implement the design. The synthesis tools connect the
functionality described in the HDL to a set of standard cells.

5) Design Optimization
The gate-level netlist is optimized for various design constraints, such as power
consumption, timing, and area. Mapping, area optimization, design rule fixing, and
delay optimization are some common types of design optimization processes used at
this stage.
 6) Physical Design

In which region MOSFER acts as amplifier?

A MOSFET acts as an amplifier in the ohmic region, where the current increases as the value
of VDS increases.
In which region MOSFER acts as Switch?
A MOSFET acts as a switch in two operating regions: the saturation region (closed switch)
and the cut-off region (open switch).
What is latch-up problem?

A latch-up can be defined as when the short circuit occurs between the two terminals like
power and ground so that high current can be generated & IC can be damaged.
In CMOS, latch-up is the occurrence of low impedance trail among the power rail &
ground rail because of the communication between the two transistors
In a latch-up transmission, the current will flow from VDD to GND straight through the two
transistors so that a short circuit can occur, thus extreme current will flow from VDD to the
ground terminal.
Different methods for latch-up prevention
1) Putting a high resistance in the path so as to limit the current through supply and make β1
*β2 < 1.
2) Surrounding PMOS and NMOS transistors with an insulating oxide layer, the technology
for latch-up protection will turn off the device once latch-up is noticed.
What are Integrated circuits?
Integrated circuits are made up of several components such as R, C, L, diodes and transistors. They are built
on a small single block or chip of a semiconductor known as an integrated circuit (IC). All of them work
together to perform a particular task.
What are soft check errors?

Soft check errors in VLSI are connectivity issues that can occur between the well and
diffusion layers of an IC design layout. They can be detected during the layout vs.
schematic (LVS) layout extraction flow
.