Syllabus

Fault Modeling
• Defects, Errors, and Faults
• Functional Versus Structural Testing
• Single Stuck-at Fault
• Fault Equivalence
• Equivalence of Single Stuck-at Fault
• Fault Collapsing
• Fault Dominance

Algorithms for Fault Simulation

• Serial Fault Simulation
• Parallel Fault Simulation
• Deductive Fault Simulation

PLA Testing

* 1
 Syllabus
TESTABILITY MEASURES
• SCOAP Controllability and Observability
• Combinational SCOAP Measures
• Sequential SCOAP Measures

Automatic Test-Pattern Generator

• Binary Search Trees.

• Binary Decision Diagrams
• Boolean Difference method
• 5 valued algebra
• D Algorithm
• PODEM
• Critical path testing

* 2
 Syllabus
Sequential Testing
• ATPG for Single-Clock Synchronous Circuits
• Time frame expansion method
• 9-valued algebra
(Upto page 226 of chapter 8)

* 3
Problem and Motivation
• Fault simulation Problem:
Given
▪ A circuit
▪ A sequence of test vectors
▪ A fault model
Determine
▪ Fault coverage - fraction (or percentage) of modeled faults
detected by test vectors
▪ Set of undetected faults
• Motivation
▪ Determine test quality and in turn product quality
▪ Find undetected fault targets to improve tests

* 4
Problem and Motivation
• Fault simulation Problem:
Given
▪ A circuit
▪ A sequence of test vectors
▪ A fault model
Determine
▪ Fault coverage - fraction (or percentage) of modeled faults
detected by test vectors
▪ Set of undetected faults
• Motivation
▪ Determine test quality and in turn product quality
▪ Find undetected fault targets to improve tests

* 5
Fault simulator in a VLSI Design
Process
Verified design Verification
netlist input stimuli

Fault simulator Test vectors

Modeled Remove Test Delete

fault list tested faults compactor vectors

Fault Low Test

coverage generator
? Add vectors

Adequate
Stop
* 6
 Fault Simulation Scenario
• Circuit model: mixed-level
• Mostly logic with some switch-level for high-impedance
(Z) and bidirectional signals
• High-level models (memory, etc.) with pin faults
• Signal states: logic
• Two (0, 1) or three (0, 1, X) states for purely Boolean logic
circuits
• Four states (0, 1, X, Z) for sequential MOS circuits
• Timing:
• Zero-delay for combinational and synchronous circuits
• Mostly unit-delay for circuits with feedback

* 7
 Fault Simulation Scenario (Continued)
• Faults:
• Mostly single stuck-at faults
• Sometimes stuck-open, transition, and path-delay faults;
analog circuit fault simulators are not yet in common use
• Equivalence fault collapsing of single stuck-at faults
• Fault-dropping -- a fault once detected is dropped from
consideration as more vectors are simulated; fault-
dropping may be suppressed for diagnosis
• Fault sampling -- a random sample of faults is simulated
when the circuit is large

* 8
 Fault Simulation Algorithms

• Serial
• Parallel
• Deductive

* 9
 Serial Algorithm
• Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:
• Modify netlist by injecting one fault
• Simulate modified netlist, vector by vector, comparing
responses with saved responses
• If response differs, report fault detection and suspend
simulation of remaining vectors
• Advantages:
• Easy to implement; needs only a true-value simulator,
less memory
• Most faults, including analog faults, can be simulated

* 10
 Serial Algorithm (Cont.)
• Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
• Alternative: Simulate many faults together

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1

Comparator f2 detected?
Circuit with fault f2

Comparator fn detected?
Circuit with fault fn

* 11
Parallel Fault Simulation
• Compiled-code method; best with two-states
(0,1)
• Exploits inherent bit-parallelism of logic
operations on computer words
• Storage: one word per line for two-state
simulation
• Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine word
length
• Speed up over serial method ~ w-1
• Not suitable for circuits with timing-critical
and non-Boolean logic

* 12
Parallel Fault Sim. Example
Bit 0: fault-free
circuit
Bit 1: circuit with c s-
a-0Bit 2: circuit with f s-
a-1
1 1 1
c s-a-0
a 1 0 1 detected
1 1 1 1 0 1
b e 1 0 1
c s-
g
a-0 0 0 0

d f s- 0 0 1
a-1

* 13
Deductive Fault Simulation
• One-pass simulation
• Each line k contains a list Lk of faults
detectable on it
• Following true-value simulation of each
vector, fault lists of all gate output lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
• PO fault lists provide detection data
• Limitations:
• Set-theoretic rules difficult to derive for non-
Boolean gates
• Gate delays are difficult to use

* 14
Deductive Fault Sim.
Example
Notation: Lk is fault list for line k
kn is s-a-n fault on line
k Le = La U Lc U {e0}
1 {a0}
a = {a0 , b0 , c0 , e0}
1 {b0 , c0}
b e 1
{b0} c 1
g
d f 0
Lg = (Le Lf ) U {g0}
U
{b0 , d0} {b0 , d0 , f1}
= {a0 , c0 , e0 , g0}
Faults detected
by
the input vector
15
ATPG Problem
• ATPG: Automatic test pattern generation
• Given
• A circuit (usually at gate-level)
• A fault model (usually stuck-at type)
• Find
• A set of input vectors to detect all modeled faults.
• Core problem: Find a test vector for a
given fault.
• Combine the “core solution” with a fault
simulator into an ATPG system.

* 16
 What is a Test?
Fault activation
Fault effect
X Combinational circuit
1
0
0 1/0 1/0
Primary inputs 1 Primary outputs
(PI) 0 (PO)
1
X
X

Path sensitization
Stuck-at-0 fault

* 17
Testing During VLSI Life Cycle
• Testing typically consists of
• Applying set of test stimuli to
• Inputs of circuit under test (CUT), and
• Analyzing output responses
• If incorrect (fail), CUT assumed to be faulty
• If correct (pass), CUT assumed to be fault-free

Input Output
Input Circuit Output
Test 1
Under Test 1
Response Pass/
Stimuli (CUT) Analysis Fail
Input Output
n m

18
 Testing During VLSI Development
• Design verification
targets design errors Design
• Corrections made Specification
prior to fabrication
Design Design
• Remaining tests target Verification
manufacturing defects Fabrication Wafer Test
• A defect is a flaw or
physical imperfection Packaging Package Test
that can lead to a fault
Quality Assurance Final Testing

19
 System-Level Testing
• Testing required to ensure system availability
• Types of system-level testing
• On-line testing – concurrent with system operation
• Off-line testing – while system (or portion of) is taken out of
service
• Performed periodically during low-demand periods
• Used for diagnosis (identification and location) of faulty replaceable
components to improve repair time

20
 Test Generation
• A test is a sequence of test patterns, called test vectors,
applied to the CUT whose outputs are monitored and
analyzed for the correct response
• Exhaustive testing – applying all possible test patterns to CUT
• Functional testing – testing every truth table entry for a
combinational logic CUT
• Neither of these are practical for large CUTs
• Fault coverage is a quantitative measure of quality of a
set of test vectors

21
Test Generation
• Fault coverage for a given set of test vectors
• 100% fault coverage may be impossible due to
undetectable faults

• Reject rate = 1 – yield(1 – fault coverage)

• A PCB with 40 chips, each with 90% fault coverage and
90% yield, has a reject rate of 34.4%
• Or 344,000 defective parts per million (PPM)

22
Prob of Fault Detection (Cont.)
• Then, is the prob that N random vectors
do not detect f
• Thus, the prob that at least one out of N random
vectors can detect f is

23
 Stuck-at Faults Truth table for fault-free behavior
❑ Any line can be and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
▪ Stuck-at-0 (SA0) y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
▪ Stuck-at-1 (SA1) a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
# fault types: k=2 b SA1 0 0 0 0 1 1 1 1

❑
c SA0 0 0 0 0 0 0 1 1
Example circuit: c SA1 1 1 0 0 1 1 1 1

▪ # fault sites: n=9 d

d
SA0
SA1
0
0
1
1
0
0
0
0
0
1
1
1
0
1
0
1

▪ # single faults =2×9=18 e

e
SA0
SA1
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
1
f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1

x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
24
 Stuck-at Faults Truth table for fault-free behavior
❑ Valid test vectors and behavior of all possible stuck-at faults
▪ Faulty circuit differs from x1x2x3 000 001 010 011 100 101 110 111
y 0 1 0 0 0 1 1 1
good circuit a SA0 0 1 0 0 0 1 0 0
a SA1 0 1 1 1 0 1 1 1
▪ Necessary vectors: b SA0 0 1 0 1 0 1 0 1
b SA1 0 0 0 0 1 1 1 1
011 detects f SA1, e SA0 c SA0 0 0 0 0 0 0 1 1
100 detects d SA1 c SA1 1 1 0 0 1 1 1 1
d SA0 0 1 0 0 0 1 0 0
– Detect total of 10 faults d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
– 001 and 110 detect e SA1 0 0 0 0 0 0 1 1
remaining 8 faults f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1

x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
25
 Stuck-at Faults Truth table for fault-free behavior
❑ 4 sets of equivalent and behavior of all possible stuck-at faults
faults x1x2x3 000 001 010 011 100 101 110 111
y 0 1 0 0 0 1 1 1

❑ # collapsed faults = a
a
SA0
SA1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
2×(PO+FO)+GI-NI b
b
SA0
SA1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
▪ PO= # primary outputs c
c
SA0
SA1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
▪ FO= # fanout stems d SA0 0 1 0 0 0 1 0 0
d SA1 0 1 0 0 1 1 1 1
▪ GI= # gate inputs e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
▪ NI= # inverters f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1

x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
26
 Stuck-at Faults
• # collapsed faults = 2×(P O+FO)+GI-NI
• PO= number of primary outputs
• FO= number of fanout stems
• GI= total number of gate inputs
for all gates including inverters
• NI= total number of inverters
• For example circuit, # collapsed faults = 10
• PO= 1, F O= 1, G I= 7, and NI= 1
• Fault collapsing typically reduces number of stuck-at
faults by 50% - 60%

27
Random Test Generation
• Simplest form of test generation
• N tests are randomly generated
• Level of confidence on random test set T
• The probability that T can detect all stuck-at faults in
the given circuit
• Quality of a random test set highly depends on the
underlying circuit
• Some circuits have many random-resistant faults

28
Weighted Random Test Generation
• Bias input probabilities to target random resistant faults
• Consider an 8-input AND gate
• Without biasing input probabilities, the prob of generating a logic 1
at the gate output = (0.5)8 = 0.004
• If we bias the inputs to 0.75, then the prob of generating a logic 1
at the gate output = (0.75)8 = 0.100
• Obtaining an optimal set of input probabilities a difficult
task
• Goal: increase the signal probabilities of hard-to-test
regions

29
Probability of Fault Detection
• Given a circuit with n inputs
• Let Tf be the set of vectors that can detect fault f
• Then is the prob that f can be detected by a
random vector
• Let be the prob that a random vector
cannot detect f

30
Minimum Detection Probability
• The min detection prob of any detectable fault actually does not
depend on n, the num of PIs
• Instead, it depends on the largest primary-output cone that it is in
• This is because any detectable fault must be excited and sensitized to a
primary output

31
Lemma 1
• In a combinational circuit with multiple outputs,
let nmax be the number of primary inputs that can
lead to a primary output. Then, the detection
probability for the most difficult detectable fault,
dmin, is:

32
Exhaustive Test Generation
• Exhaustive Testing
• Apply 2 n patterns to an n-input combinational circuit under test
(CUT)
• Guarantees all detectable faults in the combinational circuits are
detected
• Test time maybe be prohibitively long if the number of inputs is
large
• Feasible only for small circuits
• Pseudo-exhaustive Testing
• Partition circuit into respective cones
• Apply exhaustive testing only to each cone
• Still guarantees to detect every detectable fault based on Lemma 1

33
Theoretical Foundations: Boolean
Difference
• The function for the circuit is
• Let the target fault be y/0, then the function for the faulty circuit
is f’ = f(y=0)
• Goal of test generation: find a vector that makes f XOR f’ = 1

34
Boolean Difference Continued
• f XOR f’ = 1 iff f and f’ result in opposing logic
values
• Thus, any vector that can set f XOR f’ = 1 is able to
produce opposing values at the outputs of the
fault-free and faulty circuits respectively
• Definition:

35
Boolean Difference Example
• To excite the fault y/0, y=1
• Thus,

xyz= 110 or 011 can

detect the fault

36
Another Example
• Let target fault be w/0

xyz=001, 101
can detect w/0

But:

37
A Third Example
• Fault: z/0

This fault is untestable!

38
Wrap Up on Boolean Difference
• Given a circuit with output f and fault
• The set of vectors that can detect this fault
includes all vectors that satisfy

39
Deterministic ATPG
• In general, we don’t need an entire set of vectors that can
detect the target fault
• Instead, we just want to compute one vector quickly
• Rather than using Boolean Difference that can obtain all
vectors
• Simply use a branch-and-bound search to find one vector quickly
• Deterministic ATPG has two main goals
• Excite the target fault
• Propagate the corresponding fault effect to an output

40
5-valued Algebra for Comb. Circuits
• Instead of using two circuits (fault-free and the
faulty)
• We will solve the ATPG problem on one single circuit
• To do so, every signal value must be able to
capture fault-free and faulty values simultaneously
• 5-Value Algebra: 0, 1, X, D, D-bar
• D: 1/0
• D-bar: 0/1

41
Boolean Operators on 5-Valued
Algebra

42
The Justify Routine

43
Example

Fault: g/0

The recursive calls to JustifyFanoutFree():

44
The Propagate Routine

45
Example Continued
Propagate fault-effect
from g to z

46
D Algorithm
• Can handle arbitrary combinational circuits, with
internal fanout structures
• Main idea: always maintain a non-empty D-frontier
and try to propagate at least a fault effect to a
primary output
• Initially, all circuit nodes are X, except for the fault
cite, where a fault effect (D or D-bar) is placed.

47
D-Frontier and J-Frontier
• D-Frontier: All gates whose outputs are X but has
at least one D or D-bar at the input of the gates
• Initially, the D-frontier consists of only 1 gate (output of
the fault-site)
• J-Frontier: All gates whose outputs are specified by
are not justified by the input assignments

48
D-Frontier Example
• The D-frontier contains 2 gates

49
J-Frontier Example
• The J-Frontier contains 2 gates

50
Idea Behind D Algorithm
• To advance the fault-effects in the D-frontier, add
nodes to the J-frontier to justify

51
D Algorithm

52
D Algorithm Example

• Target fault: g/1

• Initially, D-Frontier: {h}, J-Frontier={g=D-bar}
• To advance D-frontier, add f=1 and c=1 to J-frontier

53
D Algorithm Example (Cont.)

• Now justify every value in J-Frontier via branch-

and-bound search
• Must not make D-frontier empty or conflict with other
J-frontier values
• Otherwise backtrack
• Result: g/1 is untestable
54
PODEM
• Also a branch-and-bound search
• Decisions only on PIs
• No J-Frontier needed
• No internal conflicts
• D-frontier may still become empty
• Backtrack whenever D-frontier becomes empty
• Backtrack also when no X-path exists from any D/D-bar
to a PO
• Decisions selected based on a backtrace from the
current objective

55
X-Path
• The D in the circuit has no path of X’s to any PO
• i.e., the D is blocked by every path to any PO

56
Getting the Objective

57
Backtrace to Select a Decision

58
PODEM Example
Target fault: f/0

• 1st Objective: f=1in order to excite the target fault

• Backtrace from the object: c=0
• Simulate(c=0): D-Frontier = {g}, some gates have been
assigned {c=d=e=h=0, f=D}
• 2nd Objective: advance D-frontier, a=1
• Backtrace from the object: a=1
• Simulate(a=0): Fault detected at z
59
Another PODEM Example
Target fault: b/0

• 1st Objective: excite fault: b=1

• Backtrace from objective: a=0
• Simulate(a=0): b=D, c=0, d=0: empty D-frontier. Must
backtrack
• Change decision to a=1
• Simulate(a=1): b=0, c=1, d=1, D-frontier still emtpy
• Backtrack, no more decisions. Fault untestable.

60
 ATPG is a Search Problem
• Search the input vector space for a test:
• Initialize all signals to unknown (X) state – complete
vector space is the playing field
• Activate the given fault and sensitize a path to a PO –
narrow down to one or more tests

Vector Vector
Space Circuit Space Circuit

X X
X 0
sa1 sa1 0/1
X 1

001 101

* 61
 Need to Deal With Two Copies of the
Circuit
Good circuit

X X
Alternatively, use a multi-valued
0
algebra of signal values for both
0 good and faulty circuits.
1

Different outputs
Same input

Faulty circuit Circuit

X X X
X
0 0
1 sa1 0/1
sa1 1
1

* 62
Multiple-Valued Algebras
Alternative
Symbol Fault-free Faulty
Representation
circuit Circuit
D 1/0
D 1 0
0/1
0 0 1
0/0 Roth’s
1 1/1
0 0
Algebra
X 1 1
G0 X/X
X X
G1 0/X
0 X
F0 1/X
1
Muth’s
F1 X/0 X
Additions
X 0
X/1
X 1

* 63
 An ATPG System
Random pattern
generator

Fault simulator
yes

Fault Random Deterministic

Save coverage patterns ATPG (D-alg.
patterns improved?
yes no effective? no or Podem)

yes
Compact Coverage no
vectors Sufficient?

* 64
Random-Pattern Generation
• Easily gets
tests for
60-80% of
faults
• Then switch
to D-
algorithm,
Podem, or
other ATPG
method

* 65