0.

1 MOS stages
Now that we have derived the input impedances seen from each of the terminals of the MOS
Transistor we can use them to study the voltage and current gains of some simple types of MOS
amplifying stages.

To do this we will consider the approximate model for the MOS transistor without the output
resistance ro
We consider as a bias network the following circuit:

VDC

VDC
RD

RG1 (D)

(G)

(S)

RG2

RS

With:

• VDC : the DC biasing voltage

We can then start considering all the possible combinations of choices for the input and output
terminal and the reference terminal.

0.1.1 Common emitter stage

Since the source is the common terminal we must choose the input and the output among the
other two terminals.

Choosing the drain as the input terminal would not make sense since the drain input impedance
is infinite, so the drain behaves as an open circuit.

Therefore, we must choose:

• the gate as the input terminal

• the drain as the output terminal

1
 42
So we have:

VDC

VDC
RD

RGEN RG1 (D)

(G)
Cout RL
(S)

Cin RG2
vSS
RS

The capacitors are added to preseve the bias point, since in DC they behave as open circuits
and so they make the bias point independent from the signal generator and from the load re-
sistance.
In our analysis we will consider them to be short circuits, by placing ourselves at the right
frequency (inside the frequency band of operation).

42
We can now derive the small signal model by switching off the voltage VDC and replacing the
MOS transistor with its equivalent circuit:

RGEN Zin

(G) (D) iL

vSS vin RG vGS gm vGS RD vD RL vL

(S) iS

RS vS

RG = RG1 k RG2
Keep in mind that RGEN is part of the source, not of the amplifier.

Let’s start by deriving the voltage gain of the common source stage.
We can start by deriving the input voltage vin by a voltage divider at the left loop:
RG
vin = vss
RG + RGEN
We also have that the gate voltage is:
vG = vin

2
 RG
vG = vss
RG + RGEN
We can now derive the source voltage from Ohm’s law at the source resistor:

vS = RS iS

We can then substitute the equation for the source current:

vS = RS gm vGS

We can then write a KVL at the left to derive the gate-source voltage:

vGS = vG − vS

vGS = vin − RS gm vGS

vGS + RS gm vGS = vin
(1 + RS gm )vGS = vin
1
vGS = vin
1 + R S gm
We can apply Ohm’s law to RD k RL to get the load voltage VL :

vL = −(RD k RL )gm vGS

Substituting the expression for the drain-source voltage we get:

gm
vL = −(RD k RL ) vin
1 + RS gm
We can then substitute the expression for the input voltage vin to get:
gm RG
vL = −(RD k RL ) vss
1 + RS gm RG + RGEN
Therefore, we have that the voltage gain of the common source stage between the input voltage
and the load voltage is:
vL gm
Av = = −(RD k RL )
vin 1 + RS gm
The overall voltage gain between the signal voltage vss and the load voltage is:

vL gm RG
Avss = = −(RD k RL )
vss 1 + RS gm RG + RGEN

We can see from the minus sign that it is an inverting stage.

Moreover, we can make the ratios:
gm RG
≤1 ≤1
1 + RS gm RG + RGEN
quite close to unity, by choosing large values of gm and a low value of RS and high values of
RG .
We can then increase a lot the values of RD k RL in order to get high voltage gains.
Therefore, it is a good inverting voltage amplifier.

3
 42
We can now derive the current gain.
In order to do that we will apply a real current source:

VDC

VDC
RD

RG1 (D)

(G)
Cout RL
(S)

iSS RGEN Cin RG2

RS

42
The small signal circuit is:

Zin

(G) (D) iL
iin
iSS
RG vGS gm vGS RD vD RL vL
RGEN

(S) iS

RS vS

We can derive the input current ii n by a voltage divider at the terminal of the source:
RGEN
iin = iSS
RGEN + RG
The gate voltage, by Ohm’s law is:
vG = RG iin
The source voltage is given by Ohm’s law:

vS = RS gm vGS

The gate-source voltage is given by a KVL at the left side:

vGS = vG − vS

Substituting the two expressions for vG and vS we get:

vGS = RG iin − RS gm vGS

4
 vGS + RS gm vGS = RG iin
(1 + RS gm )vGS = RG iin
1
vGS = RG iin
1 + RS gm
The drain current is given by:
gm
gm vGS = RG iin
1 + RS gm
We can then get the load current by a current divider at the collector node:
RC
iL = − gm vGS
RC + RL
Substituting the expression for the gate-source voltage we get:
RC gm
iL = − RG iin
RC + RL 1 + RS gm
We can then substitute the expression for the input current:
RC gm RGEN
iL = − RG iSS
RC + RL 1 + RS gm RGEN + RG
Therefore, the current gain of the common source stage between the input current iin and the
load current iL is:
iL RC gm
Ai = =− RG
iin RC + RL 1 + RS gm
The overall current gain between the signal iss and the load current iL is:

iL RC gm RGEN
Aiss = = −RG
iss RC + RL 1 + RS gm RGEN + RG

We can see how the ratios:

RC gm RGEN
≤1 ≤1 ≤1
RC + RL 1 + RS gm RGEN + RG
can be made almost one by picking large values of RC and gm and low values of RS and low
values RG with respect to RGEN .
There is still a term RG that makes for a large current gain.
Therefore, it is a good inverting current amplifier.

0.1.2 Common drain stage

Since the drain is the common terminal we must choose the input and the output among the
other two terminals.

Choosing the source as the input terminal would not make sense since the amplification would
be negligible.

5
Therefore, we must choose:

• the gate as the input terminal

• the source as the output terminal

43
So we have:

VDC

VDC
RD

RGEN RG1 (D)

(G)

(S)

Cin RG2
vSS

RS RL
Cout

The capacitors are added to preseve the bias point, since in DC they behave as open circuits
and so they make the bias point independent from the signal generator and from the load re-
sistance.
In our analysis we will consider them to be short circuits, by placing ourselves at the right
frequency (inside the frequency band of operation).

44
We can now derive the small signal model by switching off the voltage VDC and replacing the
MOS transistor with its equivalent circuit:

RGEN Zin iD
(G) (D)

vSS vin RG vGS gm vGS RD vD

(S) iS iL

RS vS RL vL

6
 RG = RG1 k RG2
Keep in mind that RGEN is part of the source, not of the amplifier.

Let’s start by deriving the input voltage of the stage vin .

We can do this by appying a voltage divider to the series between RGEN and RG in order to
determine the input voltage, which is the same as the gate voltage:
Zin
vin = vss
Zin + RGEN
Zin
vG = vss
Zin + RGEN
We can now derive the source voltage by apply Ohm’s law at the source terminal:

vS = (RS k RL )iS

The gate-source voltage is given by a KVL at the left loop and is:

vGS = vG − vS

Substituting the expressions for vG and vS we get:

vGS = vin − (RS k RL )iS

We can then substitute the relation between the source current and the gate-source voltage:

vGS = vin − (RS k RL )gm vGS

vGS + (RS k RL )gm vGS = vin

(1 + (RS k RL )gm )vGS = vin
1
vGS = vin
1 + (RS k RL )gm
The source current is then:
iS = gm vGS
gm
iS = vin
1 + (RS k RL )gm
We can then find the load voltage by applying Ohm’s law to (RS k RL ):

vL = (RS k RL )iS

We can then substitute the expression for the source current to get:
gm
vL = (RS k RL ) vin
1 + (RS k RL )gm

If we substitute the expression for the input voltage we get:

gm Zin
vL = (RS k RL ) vss
1 + (RS k RL )gm Zin + RGEN

7
Therefore, the voltage gain between the input voltage vin and the load voltage vL is:

vL (RS k RL )gm
Av = =
vin 1 + (RS k RL )gm

The voltage gain between the voltage of the signal vss and the load voltage vL is:

vL (RS k RL )gm Zin

Avss = =
Avss 1 + (RS k RL )gm Zin + RGEN

We can notice how it has at most unitary voltage gain, so this stage cannot work as a voltage
amplifier.

43
We can now derive the current gain.
In order to do that we will apply a real current source:

VDC

VDC
RD

RG1 (D)

(G)

(S)

iSS RGEN Cin RG2

RS RL
Cout

44
The small signal circuit is:

Zin
iD
(G) (D)
iin
iSS
RG vGS gm vGS RD vD
RGEN

(S) iS iL

RS vS RL vL

8
We can start by deriving iin through a current divider at the gate terminal:
RGEN
iin = iss
RGEN + RG
We can derive the gate voltage by applying Ohm’s law to RG :

vG = RG iin

We can then write the source voltage by applying Ohm’s law to (RS k RL ):

vS = (RS k RL )iS

Substituting the relation between the source current and the gate-source voltage we get:

vS = (RS k RL )gm vGS

We can derive the gate-source voltage from a KVL at the left side:

vGS = vG − vS

Substituting the expressions for the gate voltage vG and the source voltage vS we get:

vGS = RG iin − (RS k RL )gm vGS

vGS + (RS k RL )gm vGS = RG iin

(1 + (RS k RL )gm )vGS = RG iin
1
vGS = RG iin
1 + (RS k RL )gm
We can derive the source current as:
is = gm vGS
gm
is = RG iin
1 + (RS k RL )gm
The load current is then given by the current divider:
RS
iL = iS
RS + RL
Substituting the expression for the source current iS we get:
RS gm
iL = RG iin
RS + RL 1 + (RS k RL )gm

Substituting the expression for the input current iin we get:

RS gm RGEN
iL = RG iss
RS + RL 1 + (RS k RL )gm RGEN + RG

Therefore, the current gain between the input current iin and the load current iL is:

iL RS gm
Ai = = RG
iin RS + RL 1 + (RS k RL )gm

9
The voltage gain between the voltage of the signal vss and the load voltage vL is:

iL RS gm RGEN
Aiss = = RG
Aiss RS + RL 1 + (RS k RL )gm RGEN + RG

We can see that the two terms:

RS gm
≤1 ≤1
RS + RL 1 + (RS k RL )gm

can be made arbitrarily close to unity by picking small values of RS k RL and large values of
RS .
Then, we can make the ratio:
RGEN
≤1
RGEN + RG
quite close to one by picking RG relatively smaller than RGEN .
There is still a RG term left that gives quite a large current gain.
So it is a good current amplifier. Because of this, if the components are chosen well enough in
order to get a unitary voltage gain it works well as a buffer.
It is called the source follower, since it can replicate the input voltage on the output but it can
give much larger currents.

0.1.3 Common base stage

Since the gate is the common terminal we must choose the input and the output among the
other two terminals.

Choosing the drain as the input terminal would not make sense since it behaves as an open
circuit.
Therefore, we must choose:

• the source as the input terminal

• the drain as the output terminal

43
So we have:

VDC

VDC
RD

RG1 (D)

RL
(G) Cout
RGEN
(S)

RG2

Cin vSS
RS

10
The capacitors are added to preseve the bias point, since in DC they behave as open circuits
and so they make the bias point independent from the signal generator and from the load re-
sistance.
In our analysis we will consider them to be short circuits, by placing ourselves at the right
frequency (inside the frequency band of operation).

44
We can now derive the small signal model by switching off the voltage VDC and replacing the
MOS transistor with its equivalent circuit:

iD iL
(G) (D)

RG vGS gm vGS RD vD RL

(S) iS
ZiS

RGEN
RS vS vSS
vin

RG = RG1 k RG2
Keep in mind that RGEN is part of the source, not of the amplifier.

We can write a voltage divider at the source terminal in order to find vin :
(RS k ZiS )
vin = vss
(RS k ZiS ) + RGEN
With:
1
ZiG =
gm
Since no current is flowing through the gate terminal we have:

vG = 0

We can then write a KVL at the left side to get:

vGS = −vS

Since vS = vin we have:

vGS = −vin
the drain current iD is then:
iD = gm vGS

11
We have that, by Ohm’s law, the voltage on the load is:

vL = −(RD k RL )iD

Substituting the expression for the drain current we get:

vL = −(RD k RL )gm vGS

Substituting the expression for the gate-source voltage we get:

vL = (RD k RL )gm vin

We can then substitute the expression for the input voltage vin to get:

(RS k ZiS )
vL = gm (RD k RL ) vss
(RS k ZiS ) + RGEN

Therefore, the voltage gain of the common gate source between the input voltage vin and the
load voltage vL is:
vL
Av = = (RD k RL )gm
vin
The overall voltage gain between the input signal voltage vss and the load voltage vL is:

vL (RS k ZiS )
Avss = = gm (RD k RL )
vss (RS k ZiS ) + RGEN

We can see how the factor:

(RS k ZiS )
≤1
(RS k ZiS ) + RGEN
can be made almost unitary by making (RS k ZiS ) much biffer than RGEN

43
We can now derive the current gain.
In order to do that we will apply a real current source:

VDC
VDC
RD

RG1 (D)

RL
(G) Cout
(S)

RG2

RS Cin RGEN iSS

12
44
The small signal circuit is:

iD iL
(G) (D)

RG vGS gm vGS RD vD RL vL

(S) iS iin
ZiS

RS vS RGEN iSS

We can derive the input current by applying a current divider to the terminal of the source:
RGEN
iin = iss
RGEN + (RS k ZiS )
We can then apply a current divider to the source terminal of the transistor:
RS
iD = − iin
RS + ZiS
The load current is then given by the current divider:
RD
iL = − iD
RD RL
Substituting the expression for the drain current we get:
RD RS
iL = iin
RD RL RS + ZiS
We can then substitute the expression for the input current iin to get:
RD RS RGEN
iL = iss
RD RL RS + ZiS RGEN + (RS k ZiS )
Therefore, the current gain of the common gate stage between the input current iin and the
load current iL is:
iL RD RS
Ai = = iin
iin RD RL RS + ZiS
The overall current gain between the input signal current iss and the load current iL is:

iL RD RS RGEN
Aiss = =
iss RD RL RS + ZiS RGEN + (RS k ZiS )

We can see how these ratios can be made at most unitary.

So, the common gate stage has at most unitary current gain.

13
0.1.4 BJT stages applications
According to the previous computations and observations we have the following characteristics
for each topology:

topology current gain voltage gain

Common source high high
Common drain high low
Common gate low high

Moreover, from the previously derived formulae for the input impedances, we can see that the
input and output impedances for each stage are:

topology input impedances output impedances

Common emitter high high
Common collector high low
Common base low high

We can see that, in general, the derived impedances are not always the ones we would want in
ideal amplifiers of the given kinds.
Therefore, the behavior of such circuits won’t in general be close to the ideal one!

0.1.5 About the approximations ...

The given approximation of neglecting ro is valid when it is much larger than any other resis-
tance present in the circuit.
This imposes some practical limitations in the values of the gains we can achieve, since, when
resistances become of the order of the output ones of the transistors, gains stop growing since
their contributions are not negligible any more.

14