Lab Workbook Creating a System with SDSoC

Creating a System with SDSoC

Introduction
This lab guides you through the process of using SDSoC to create a new project using available
templates, marking functions for hardware implementation, building a hardware implemented design, and
running the design on either the Zed or ZYBO board.

Objectives
After completing this lab, you will be able to:
 Create a new SDSoC project for your application from a number of available
platforms and project templates
 Mark functions for hardware implementation
 Build your project to generate a bitstream containing the hardware implemented
function and an software executable file that invokes this hardware implemented function
 Test the design in hardware

Procedure
This lab is separated into steps that consist of general overview statements that provide information on
the detailed instructions that follow. Follow these detailed instructions to progress through the lab.
This lab comprises four primary steps: You will create an SDSoC project, mark two functions for hardware
implementation, build the design with the hardware accelerators, and, test the design in hardware.

General Flow for this Lab

Step 1: Step 2: Step 3: Step 4:

Create an Mark Functions Build the Test the
SDSoC for Hardware Design with Design in
Project Implementation Hardware Hardware
Accelerators

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1Create an SDSoC Project Step 1

1.1. Launch SDSoC and create a project, called lab1, using one of the available
templates, targeting the Zed or Zybo board.

1.1.1. Open SDSoC by selecting Start > All Programs > Xilinx Design Tools > SDSoC 2015.4 >
SDSoC 2015.4

The Workspace Launcher window will appear.

1.1.2. Click on the Browse button and browse to c:\xup\SDSoC\labs, and click OK.

Figure 1. Selecting a workspace

1.1.3. Click OK.

The SDSoC development environment window will appear showing the Welcome tab.

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Figure 2. The SDSoC development environment with Welcome tab

From here you can create a new project, import an existing project, access the SDSoC user
guide, and access the SDK user guide by clicking on the desired link.

1.1.4. Click X on the Welcome tab to close it, and you will see the empty workspace in the background.

1.1.5. Select File > New > SDSoc Project to open the New Project GUI.

1.1.6. Enter lab1 as the project name, select either zybo or zed (depending on the board you are using)
via drop-down button, select Linux as the target OS, and click Next.

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Figure 3. Naming the project and selecting target platform and OS

The Templates page appears, containing source code examples for the selected platform.

1.1.7. Select Matrix Multiply-Add (area reduced) in case of zybo or Matrix Multiplication and
Addition in case of zed as the source.

Figure 4. Selecting from available templates

1.1.8. Click Finish.

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The created project will be displayed. In the left, you will see Project Explorer under which the
lab1 project directory will be displayed (you may have to expand the folder). It shows the
Includes and src folders. The src folder contains the source files which were copied from the
template source directory located at <SDSoC_install_directory>\samples\<template_name>. The
lab1 folder also shows the project.sdsoc project file. Double-clicking on it will display what you
see in the right-side pane.

In the SDSoC Project Overview pane, you see the Overview tab being displayed. Note that
another tab, called Platform, is also available. In the Overview tab, you see General, Hardware
Functions, Options, and Actions sub-areas. From here you will be able to change options, identify
the function(s) that will be implemented in hardware, setup for debugging and estimation, and
access various reports.

Figure 5. Created SDSoC project

2Mark Functions for Hardware Implementation Step 2

2.1. Mark madd and mmult functions for the hardware accelerations with
default clock speed.

2.1.1. Click on the “+” sign in the Hardware Functions area to open up the list of software functions in
the design.

Figure 6. Invoking functions list to select functions which can be hardware target

The Select functions for hardware acceleration window will open. The source files will be scanned
and available functions will be displayed.

2.1.2. While holding down the Ctrl key, select mmult and madd and click OK.

Alternatively, you can expand mmult.cpp and madd.cpp in the Project Explorer tab, right click on
mmult and madd functions, and select Toggle HW/SW (when the function is already marked for
hardware, you will see Toggle HW/SW [H]). When you have a source file open in the editor, you
can also select hardware functions in the Outline window.

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Figure 7. Selecting functions for hardware target

2.1.3. The two function names will be added into the Hardware Functions window.

Figure 8. Target hardware accelerators entries updated

You can select each function, click on the drop-down button of the Clock Frequency, and select a
clock speed that will be applied to that function. You can also select multiple functions (CTRL +
Click) and apply the clock frequency to all of them. Note the default clock frequency of 142.86
MHz for Zed and 100.00 MHz for Zybo. These speeds are defined in the platform that was
selected for the design.

(a) Zed (b) Zybo

Figure 9. Available clocks for the accelerators in a given platform

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2.1.4. Leave the clocks set to the default frequency of 142.86 MHz for Zed and 100.00 MHz for Zybo for
both functions.

2.1.5. Expand the lab1 folder in the Project Explorer pane and notice that the functions are marked for
hardware implementation in madd.cpp and mmult.cpp files.

Figure 10. Expanded project view indicating the selected functions for hardware
implementation

3Build the Design with Hardware Accelerators Step 3

3.1. Select SDRelease configuration and build the project. When done, analyze
the data motion network through the report and built hardware through
Vivado IPI.

3.1.1. Right-click on lab1 in the Project Explorer and select Build Configurations > Set Active to see
possible configurations and what is currently selected.

Figure 11. Selecting build configuration

3.1.2. Select Build Configurations > Set Active > SDRelease

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The SDRelease build configuration uses a higher compiler optimization setting than the SDDebug
build.

Building the project and generating the results in the next step may take 20 to 30 minutes.
Alternatively, you can import provided pre-built files into your workspace and load the results.

3.1.3. Right-click on lab1 and select Build Project

The output from the SDSoC compiler can be viewed in the Console tab. The functions selected
for hardware are compiled into IP blocks using Vivado HLS. The IP blocks are then integrated
into a Vivado design based on the selected base platform. Vivado will carry out synthesis, and
place and route tools to build a bitstream. The software functions that have been moved to
hardware will be replaced by function calls to the hardware blocks, and the software will be
compiled to generate an ELF executable file.

This may take about 25 to 30 minutes.

You can also load the results by importing the pre-built files into your workspace with these steps:

Select File > Import and then select General > Existing Projects into Workspace and click Next.

Select Select archive file and click Browse to navigate to c:\xup\SDSoC\sources\lab1

Select lab1_prebuilt.zip, and click Open

Click Finish.

3.1.4. Expand the lab1 (or lab1_prebuilt if you have imported the project) directory in Project Explorer
and observe that SDRelease folder is created along with virtual folders of Binaries and Archives.
Expanding the SDRelease folder shows _sds, sd_card, src folders along with lab1.elf ((or
lab1_prebuilt.elf if you have imported the project) [executable], lab1.elf.bit (or
lab1_prebuilt.elf.bit if you have imported the project) [hardware bit file] and several make files.

(a) Generated (b) Imported

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Figure 12. Project Explorer folders

The sd_card folder contains files and sub-directory (depending on the target OS) which can be
copied to a SD card and then used to boot the system to test the design in hardware.

The src folder contains object and debug information carrying files of the main function as well as
the hardware target files.

The _sds folder contains various sub-folders and files generated by SDSoC as well as other
underlying used tools.

3.1.5. Expand the _sds folder.

Figure 13. The generated _sds folder content

Notice that there are five sub-folders out of which four are greyed-out and one is shown as
normal. The directory which is not greyed-out (swstubs), indicates the folder and its contents
were generated by SDSoC. The greyed folders (iprepo, p0, reports, vhls) were generated by the
underlying tools.

The swstubs contains various source files to handle data motion as well as communication with
the hardware accelerators. It also contains various stub files and generated libraries.

The iprepo and vhls folders are generated by Vivado HLS. The iprepo has a sub-folders for each
hardware function. The vhls folder contains the complete HLS solution for each function. It also
contains tcl files used to generate the solution.

The p0 folder consists of ipi and sd_card sub-folders which includes the Vivado IPI project
(synthesis and implementation tcl files and results) and the generated SD card contents. The
project file, located in ipi sub-folder, has an extension of xpr. The project can be opened with
Vivado to display the block diagram of the generated system-level hardware.

The reports folder consists of log files and the data_motion.html containing the data motion
network report.

3.1.6. In the SDSoC Project Overview window, under the Reports pane, click on Data Motion Network
report.

The report shows the connections made by the SDSoC environment and the types of data
transfers for each function implemented in hardware. You can also open this report file by double-
clicking data_motion.html entry in SDRelease > _sds > reports of Project Explorer.

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Figure 14. Data motion network and accelerator callsites

There are two accelerated functions- madd and mmult. They are given instance names of
madd_0 and mmult_0. Each function has three arguments and hence three ports. Notice that the
out_C port of mmult_0 is directly connected to A_PORTA port of madd_0 port, whereas the other
two ports of each hardware are connected in the system via AXIDMA_SIMPLE channels on ACP.

The transfer size is 4096 bytes or 1024 words on each ports of the two accelerators.

3.1.7. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > SDSoC 2015.4 >
Vivado Design Suite > Vivado 2015.4

3.1.8. Open the design by browsing to c:\xup\SDSoC\labs\lab1\SDRelease\_sds\p0\ipi and selecting

either the zybo.xpr or zed.xpr.

3.1.9. Click on Open Block Design in the Flow Navigator pane. The block design will open. Note
various system blocks which connect to the Cortex-A9 processor (identified by ZYNQ in the
diagram).

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Figure 15. The generated block design

As seen before, this platform supports four clocks. There are four reset blocks, one for each
clock. As only the 142.86 MHz clock in Zed or the 100 MHz clock in Zybo was used for the
accelerators, it connects only one reset block is connected (second from top). The other blocks
will be optimized away during synthesis.

We have targeted two functions for hardware acceleration, and hence two HLS created blocks
are generated and included in the design.

Since there are four data mover connections using ACP, there are four data movers (indicated by
blue color). The four data movers connect to the processor’s ACP interface using the ACP
interconnect instance.

The mmult_o output (Out C) has a direction path to madd_0 input (A) is a direct connection, i.e. it
does not go through any data movers. You can see the path by zooming in and tracing the
connections (highlighted below).

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Figure 16. Non data mover connection between mmult_0 and madd_0

3.1.10. Close Vivado by selecting File > Exit

3.2. Open the main.cpp, mmult.cpp, and madd.cpp files under SDRelease >
_sds> swstubs and lab1 > src folders and understand the added code
segments.

3.2.1. Expand lab1 > src and double-click on main.cpp to see its content.

If line numbers are not visible then you can right-click in the left border of the file and select Show
Line Numbers.

Note that line 140 calls the multadd_test function call. The multadd_test function is defined
between lines 88 and 115, which in turn calls mmult at line 98 and madd at line 100. The mmult
function is defined in mmult.cpp (lines 31-57) and the madd function is defined in madd.cpp (lines
4-13). Both these files are under the same src folder.

3.2.2. Expand SDRelease > _sds> swstubs and double-click on main.cpp to see its content.

Note that line 142 calls multadd_test function call as seen in the original source file. The
multadd_test function is now preceded by two function prototypes (lines 88 and 89) and the
function is defined between lines 90 and 117. On lines 100 and 102 it makes calls to
_p0_mmult_0 and _p0_madd_0 replacing the original calls.

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Figure 17. Updated main.cpp file content

3.2.3. Double-click on the mmult.cpp under SDRelease > _sds> swstubs to see its content.

The _p0_mmult_0 function is defined in lines 63 through 78, replacing the original functionality
with the data transfer using the cf_send command. Similarly, the madd function is updated in
madd.cpp (lines 19-38). It additionally uses cf_receive call to get the results.

The subsequent labs will discuss these function calls.

Figure 18. The updated mmult.cpp file

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4Test the Design in Hardware Step 4

4.1. Copy the files located under SDRelease\SD_Card folder into a SD card.
Place the card into the board. Configure the board to boot from SD.
Connect and power up the board. Establish serial communication. Execute
the application.

4.1.1. Using the Windows Explorer, copy all the files located under either lab1\SDRelease\SD_Card
folder or lab1_prebuilt\SDRelease\SD_Card to the SD (Zed) or Micro-SD (Zybo) card.

4.1.2. Use SDK Terminal window on Zed or Terminal window on Zybo or third party terminal emulator
program like PuTTy, HyperTerminal, TeraTerm programs.

4.1.3. Select appropriate C OM port (depending on your computer), and configure the terminal with the
115200 baud rate.

4.1.4. You should see the output in the console.

Figure 19. System bootup output

If you don’t see the output then you can press PS-SRST push-button (Red) on the board.

4.1.5. In the Terminal window, either enter /mnt/lab1.elf or /mnt/lab1_prebuilt.elf at the command
prompt and hit the Enter key.

The program will be executed and the result will be displayed showing the number of cycles
software execution takes vs the number of cycles taken using the hardware accelerators. It also
shows the number rows and columns of the matrices.

(a) Zed

(a) Zybo
Figure 20. Program output

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4.1.6. Close SDSoc by selecting File > Exit

4.1.7. Turn OFF the power to the board.

Conclusion
In this lab, you created a project in the SDSoC Development Environment using one of the available
project templates. You then identified the functions which you wanted to put in the PL section of the Zynq
chip to improve the performance. Once the system was built, you analyzed the Data Motion network and
the created Vivado IPI project. Finally, you copied the relevant files on a SD card and verified the design
in hardware.

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