World Academy of Science, Engineering and Technology

International Journal of Electronics and Communication Engineering

Vol:11, No:3, 2017

Rail-To-Rail Output Op-Amp Design with Negative

Miller Capacitance Compensation
Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

 effect transistor (MOSFET); firstly, through the structure of

Abstract—In this paper, a two-stage op-amp design is considered the MOSFET as shown Fig. 1. The MOSFET has five
using both Miller and negative Miller compensation techniques. The capacitances between its drain (D), gate (G), source (S), and
first op-amp design uses Miller compensation around the second bulk (B) terminals. The overlap capacitance between the gate
amplification stage, whilst the second op-amp design uses negative
and the drain (Cgd) creates a feedback between the gate input
International Science Index, Electronics and Communication Engineering Vol:11, No:3, 2017 waset.org/Publication/10006593

Miller compensation around the first stage and Miller compensation

around the second amplification stage. The aims of this work were to and the drain output nodes. Although Cgd typically is a small
compare the gain and phase margins obtained using the different capacitance value, it will however have an effect on the high-
compensation techniques and identify the ability to choose either frequency response of the amplifier. The capacitance Cgd is
compensation technique based on a particular set of design called the Miller effect or Miller capacitance.
requirements. The two op-amp designs created are based on the same
two-stage rail-to-rail output CMOS op-amp architecture where the
Miller D
first stage of the op-amp consists of differential input and cascode compensation
circuits, and the second stage is a class AB amplifier. The op-amps Cdb Cgs - gate-source
have been designed using a 0.35m CMOS fabrication process. capacitance
Cgd
Cgd - gate-drain
Keywords—Op-amp, rail-to-rail output, Miller compensation, B
G capacitance
negative Miller capacitance. Csb - source-bulk
Csb
Cgs capacitance
I. INTRODUCTION S Cdb - drain-bulk

I N many electronic circuit designs, the operational amplifier

(op-amp) is an important circuit building block. The op-amp
is a differential input amplifier circuit that uses external
Cgb

Fig. 1 Structure of the MOSFET

feedback to create useful circuits such as buffers, comparators,
oscillators, instrumentation amplifiers and filters. The move Secondly, it can be performed by adding an external
over the last number of years has been to operate the op-amp capacitor (CM) around the second stage of the conventional
on lower power supply voltages and with single rail operation two-stage CMOS op-amp as shown in Fig. 2. In this figure,
whilst utilizing lower geometry fabrication processes. the external Miller capacitor (CM) is connected to the second
However, reducing the supply voltage and transistor sizes has stage, although the capacitor could also be connected around
an effect on the design operation characteristics such as the first stage or around the complete amplifier circuit.
stability and frequency response. Various circuit architectures In this paper, Miller compensation is considered by firstly
have considered these concerns in order to reduce performance using conventional Miller compensation and secondly by
related problems [1]-[4]. In general, Miller compensation is using a combination of Miller and negative Miller
used to improve the stability and frequency response of the compensation. The target amplifier is a two-stage rail-to-rail
op-amp. output CMOS op-amp operating on a +3.3 V single rail power
The Miller effect can be realized in two ways within a supply. The paper is organized as follows. Section II will
CMOS (complementary metal oxide semiconductor) analogue introduce Miller theory and Miller compensation with its
amplifier circuit using the metal oxide semiconductor field extension to negative Miller compensation. Section III will
introduce the two-stage CMOS op-amp design with rail-to-rail
Muhaned Zaidi is with the Department of Electronic and Computer
output operation using the AMS 0.35 µm CMOS technology.
Engineering, University of Limerick, Limerick, Ireland and University of Section IV will present the implementation of negative Miller
Wasit, Wasit, Iraq. (phone: 00-353-61-202298, fax: 00-353-61-338176, e- capacitance and simulation of the op-amp using the Spectre
mail: muhaned.zaidi@ul.ie). simulator with typical transistor models.
Ian Grout is with the Department of Electronic and Computer Engineering,
University of Limerick, Limerick, Ireland (e-mail: ian.grout@ul.ie).
Abu Khari A’ain is with the Faculty of Electrical Engineering, Universiti
Teknologi Malaysia, Skudai, Malaysia (e-mail: abu@fke.utm.my).

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 World Academy of Science, Engineering and Technology
International Journal of Electronics and Communication Engineering
Vol:11, No:3, 2017

output to positive input [7]-[9]. Fig. 4 shows how this idea can
CM be achieved in order to reduce the input capacitance of a
differential stage. By adding the feedback capacitors of equal
value (CNM), the original input capacitance at each input node
(with reference to GND) is reduced, and an improvement of
Differential Voltage Output op-amp unity gain frequency and phase margin is achieved
Input input stage amplifier stage [3].

Fig. 2 Conceptual system block diagram with Miller compensation CNM

around the second voltage amplifier stage

II. MILLER THEORY Differential

Input input stage
Output
A. Miller Compensation
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For a two-stage op-amp design, Miller compensation is

typically accomplished by connecting an external Miller
capacitor between the output of the second stage and output of CNM
first stage transistors as shown in Fig. 2. As identified in [2],
Fig. 4 Schematic of differential input with negative Miller
the Miller capacitor can be modelled as an impedance capacitance
connected from the output of the differential input stage to
ground (GND) and a second impedance connected from the Fig. 5 shows the differential amplifier with a differential
output stage to ground. This principle is shown in Fig. 3. input (Vin(+) and Vin(-)) and a differential output (Vout(+)
The capacitor on the input node has a capacitance value of and Vout(-)). The capacitances CNM are connected between
C(1 + A) and the capacitor on the output has a capacitance Vout(+) with Vin(-) , and Vout(-) with Vin(+). If the feedback
value of C(1 + 1/A), where A is the voltage gain of the second capacitance CNM is much larger than amplifier input
stage. An advantage of this is that the dominant pole is shifted capacitance, the gain bandwidth improvement will be limited
downwards to a lower frequency and the non-dominant pole is by the output load capacitance CL. Cancelling the effect of a
shifted upwards to a higher frequency [4], which leads to large capacitance will require a large feedback capacitor CNM.
improved amplifier stability but with an associated reduction
in the unity gain frequency.

Differential Voltage Output

Input input stage amplifier stage

C (1+A) C (1+1/A)

Fig. 3 Gain stage with Miller capacitance equivalent

B. Negative Miller Compensation
Within each MOSFET, parasitic capacitances are present
which will limit the speed of operation of any circuit using the
MOSFET [5]. Negative Miller compensation has been
demonstrated to reduce this unwanted effect. Negative Miller
compensation uses the idea of negative capacitance which has Fig. 5 Differential input stage with negative Miller compensation [7]
a unique property that its voltage falls when the capacitor
charges [6]. Negative Miller compensation has been discussed This means that a suitable differential amplifier
widely in various text books and scientific articles including performance (phase margin and unity gain frequency) can be
[1]-[3], [6]-[8]. achieved if load capacitance CL is small. If a high voltage gain
A negative Miller capacitance (CNM) is useful to cancel or of the gain stage is created by a large op-amp output
remove the effect of any parasitic capacitances by using the resistance, the bandwidth can be significantly improved with
advantage of the Miller effect. The Miller effect is one way to negative capacitance. The expression for the effective input
create the negative capacitance. Negative capacitance is capacitance for each input node, Ceff, without CNM is given by:
created by connecting a regular capacitor across a non-
inverting amplifier with a gain >> 1 [6]. In a fully differential C C C 1 A (1)
amplifier, this is achieved by connecting capacitors between
the non-inverting output to the negative input and inverting

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Vol:11, No:3, 2017

In (1), if the amplifier voltage gain A >> 1, the inclusion of

negative Miller capacitance shows that the effective input Differential Class AB Output
Input input Cascode output
capacitance is reduced [6]. To achieve a negative Miller
capacitance, CNM can be added between the amplifier inputs circuit stage
and outputs [10]. However, the charge on this additional
capacitor is shared with the Cgd capacitance and:
Fig. 6 Block diagram of the op-amp structure
C C C 1 A C 1 A (2) B. Rail-To-Rail Output
The second stage is provided by feedforward class-AB
Assuming that CNM is approximately equal to Cgd then: control and is achieved using transistors M23 and M24, biased
by two in phase signal currents from the cascade transistors
C C 2C (3) M11 and M13. The gate voltages are kept at a constant value
by the stacked diode connected transistors (M25-M26 and
International Science Index, Electronics and Communication Engineering Vol:11, No:3, 2017 waset.org/Publication/10006593

Thus, as long as the amplifier gain is much greater than 1, a M27-M28). The floating current source transistors are M21
reduction in the effective input capacitance is achieved. and M22, and their transistors are connected to the stacked
diode with feed-forward class-AB control. The output stage
III. AMPLIFIER STRUCTURE with transistor coupled feedforward class AB control and
A. Cascode Circuit floating current source is appropriate for designing a compact
In the previous section, Miller capacitance and negative and power efficient op-amp [11].
Miller capacitance have been considered within an amplifier
design of the form shown in Fig. 6. To obtain a high output
voltage range using a CMOS technology, a cascode circuit can
be employed. The cascode circuit has a transconductance (gm)
equal to that of one input transistor and the DC bias current.
The mirror current connected transistors in the cascode
circuits have the same currents as the differential stage input
transistors; otherwise, the tail current is greater than the
current of the input stage. A high gm for the differential input
stage provides a high unity gain frequency.
The unity gain frequency is given by:

(4)

If the transconductance in (4) is a small value, the unity

gain frequency will be high while the phase margin (PM) is
decreased according to:

180° tan tan tan (5)

where P1, P2 and Z are first pole, second pole, and zero pole Fig. 7 Class AB stage structure with Miller capacitance
values, respectively. However, the lower currents in the
bottom set of current source transistors and upper mirror The class AB amplifier and floating current source control
transistors allow these transistors to have a lower W/L ratio in is implemented in the cascode circuit in order to decrease the
strong inversion at the same saturation voltages [11]. noise and offset. The noise and offset of the amplifier are
The wide-swing cascade current mirror used in the cascade mainly determined by the input transistors and the summing
circuit produces a high output resistance [12] which is given circuit [13]. In addition, the minimum supply voltage for the
by: class_AB stage transistor operation is equal to Vdd (min) =
Vgs(M26) + Vgs(M25) + Vsat. Even if M25 and M26 operate
|| || (6) in weak inversion, it means that Vdd (min) of this stage is
quite often the value that limits the minimum power supply
The gain of the cascode circuit is given by: voltage for low voltage operation of the overall op-amp [14],
[15]. Moreover, good high-frequency behaviour is achieved as
(7)
the coupling between the gates is realized by a single
transistor [16].

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 World Academy of Science, Engineering and Technology
International Journal of Electronics and Communication Engineering
Vol:11, No:3, 2017

IV. DESIGN IMPLEMENTATION AND RESULTS the negative input to the output of first stage and CNM2 is
Fig. 8 shows the second op-amp circuit with Miller and connected between the positive input to the output) and they
negative Miller capacitances. The negative Miller capacitance must be matched values.
is connected around the first stage (CNM1 is connected between
International Science Index, Electronics and Communication Engineering Vol:11, No:3, 2017 waset.org/Publication/10006593

Fig. 8 Schematic of the second op-amp (negative Miller compensation and Miller compensation)

The op-amp was simulated with AMS 0.35 μm CMOS changed since the input differential pair or current summing
technology and simulated using the Cadence Spectre branches do not contribute to PSRR [17].
simulator. The threshold voltages of NMOS are around 0.5 V
TABLE I
and PMOS transistors are in the around of 0.7 V. DIFFERENT MILLER CAPACITOR VALUES FOR THE FIRST OP-AMP DESIGN
The supply voltage Vdd is 3.3 V and the load capacitance is CM pF Phase margin degree Unity gain frequency (MHz)
a 1 pF. Table I shows the results for the first op-amp design 0.2 52.43 233.1
with different Miller capacitor values (i.e., no negative Miller 0.4 68.99 129.6
capacitors included) and identifies that the phase margin has 0.6 75.02 87.40
increased with increasing the Miller compensation (increasing 0.8 78.12 6380
the value of CM), but the unity gain frequency has reduced. 1 79.87 53.05
Fig. 9 shows the gain frequency and phase for different of the 1.2 81.14 42.32
Miller capacitance values.
Table II shows the different values of the negative Miller TABLE II
DIFFERENT NEGATIVE MILLER CAPACITOR FOR THE SECOND OP-AMP
capacitor with a fixed Miller capacitor value of 0.4 pF. The DESIGN (FIXED MILLER CAPACITOR VALUE)
unity gain frequency increases and phase margin shows a CNM pF Phase margin degree Unity gain frequency (MHz)
reduction as the value of CNM is increased. Fig.10 shows the 0.2 57.34 290.94
gain frequency and phase with different of the negative Miller 0.4 52.41 328.88
capacitance. 0.6 48.07 328
In Table III, a comparison between the two op-amp designs 0.8 44.76 359.12
is provided. The DC gain, common mode rejection ratio 1 42.69 373.36
(CMRR) and power supply rejection ratio (PSRR) have not 1.2 41.14 384.56

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Vol:11, No:3, 2017
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(a)

(b)
Fig. 9 Frequency response of the first op-amp (a)- gain and (b)- phase

(a)

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Vol:11, No:3, 2017
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(b)
Fig. 10 Frequency response of the second op-amp (a)- gain and (b)- phase

Fig. 11 Miller capacitance variation with unity gain and phase margin

Fig. 12 Negative Miller capacitance variation with unity gain and phase margin

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Vol:11, No:3, 2017

TABLE III [9] García López, I., et al., High speed BiCMOS linear driver core for
COMPARISON OF OP-AMP PERFORMANCE: MILLER CAPACITANCE ONLY AND segmented InP Mach-Zehnder modulators. Analog Integrated Circuits
COMBINED MILLER WITH NEGATIVE MILLER CAPACITANCE OP-AMP and Signal Processing, 2016. 87(2): p. 105-115.
Miller capacitance Miller and [10] Palermo, S., ECEN620: Network Theory Broadband Circuit Design Fall
Parameters 2014. 2012.
only negative Miller
Power supply (V) 3.3 3.3 [11] De Langen, K.-J. and J. Huijsing, Compact low-voltage and high-speed
CMOS, BiCMOS and bipolar operational amplifiers. Vol. 520. 2013:
DC gain (dB) 85.93 85.93 Springer Science & Business Media.
Phase margin (degree) 49.5 53.13 [12] Miser, B.D., Design of a Wide-Swing Cascode Beta Multiplier Current
Unity gain frequency (MHz) 174.4 217.7 Reference. 2003.
CMRR (dB) 100.4 100.4 [13] Fiedorow, P., et al. Design and implementation of general purpose
opamp using multipath frequency compensation. in New Circuits and
PSRR (dB) 135.43 135.43
Systems Conference (NEWCAS), 2011 IEEE 9th International. 2011.
Slew rate (V/µs) 79.4 75.9 IEEE.
DC offset (mV) 1.53 1.53 [14] Hogervorst, R., et al., A compact power-efficient 3 V CMOS rail-to-rail
Input Common Mode Voltage 0~2.45 0~2.45 input/output operational amplifier for VLSI cell libraries. Solid-State
Circuits, IEEE Journal of, 1994. 29(12): p. 1505-1513.
Output Voltage Swing high (V) 3.28 3.28
International Science Index, Electronics and Communication Engineering Vol:11, No:3, 2017 waset.org/Publication/10006593

[15] Ivanov, V.V. and I.M. Filanovsky, Operational amplifier speed and
Output Voltage Swing low(mV) 0.12 0.12 accuracy improvement: analog circuit design with structural
Settling Time (µs) 0.217 0.182 methodology. Vol. 763. 2006: Springer Science & Business Media.
[16] Hogervorst, R. and J. Huijsing, Design of low-voltage, low-power
operational amplifier cells. Vol. 374. 2013: Springer Science & Business
V. CONCLUSIONS Media.
In the paper, two op-amp designs with different unity gain [17] Loikkanen, M., Design and compensation of high performance class AB
amplifiers. Academic Dissertation, Faculty of Technology, University of
frequencies and phase margins have been discussed. A scheme Oulu, 2010.
using a combination of Miller and negative Miller
compensation was presented. In this arrangement, the op-amp
is compensated by connecting a Miller capacitor around the
first stage and the second compensation using negative Miller
around second stage of the op-amp. This configuration results
in a significant improvement the unity gain frequency with
suitable phase margin, presenting higher speed and
appropriate stability. An op-amp was designed using a 0.35
m CMOS fabrication process using the planned
compensation scheme. The total unity gain frequency of the
op-amp is increased when related to the Miller compensation
techniques with a single power supply operation.

ACKNOWLEDGMENT
The authors would like acknowledge the support for this
project from the Iraqi Ministry of Higher Education and
Scientific Research (MOHESR).

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