High Accuracy CMOS Capacitance Multiplier

Salvatore Pennisi

DEES (Dipartimento Elettrico Elettronico e Sistemistico) University of Catania, Viale Andrea Doria, 6
1-95125 CATANIA - ITALY - Phone: +39-095-73823 18: Fax: +39-095-330793: email: spennisi@dees.unict.it

ABSTRACT

This paper presents a CMOS circuit suitable to magnify

the value of a grounded unit capacitance. The
multiplicatioi factor is achieved through the gain of
current mirrors and its maximum value is solely limited
by power consumption constraints. Circuit solutions are
then developed to reduce power dissipation and to enable
the detection of small unit capacitances. Thanks to its
inherent simplicity, the circuit is also characterized by Fig. 1: Current-mode capacitance multiplier principle for
wide-band operations. An on-chip tuning technique is also a grounded capacitor C.
included which allows the value of the obtained
capacitance to be adjusted by about f70%. Simulations of ln our discussions we assume that the capacitor to be
a design example are provided. multiplied is grounded, as this situation is the most
general one.
Considering an ideally unitary voltage gain between
the gate and source terminals of the transistor, simple
1. INTRODUCTION analysis shows that the input impedance, Z,,=V,,,/l,,. is
equal to IlskC,,. Thus, the value of the capacitance
Analog integrated systems often require the connected between the source terminal and ground is
implementation of high-valued capacitors characterized effectively multiplied by the current gain k. The main
by good accuracy and linearity. This is however an advantage of this scheme (and of many of the current-
onerous task since linear capacitors -realized with two mode ones) relies on its simplicity. Moreover, the
polysilicon layers- exhibit a relatively small specific linearity and the high bandwidth of the current transfer
capacitance. Furthermore, in some sensor applications it gain, realized with current mirrors, is reflected on the
can be useful to deal with capacitance values higher than obtained capacitance value. Of course, unavoidable
those normally given by the capacitive sensors. In all nonidealities affect the circuit behavior. Basically, we
these circumstances, a circuit behaving as a capacitance have to consider the finite impedance at the gate of MI
multiplier becomes very useful. due to the generator kll, and the output of the current
Active capacitive multipliers have been developed in mirror (that we model with a resistor RI in parallel with a
the past, employing both voltage- or current-mode parasitic capacitance Cl), the output resistance of the
techniques [ 1-31, Solutions using voltage amplifiers as
source follower transistor (lig,,,), and the output
active elements (exploiting the well-known Miller effect)
impedance of the current generator IB (R2 in parallel with
can achieve high multiplication factors but are limited in
C2) Moreover, the pole in the current mirror
frequency since the voltage gain includes a relatively low
transferfunction, Q, limits the high-frequency operations.
frequency pole, moreover they require the availability of
After considering these nonidealities we get
both capacitor terminals. Current-mode techniques
provide high-frequency performance but, as will be clear
later, with reduced values of multiplication factors. In this
last case, negative Current Conveyors (CCII-) [4], current
mirrors and current amplifiers [ 5 ] have been used as
active elements. To explain the operating principle of
current-mode capacitive multiplication, consider the and the equivalent circuit of this impedance is modeled in
feedback configuration which uses a common-drain (or Fig. 2. It is seen that resistances RI and R2 affect the low-
common-collector) transistor and a current mirror with frequency circuit behaviour. However, since RZ is divided
current ratio equal to k, as schematically illustrated in Fig. by k its effect is usually the dominating one and can
I. dramatically reduce the operating frequency bandwidth

0-7803-7596-3/02/$17.00 02002 IEEE 389

for large values of k. At high frequencies the limitation is this current mirror which lastly feeds the amplified
due to the lowest pole among those introduced by the current back to the input terminal.
voltage and current transfers (g,/C,, and w,respectively). Note that to minimize the effects of the finite drain
Moreover, the minimum usable value of C,, is limited by impedance of M2, we connect the gate of M3 to the input
capacitor C, while CI causes an offset error. Finally, it is terminal, instead to a constant voltage. In this manner, M2
apparent that any error of the current mirror ratio turns and M4 operate under the same electrical and topological
directly into a gain error. conditions, thus improving the accuracy by which the
In order to improve the above solution, we propose in this current from the capacitor is sensed and allowing the
paper a novel implementation of capacitance multiplier amplification of very small unit capacitances. The AC
which reduces the effects of many of the nonidealities schematic in Fig. 4 is useful to visualize this concept. The
discussed above, thus allowing the detection and circuit represents the input section of the proposed circuit
amplification of smaller unit capacitors and enhancing the removing the unit capacitor. Assume that transistors M2
frequency performance. To improve flexibility, an and M4 are ideal voltage-controlled current-sources and
electronic tuning technique is also added enabling the on- that their finite output impedance is modeled by zO2and
chip variation of the multiplication factor. This last zd,with zO2=zo4as M2 and M4 are implementing a unitary
property is, for instance, essential to compensate for current mirror. Atter applying V,,, the output current

+°F+cl
process tolerances in continuous-time filters or integrated provided by M3 should he ideally zero, because no
sensor applications. capacitance has to be sensed. Actually, V,, causes the
small-signal current I (about equal to V,,Jzo2)to flow
through zoz, this current must be supplied by M2
(remember that MI is forced to conduct the fixed current
I*). Due to the mirror action, current I is replicated by M4
C2 ) and, since V,, is also applied to the gate of M3, it is
perfectly canceled by the current generated onto zd.Thus,
we get I;=O. In conclusion, current I, is effectively the one
flowing through the unit capacitor C, irrespective of the
& - actual impedance which subsists in parallel with C.
Fig. 2: Low-frequency equivalent circuit of the input
impedance of circuit in Fig. I.

v~~

k.18

IN
I
Fig. 4: A schematic of the input section of the proposed
circuit (removing the unit capacitor C.)

It can he noticed that, without using this technique,

the finite output impedance of M2 would strongly limit
circuit operations at low frequency. Indeed, being the
M6
current on a capacitor proportional to the frequency, for
angular frequencies much lower than l/(lz&) the current
vss through C would be much lower than that flowing through
Fig. 3: Basic idea of the proposed capacitor multiplier. io, and therefore its contribution to I; would he hardly
detectable. On the other hand, the equivalent output
resistance at the drain of M7 can be made very large using
2. THE PROPOSED SOLUTION cascoding techniques, thereby minimizing its adverse
effect at low frequencies.
The proposed circuit is shown in Fig. 3. The input Another attractive feature of the circuit is its very
transistor, M I , acts as a voltage follower and at its source small resistance exhibited at the source of M I , whose
terminal the grounded unit capacitor, C, is connected. expression is approximately l / g i r d . This, as already
Since the current through MI is constant (it is set by the
bias current generator IR) the current flowing through C is stated, improves the high-frequency performance.
sensed by transistor M2, it is then mirrored through M4 The circuit main drawback is the high power
dissipation that is proportional to the multiplication
and delivered to the current mirror M5-M7. The
capacitance factor is set by the transistor aspect ratios of factor. Indeed, the small-signal multiplication factor, k,
applies also to the quiescent current of the mirror M5-M8.

390
 rN

vss
Fig. 5: Improved capacitor multiplier.

When a large factor k is needed, this constitutes a serious

problem. To avoid the above limitation, we adopt the Note that the achieved current ratio, also applies to
solution in Fig. 5 , where the small-signal current gain is the quiescent currents in addition the small signal
obtained through the cascade of three current-mirror component. Therefore, we have to vary the bias current of
stages (M5a-M7a, M5b-M7b, and MSc-M7c). The i-th the output branch according to the tuning voltage applied
current mirror provides a current gain equal to k, so that [6]. For this reason it is convenient to apply this technique
the overall multiplication factor is k = k , k2 k;, hut the to the last current mirror in Fig. 5 , M5c-MBc, and
quiescent current of the input section of each current consequently only to its bias current generator k;18.
mirror (i.e., transistors M5-M6) is always the same and
equal to I,. Therefore, the total current dissipation of the 3. SIMULATIONS
circuit is
I Q . T ~=T (4 +ki + k2 + k; )I, (2) The circuit in Fig. 5 was simulated with SPICE and using
instead of (2+ k , k2 k& the models of a 0.8-pm CMOS process. Transistors
Finally, a tuning subsection can be incorporated in dimensions and bias settings are summarized in Table I.
the circuit. The most simple is perhaps the one which A typical behavior of the module and phase of the input
exploits triode-biased transistors (MTI-MT2) as source impedance is plotted in Fig. 7 curves a, where we set
degeneration of a generic unitary current mirror (M5- C=lpF and k=8 (kl= k2= k3=2). It can be noticed that the
MS), as illustrated in Fig. 6 [6]. If the tuning voltage, impedance is predominantly capacitive within a limited
VTUW is zero the mirror operates under balanced frequency range. Note that this range is strongly reduced
conditions, because the conductance of MT2 equals that if the gate of M3 is connected to a constant voltage as
of MTI, and Io,,,equals I,,,If V T W ~is negative (positive) shown by curves b in the same figure (and using the same
the conductance of M8 is lower (greater) than that of M7 other settings).
and I,,, is lower (greater) than I,". Therefore, their current A quantification of the frequency range where the
ratio can he varied by means of VTUNE. capacitance multiplication occurs and the related
accuracy, can be made by considering the three
parameters defined below. The first two are related to the

tJdM5
lo", 11"

bandwidth at -1" with respect to -90" and are

respectively the lower, fieL, and higher, JmH, limit
M7 frequencies. The second parameter is defined as

where f is an arbitrary frequency internal to the -1"

bandwidth. Equation (3) gives a capacitance value which
VS S is nominally equal to kC. For instance, the curves a in
Fig. 7 yieldfiSL=4.4O kHz,fi., =132kHz and Cw7.85pF,
Fig. 6: Tuning technique using triode-biased transistors with a percentage error compared to the ideal capacitance
MTI-MT2. value (8 pF) of -1.9%. As already noted, the circuit may

39 1
be useful in two different contests. The first concerns the
realization of high capacitance values, otherwise
impractical to be fabricated, and the second is to detect
and amplify very small capacitances, like those provided
by integrated sensors. To examine the circuit
performances within these two frameworks and to
understand their fundamental limitations we set different
unit capacitors ranging from 50 t T to I O pF and four
different multiplication factors, all obtained using
.5ood1.-~~............~~~~..............~~................~~
<
kl=k2=k3. These results are summarized in Table 11, and ,.MI2 .
i EmHZ I.ORHZ IUOMHZ
the case for e l 0 pF is also illustrated in Fig. 8. It is 0 n PLZi")
seen that there is an offset and a gain error. Offset is FIPg"P"C9

caused by the parasitic capacitance in parallel to Z,, Fig. 7: Module and phase of the input impedance (ZJ of
(about 25fF) and its effect becomes negligible for large the proposed circuit in Fig.5 (curves a) and with the gate
values of kC. The gain error is constant (about -2.5%) and of M3 biased at constant voltage (curves b). C = IpF and
is due to the transfer gain of the current mirrors. We see k = 8 were set in both cases.
that increasing k reduces the -Io-bandwidth. Moreover,
increasing C by a factor of 10 produces approximately the
same decrease i n h O L .In conclusion, we can obtain an
accurate magnification of unit capacitances as low as
IOOfF, and the easy realization of equivalent capacitances
in the range of several nanofarads. The tuning technique
was finally applied. In brief, by varying r/7wEfrom
+0.3V to -0.4V, C, modifies by about &70%.

Fig. 8: Magnitude and phase of the input impedance (ZJ

VDD-VSS of the circuit in Fig.5 with C=lOpF and k = 1, 8, 125,
1.5 V 1000.
] 1.6 V
Table 1. Transistors dimensions and bias settings.
4. REFERENCES

[ I ]A.DAmico, C. Di Natale, M. Mariucci, G. Baccarani, M.

Faccio, G. Ferri, F. Maloberti, P. Malcovati, G. Stochino,
"Active capacitance multiplication for sensor application" -
Sensors and Microsystems - Proc. Second Italian Coxference of
Sensors and Microsystems, Roma, Feb.1997.
[Z] G.Di Cataldo. G.Ferri, S.Pennisi, "Active capacitance
multiplication by current conveyors" Proc. IEEE ISCAs'98,
Monterey, May. 1998.
[3] G. Rincon-Mora, "Active Capacitor Multiplier in Miller-
Compensated Circuits" I€€€ Trans. on Solid-state Circuits,
Vol. 35 N.1 Jan. 2000.
[4] A. Sedrq K. Smith, "A Second-Generation Current
Conveyor and Its Applications", IEEE Trans. on Circuil
Theory, CT-I?, pp. 132-133, February 1970.
[ 5 ] G. Palmisano, G. Palumbo, S. Pennisi, CMOS Current
Amplrjers, BostonlDordrechtiLondon, Kluwer Academic
Publishers, 1999.
[6] G. Palmisano, S. Pennisi, "New CMOS Tunable
Transconductor for Filtering Applications", Proc. IEEE
ISCAS'OI, Sydney, Vol. I , pp. 196-199, May 2001.

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