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Sem IV P 406

This document contains assignments for an M.Sc. seminar on hardware description language (VHDL) and USB devices. It lists 9 students and their assigned topics to research and present on. The topics include different aspects of VHDL like processes, packages and attributes. It also includes topics on USB specifications and protocols like transactions, drivers, interfaces and common bus standards like I2C, SPI and UART.

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104 views2 pages

Sem IV P 406

This document contains assignments for an M.Sc. seminar on hardware description language (VHDL) and USB devices. It lists 9 students and their assigned topics to research and present on. The topics include different aspects of VHDL like processes, packages and attributes. It also includes topics on USB specifications and protocols like transactions, drivers, interfaces and common bus standards like I2C, SPI and UART.

Uploaded by

durg3sh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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BHAVAN'S COLLEGE ANDHERI

M. Sc. (Sem IV) Assignments for Internal Assessment (2019-20)


Roll
Name PSPH 406
No
1 Akshaya 1. Describing Hardware in VHDL, Entity, Architectures
Morajkar 2. Object , Signal, Variables, Constants, Scalar Types, Composite Types Data Types in
VHDL
3. Uses and limits, Evolution of an interface, Bus components in USB.
4. Inter Integrated Circuit (I2C), Serial Peripheral Interface (SPI),
2 Tanvi Patil 1. Concurrent Signal Assignment, Event Scheduling, Statement concurrency in
VHDL.
2. Subprograms Function, Conversion Functions, Resolution Functions,
3. Division of Labor, Developing a Device in USB.
4. Universal Asynchronous Receiver Transmitter (UART)
3 Girija R 1. Structural Designs, Sequential Behavior in VHDL.
Nbirgide 2. Packages, Package Declaration in VHDL.
3. Transfer Basics, Elements of a Transfer
4. Wire Interface, Parallel Interface
4 Shivoshree K 1. Process Statements, Process Declarative Region, Process Statement Part, Process
singh Execution in VHDL.
2. Deferred Constants, Subprogram Declaration, Package Body in VHDL.
3. USB 2.0 Transactions, Ensuring Successful Transfers, SuperSpeed Transactions.
4. RS-232 & RS-485, USB.
5 Ritesh Trhakur 1. Sequential Statements, Architecture Selection, Configuration Statements, Power of
Configurations in VHDL.
2. Different types of Attributes in VHDL.
3. Control ransfers, Bulk Transfers, Interrupt Transfers, Isochronous Transfers
4. IEEE 1394 (Firewire), Infrared (IrDA),
6 Pradeep 1. Inertial Delay, Transport Delay, Inertial Delay Model, Transport Delay Model in
Padmukhi VHDL
2. Attributes ‘EVENT and ,LAST-VALUE Attribute ‘LAST-EVENT Attribute,
‘ACTIVE and ‘LAST-ACTIVE Signal Kind Attributes in VHDL.
3. Enumeration: The Process, Descriptors.
4. Bluetooth, Wi-Fi, ZigBee,
7 Riya Thaoliyal 1. Drivers, Driver Creation, Bad Multiple Driver Model, in VHDL
2. Attribute ‘DELAYED, Attribute ‘STABLE, Attribute ‘QUIET,
Attribute TRANSACTION, Type Kind Attributes, Range Kind
Attributes in VHDL.
3. Elements of a Control Transfer, Standard Requests, Other Requests.
4. The I 2C-Bus Conceptand General Characteristics Bit Transfer
8 Drgesh K 1. Block Statements, Guarded Blocks in VHDL.
Mishra 2. Default, Component, Lower-Level Configurations in VHDL.
3. Chip Choices: Components of USB device.
4. Data validity START and STOP conditions Transferring Data , Byte format,
Acknowledge
9 Rajendra C 1. Sequential Statements, IF Statements, CASE Statements, LOOP statements, NEXT
kuwara Statement, EXIT Statement, ASSERT Statement in VHDL.
2. Port Maps, Mapping Library Entities, Generics in Configurations in VHDL.
3. Host Communicates: Device Drivers, Inside the Layers, Writing Drivers, Using GUIDs.
4. Arbitration and Clock Generation Synchronization ,Arbitration , Use of the clock
synchronizing mechanism as a handshake ,Formats with 7-Bit Addresses

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