4.

8 kHz, Ultralow Noise, 24-Bit

Sigma-Delta ADC with PGA and AC Excitation
Data Sheet AD7195
FEATURES Chromatography
AC or DC sensor excitation PLC/DCS analog input modules
RMS noise: 8.5 nV at 4.7 Hz (gain = 128) Data acquisition
16 noise-free bits at 2.4 kHz (gain = 128) Medical and scientific instrumentation
Up to 22.5 noise-free bits (gain = 1) GENERAL DESCRIPTION
Offset drift: 5 nV/°C
The AD7195 is a low noise, complete analog front end for high
Gain drift: 1 ppm/°C
precision measurement applications. It contains a low noise,
Specified drift over time
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
2 differential/4 pseudo differential input channels
The on-chip low noise gain stage means that signals of small
Automatic channel sequencer
amplitude can be interfaced directly to the ADC. The AD7195
Programmable gain (1 to 128)
contains ac excitation, which is used to remove dc-induced
Output data rate: 4.7 Hz to 4.8 kHz
offsets from bridge sensors.
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection The device can be configured to have two differential inputs or
Power supply four pseudo differential inputs. The on-chip channel sequencer
AVDD: 4.75 V to 5.25 V allows several channels to be enabled, and the AD7195 sequentially
DVDD: 2.7 V to 5.25 V converts on each enabled channel. This simplifies communication
Current: 6 mA with the part. The on-chip 4.92 MHz clock can be used as the
Temperature range: –40°C to +105°C clock source to the ADC or, alternatively, an external clock or
Package: 32-lead LFCSP crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
INTERFACE
The device has two digital filter options. The choice of filter
3-wire serial
affects the rms noise/noise-free resolution at the programmed
SPI, QSPI™, MICROWIRE™, and DSP compatible
output data rate, the settling time, and the 50 Hz/60 Hz rejec-
Schmitt trigger on SCLK
tion. For applications that require all conversions to be settled,
APPLICATIONS the AD7195 includes a zero latency feature.
Weigh scales The part operates with a 5 V analog power supply and a digital
Strain gage transducers power supply from 2.7 V to 5.25 V. It consumes a current of
Pressure measurement 6 mA. It is housed in a 32-lead LFCSP package.
Temperature measurement
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND REFIN(+) REFIN(–)

REFERENCE
DETECT
AIN1 AVDD
AIN2
AIN3 DOUT/RDY
SERIAL
AIN4 INTERFACE
MUX
PGA Σ-Δ AND
DIN
AINCOM ADC CONTROL SCLK
LOGIC
CS
SYNC
BPDSW AGND

TEMP
SENSOR
AC
EXCITATION CLOCK
CLOCK CIRCUITRY
AD7195
08771-001

ACX1 ACX1 ACX2 ACX2 MCLK1 MCLK2

Figure 1.

Rev. A Document Feedback

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AD7195 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Overview ..................................................................................... 25
Interface ............................................................................................. 1 Analog Input Channel ............................................................... 26
Applications ....................................................................................... 1 PGA .............................................................................................. 26
General Description ......................................................................... 1 Reference ..................................................................................... 26
Functional Block Diagram .............................................................. 1 Reference Detect ......................................................................... 26
Revision History ............................................................................... 2 Bipolar/Unipolar Configuration .............................................. 27
Specifications..................................................................................... 3 Data Output Coding .................................................................. 27
Timing Characteristics ................................................................ 6 Burnout Currents ....................................................................... 27
Absolute Maximum Ratings ............................................................ 8 AC Excitation .............................................................................. 27
Thermal Resistance ...................................................................... 8 Channel Sequencer .................................................................... 28
ESD Caution .................................................................................. 8 Digital Interface .......................................................................... 28
Pin Configuration and Function Descriptions ............................. 9 Reset ............................................................................................. 32
Typical Performance Characteristics ........................................... 11 System Synchronization ............................................................ 32
RMS Noise and Resolution............................................................ 13 Clock ............................................................................................ 32
Sinc Chop Disabled ................................................................... 13
4
Enable Parity ............................................................................... 32
Sinc Chop Disabled ................................................................... 14
3
Temperature Sensor ................................................................... 32
Sinc Chop Enabled .................................................................... 15
4
Bridge Power-Down Switch ...................................................... 33
Sinc Chop Enabled .................................................................... 16
3
Calibration................................................................................... 33
On-Chip Registers .......................................................................... 17 Digital Filter ................................................................................ 34
Communications Register ......................................................... 18 Sinc4 Filter (Chop Disabled) ..................................................... 34
Status Register ............................................................................. 19 Sinc3 Filter (Chop Disabled) ..................................................... 36
Mode Register ............................................................................. 19 Chop Enabled (Sinc4 Filter) ...................................................... 38
Configuration Register .............................................................. 21 Chop Enabled (Sinc3 Filter) ...................................................... 40
Data Register ............................................................................... 23 Summary of Filter Options ....................................................... 41
ID Register ................................................................................... 23 Grounding and Layout .............................................................. 42
GPOCON Register ..................................................................... 23 Applications Information .............................................................. 43
Offset Register............................................................................. 24 Weigh Scales ................................................................................ 43
Full-Scale Register ...................................................................... 24 Outline Dimensions ....................................................................... 44
ADC Circuit Information .............................................................. 25 Ordering Guide .......................................................................... 44

REVISION HISTORY
7/2017—Rev. A to Rev. B
Changed CP-32-11 to CP-32-12 .................................. Throughout
Changes to Table 5 .......................................................................... 10
Updated Outline Dimensions ....................................................... 44
Changes to Ordering Guide .......................................................... 44

1/2010—Revision 0: Initial Version

Rev. A | Page 2 of 44
Data Sheet AD7195

SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz,
TA = TMIN to TMAX, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments 1
ADC
Output Data Rate 4.7 4800 Hz Chop disabled
1.17 1200 Hz Chop enabled, sinc4 filter
1.56 1600 Hz Chop enabled, sinc3 filter
No Missing Codes 2 24 Bits FS > 1, sinc4 filter 3
24 Bits FS > 4, sinc3 filter3
Resolution See the RMS Noise and Resolution section
RMS Noise and Output See the RMS Noise and Resolution section
Data Rates
Integral Nonlinearity
Gain = 12 ±1 ±5 ppm of FSR
Gain > 1 ±5 ±15 ppm of FSR
Offset Error 4, 5 ±75/gain µV Chop disabled
±0.5 µV Chop enabled
Offset Error Drift vs. ±100/gain nV/°C Gain = 1 to 16; chop disabled
Temperature
±5 nV/°C Gain = 32 to 128; chop disabled
±5 nV/°C Chop enabled
Offset Error Drift vs. Time 25 nV/1000 Gain > 32
hours
Gain Error4 ±0.001 ±0.005 % max AVDD = 5 V, gain = 1, TA = 25°C (factory calibration
conditions)
±0.006 % Gain > 1, post internal full-scale calibration
Gain Drift vs. Temperature ±1 ppm/°C
Gain Drift vs. Time 10 ppm/1000 Gain = 1
hours
Power Supply Rejection 95 dB Gain = 1, VIN = 1 V
98 103 Gain = 8, VIN = 1 V/gain
100 110 dB Gain > 8, VIN = 1 V/gain
Common-Mode Rejection
@ DC2 100 115 dB min Gain = 1, VIN = 1 V
@ DC 115 140 dB min Gain > 1, VIN = 1 V/gain
@ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz, 60 Hz2 120 dB 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz
(60 Hz output data rate)
Normal Mode Rejection2
Sinc4 Filter
Internal Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
74 dB 50 Hz output data rate, REJ60 6 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 96 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 97 dB 60 Hz output data rate, 60 ± 1 Hz
External Clock
@ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
82 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 120 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 120 dB 60 Hz output data rate, 60 ± 1 Hz
Sinc3 Filter
Internal Clock
@ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
60 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 70 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 70 dB 60 Hz output data rate, 60 ± 1 Hz

Rev. A | Page 3 of 44
AD7195 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments 1
External Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
67 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz 95 dB 50 Hz output data rate, 50 ± 1 Hz
@ 60 Hz 95 dB 60 Hz output data rate, 60 ± 1 Hz
ANALOG INPUTS
Differential Input Voltage ±VREF/gain V VREF = REFIN(+) − REFIN(−), gain = 1 to 128
Ranges
−(AVDD − +(AVDD − V Gain > 1
1.25 V)/gain 1.25 V)/gain
Absolute AIN Voltage Limits2
Unbuffered Mode AGND − 0.05 AVDD + 0.05 V
Buffered Mode AGND + 0.25 AVDD − 0.25 V
Analog Input Current
Buffered Mode
Input Current2 −2 +2 nA Gain = 1
−4.5 +4.5 nA Gain > 1
Input Current Drift ±5 pA/°C
Unbuffered Mode
Input Current ±5 µA/V Gain = 1, input current varies with input voltage
±1 µA/V Gain > 1
Input Current Drift ±0.05 nA/V/°C External clock
±1.6 nA/V/°C Internal clock
REFERENCE INPUT
REFIN Voltage 1 AVDD AVDD V REFIN = REFIN(+) − REFIN(−). The differential input must
be limited to ±(AVDD − 1.25 V)/gain when gain > 1
Absolute REFIN Voltage GND − 0.05 AVDD + 0.05 V
Limits2
Average Reference Input 7 µA/V
Current
Average Reference Input ±0.03 nA/V/°C External clock
Current Drift
±1.3 nA/V/°C Internal clock
Normal Mode Rejection2 Same as for
analog inputs
Common-Mode Rejection 95 dB
Reference Detect Levels 0.3 0.6 V
TEMPERATURE SENSOR
Accuracy ±2 °C Applies after user calibration at 25°C
Sensitivity 2815 Codes/°C Bipolar mode
BRIDGE POWER-DOWN SWITCH
RON 10 Ω
Allowable Current2 30 mA Continuous current
BURNOUT CURRENTS
AIN Current 500 nA Analog inputs must be buffered and chop disabled
DIGITAL OUTPUTS (ACXx, ACXx )
Output High Voltage, VOH2 4 V AVDD = 5 V, ISOURCE = 200 µA
Output Low Voltage, VOL2 0.4 V AVDD = 5 V, ISINK = 800 µA
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency 4.72 5.12 MHz
Duty Cycle 50:50 %
External Clock/Crystal2
Frequency 2.4576 4.9152 5.12 MHz
Input Low Voltage VINL 0.8 V DVDD = 5 V
0.4 V DVDD = 3 V
Input High Voltage, VINH 2.5 V DVDD = 3 V
3.5 V DVDD = 5 V
Input Current −10 +10 µA

Rev. A | Page 4 of 44
Data Sheet AD7195
Parameter Min Typ Max Unit Test Conditions/Comments 1
LOGIC INPUTS
Input High Voltage, VINH2 2 V
Input Low Voltage, VINL2 0.8 V
Hysteresis2 0.1 0.25 V
Input Currents −10 +10 µA
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH2 DVDD − 0.6 V DVDD = 3 V, ISOURCE = 100 µA
Output Low Voltage, VOL2 0.4 V DVDD = 3 V, ISINK = 100 µA
Output High Voltage, VOH2 4 V DVDD = 5 V, ISOURCE = 200 µA
Output Low Voltage, VOL2 0.4 V DVDD = 5 V, ISINK = 1.6 mA
Floating-State Leakage −10 +10 µA
Current
Floating-State Output 10 pF
Capacitance
Data Output Coding Offset binary
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × FS V
Zero-Scale Calibration Limit −1.05 × FS V
Input Span 0.8 × FS 2.1 × FS V
POWER REQUIREMENTS 7
Power Supply Voltage
AVDD − AGND 4.75 5.25 V
DVDD − DGND 2.7 5.25 V
Power Supply Currents
AIDD Current 0.85 1 mA gain = 1, buffer off
1.1 1.3 mA gain = 1, buffer on
3.5 4.5 mA gain = 8, buffer off
4 5 mA gain = 8, buffer on
5 6.4 mA gain = 16 to 128, buffer off
5.5 6.9 mA gain = 16 to 128, buffer on
DIDD Current 0.35 0.4 mA DVDD = 3 V
0.5 0.6 mA DVDD = 5 V
1.5 mA External crystal used
IDD (Power-Down Mode) 2 µA
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5
The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7
Digital inputs equal to DVDD or DGND.

Rev. A | Page 5 of 44
AD7195 Data Sheet
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless
otherwise noted.

Table 2.
Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments 1, 2
READ AND WRITE OPERATIONS
t3 100 ns min SCLK high pulse width
t4 100 ns min SCLK low pulse width
READ OPERATION
t1 0 ns min CS falling edge to DOUT/RDY active time
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t2 3 0 ns min SCLK active edge to data valid delay 4
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t5 5, 6 10 ns min Bus relinquish time after CS inactive edge
80 ns max
t6 0 ns min SCLK inactive edge to CS inactive edge
t7 10 ns min SCLK inactive edge to DOUT/RDY high
WRITE OPERATION
t8 0 ns min CS falling edge to SCLK active edge setup time4
t9 30 ns min Data valid to SCLK edge setup time
t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min CS rising edge to SCLK edge hold time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.

Rev. A | Page 6 of 44
Data Sheet AD7195
Circuit and Timing Diagram
ISINK (1.6mA WITH DVDD = 5V,
100µA WITH DVDD = 3V)

TO
OUTPUT 1.6V
PIN
50pF

08771-002
ISOURCE (200µA WITH DVDD = 5V,
100µA WITH DVDD = 3V)

Figure 2. Load Circuit for Timing Characterization

CS (I)

t6
t1
t5

DOUT/RDY (O) MSB LSB

t2 t7

t3

SCLK (I)

08771-003
t4
I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

CS (I)

t8 t11

SCLK (I)

t9
t10

DIN (I) MSB LSB

08771-004

I = INPUT, O = OUTPUT

Figure 4. Write Cycle Timing Diagram

Rev. A | Page 7 of 44
AD7195 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 3. θJA is specified for the worst-case conditions, that is, a device
Parameter Rating soldered in a circuit board for surface-mount packages.
AVDD to AGND −0.3 V to +6.5 V
Table 4. Thermal Resistance
DVDD to AGND −0.3 V to +6.5 V Package Type θJA θJC Unit
AGND to DGND −0.3 V to +0.3 V 32-Lead LFCSP 32.5 32.71 °C/W
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V ESD CAUTION
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering
Reflow 260°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 8 of 44
Data Sheet AD7195

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DOUT/RDY
MCLK2
MCLK1

SYNC
SCLK

DIN

NC
CS
32
31
30
29
28
27
26
25
ACX2 1 24 DVDD
ACX2 2 23 AVDD
ACX1 3 22 DGND
ACX1 4 AD7195 21 AGND
AVDD 5 TOP VIEW 20 BPDSW
(Not to Scale)
AGND 6 19 NC
NC 7 18 REFIN(–)
AINCOM 8 17 REFIN(+)

11
10

12
13
14
15
16
NC
NC
NC
NC
AIN1
AIN2

AIN3
AIN4

08771-005
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO AGND.

Figure 5.Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 ACX2 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. In ac mode, ACX2 toggles in anti-phase with ACX1. If the ACX bit equals zero (ac
excitation turned off), the ACX2 output remains low. When toggling, it is guaranteed to be nonoverlapping
with ACX1. The nonoverlap interval between ACX1 and ACX2 is 1/(master clock) which is equal to 200 ns
when a 4.92 MHz clock is used.
2 ACX2 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. This output is the inverse of ACX2. If the ACX bit equals zero (ac excitation turned
off), the ACX2 output remains high.
3 ACX1 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. When ACX1 is high, the bridge excitation is taken as normal and when ACX1 is
low, the bridge excitation is reversed (chopped). If the Bit ACX equals zero (ac excitation turned off), the ACX1
output remains high.
4 ACX1 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac
excited bridge applications. This output is the inverse of ACX1. When ACX1 is low, the bridge excitation is
taken as normal and when ACX1 is high, the bridge excitation is reversed (chopped). If the ACX bit equals
zero (ac excitation turned off), the ACX1 output remains low.
5 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.
6 AGND Analog Ground Reference Point.
7 NC No Connect. This pin should be tied to AGND.
8 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo differential operation.
9 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN2 or as a pseudo differential input when used with AINCOM.
10 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN1 or as a pseudo differential input when used with AINCOM.
11 NC No Connect. This pin should be tied to AGND.
12 NC No Connect. This pin should be tied to AGND.
13 NC No Connect. This pin should be tied to AGND.
14 NC No Connect. This pin should be tied to AGND.
15 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudo differential input when used with AINCOM.
16 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN3 or as a pseudo differential input when used with AINCOM.
17 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can
lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD,
but the part functions with a reference from 1 V to AVDD.
18 REFIN(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V.
19 NC No Connect. This pin should be tied to AGND.
Rev. A | Page 9 of 44
AD7195 Data Sheet
Pin No. Mnemonic Description
20 BPDSW Bridge Power-Down Switch to AGND.
21 AGND Analog Ground Reference Point.
22 DGND Digital Ground Reference Point.
23 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.
24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD.
25 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7195 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally
to DVDD.
26 NC No Connect. This pin should be tied to AGND.
27 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the appro-
priate register.
29 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
30 MCLK2 Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.
31 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
32 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
EPAD Exposed Pad. Connect the exposed pad to AGND.

Rev. A | Page 10 of 44
Data Sheet AD7195

TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760 30

8,388,758
25

8,388,756
20

FREQUENCY
8,388,754
CODE

15
8,388,752

10
8,388,750

8,388,748 5

8,388,746 0

08771-009
08771-006
0 200 400 600 800 1000 8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920
SAMPLE CODE

Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Figure 9. Noise Distribution Histogram (VREF = 5 V,
Chop Disabled, Sinc4 Filter) Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
250 8,388,820

8,388,800

200 8,388,780

8,388,760
FREQUENCY

150 8,388,740
CODE

8,388,720

100 8,388,700

8,388,680

50 8,388,660

8,388,640

0 8,388,620

08771-010
8,388,746

8,388,748

8,388,750

8,388,752

8,388,754

8,388,756

8,388,758

8,388,760

0 100 200 300 400 500 600 700 800 900 1000
08771-007

SAMPLES

CODE

Figure 7. Noise Distribution Histogram (VREF = 5 V, Figure 10. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 1,
Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Chop Disabled, Sinc4 Filter)
8,388,950 80

8,388,900
70
8,388,850
60
8,388,800
50
FREQUENCY

8,388,750
CODE

8,388,700 40

8,388,650
30
8,388,600
20
8,388,550
10
8,388,500

8,388,450 0
08771-011
08771-008

0 100 200 300 400 500 600 700 800 900 1000 8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820
SAMPLES CODE

Figure 8. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Figure 11. Noise Distribution Histogram (VREF = 5 V,
Chop Disabled, Sinc4 Filter) Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc4 Filter)

Rev. A | Page 11 of 44
AD7195 Data Sheet
3.0 0

–0.1
2.0

–0.2
1.0
INL (ppm of FSR)

OFFSET (µV)
–0.3
0
–0.4

–1.0
–0.5

–2.0
–0.6

–3.0 –0.7

08771-015
08771-012
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –60 –40 –20 0 20 40 60 80 100 120
VIN (V) TEMERATURE (°C)

Figure 12. INL (Gain = 1) Figure 15. Offset Error (Gain = 128, Chop Disabled)
6 1.000008

1.000007
4

1.000006
2
INL (ppm of FSR)

1.000005
GAIN

0 1.000004

1.000003
–2

1.000002
–4
1.000001

–6 1.000000

08771-016
08771-013

–0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020 –60 –40 –20 0 20 40 60 80 100 120
VIN (V) TEMPERATURE (°C)

Figure 13. INL (Gain = 128) Figure 16. Gain Error (Gain = 1, Chop Disabled)
66 128.003

128.002
64
OUTPUT VOLTAGE (µV)

128.001
62

128.000
GAIN

60
127.999

58
127.998

56
127.997

54 127.996
08771-017
08771-014

–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 14. Offset Error (Gain = 1, Chop Disabled) Figure 17. Gain Error (Gain = 128, Chop Disabled)

Rev. A | Page 12 of 44
Data Sheet AD7195

RMS NOISE AND RESOLUTION

The tables in this section show the rms noise, peak-to-peak generated with a differential input voltage of 0 V when the ADC
noise, effective resolution, and noise-free (peak-to-peak) resolu- is continuously converting on a single channel. It is important
tion of the AD7195 for various output data rates and gain settings, to note that the effective resolution is calculated using the rms
with chop disabled and chop enabled for the sinc4 and sinc3 noise, whereas the peak-to-peak resolution is calculated based
filters. The numbers given are for the bipolar input range with on peak-to-peak noise. The peak-to-peak resolution represents
the external 5 V reference. These numbers are typical and are the resolution for which there is no code flicker.

SINC4 CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 4.7 852.5 280 96 50 22 10 8.5
640 7.5 533 390 120 54 28 12 10.5
480 10 400 470 130 56 31 14 11.5
96 50 80 1000 150 78 45 33 28
80 60 66.7 1100 170 88 52 36 31
32 150 26.7 1460 220 125 75 55 48
16 300 13.3 1900 285 170 100 75 67
5 960 4.17 3000 480 280 175 140 121
2 2400 1.67 5000 780 440 280 220 198
1 4800 0.83 14,300 1920 1000 550 380 295

Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 4.7 852.5 1600 500 250 130 65 56
640 7.5 533 2200 650 290 150 80 65
480 10 400 3000 670 300 190 100 70
96 50 80 6000 900 450 280 180 170
80 60 66.7 7200 1100 480 300 220 190
32 150 26.7 8300 1500 750 410 340 310
16 300 13.3 11,000 1700 1000 600 440 430
5 960 4.17 20,000 3000 1800 1100 810 710
2 2400 1.67 32,000 5100 2800 1700 1400 1200
1 4800 0.83 86,000 13,000 6000 3500 2400 1900

Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 1 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
1023 4.7 852.5 24 (22.6) 23.6 (21.3) 23.6 (21.3) 23.6 (21.2) 23.6 (21.2) 23.1 (20.4)
640 7.5 533 24 (22.1) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 23.4 (20.9) 22.8 (20.2)
480 10 400 24 (21.7) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.6) 22.7 (20.1)
96 50 80 23.3 (20.7) 23 (20.4) 22.9 (20.4) 22.7 (20.1) 22.2 (19.7) 21.4 (18.8)
80 60 66.7 23.1 (20.4) 22.8 (20.1) 22.8 (20) 22.5 (20 ) 22.1 (19.4) 21.3 (18.6)
32 150 26.7 22.7 (20.2) 22.4 (19.7) 22.3 (19.7) 22 (19.5) 21.5 (18.8) 20.6 (17.9)
16 300 13.3 22.3 (19.8) 22.1 (19.5) 21.8 (19.3) 21.6 (19) 21 (18.4) 20.1 (17.5)
5 960 4.17 21.7 (18.9) 21.3 (18.7) 21.1 (18.4) 20.8 (18.1) 20.2 (17.6) 19.3 (16.7)
2 2400 1.67 20.9 (18.3) 20.6 (17.9) 20.4 (17.7) 20.1 (17.5) 19.5 (16.8) 18.6 (16)
1 4800 0.83 19.4 (16.8) 19.3 (16.6) 19.3 (16.4) 19.1 (16.4) 18.8 (16) 18 (15.3)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. A | Page 13 of 44
AD7195 Data Sheet
SINC3 CHOP DISABLED
Table 9. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 4.7 639.4 290 125 53 24 10.5 9
640 7.5 400 470 135 56 29 13 11.5
480 10 300 610 145 58 32 16 12.5
96 50 60 1100 160 86 50 35 29
80 60 50 1200 170 95 55 40 32
32 150 20 1500 230 130 80 58 50
16 300 10 1950 308 175 110 83 73
5 960 3.13 4000 590 330 200 150 133
2 2400 1.25 56,600 7000 3500 1800 900 490
1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450

Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 4.7 639.4 1700 750 260 140 65 56
640 7.5 400 2400 800 340 150 84 60
480 10 300 3000 900 360 200 100 70
96 50 60 6600 1000 480 290 200 180
80 60 50 6800 1100 600 300 240 200
32 150 20 8900 1400 710 470 360 310
16 300 10 13,000 2000 1000 670 470 500
5 960 3.13 25,000 3400 2200 1200 850 800
2 2400 1.25 310,000 41,000 22,000 12,000 5600 3100
1 4800 0.625 2,600,000 300,000 170,000 79,000 41,000 24,000

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 1 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
1023 4.7 639.4 24 (22.5) 23.5 (21) 23.5 (21) 23.5 (21) 23.5 (21) 23 (20.4)
640 7.5 400 24 (22) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 23.3 (20.8) 22.7 (20.3)
480 10 300 24 (22) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 23.2 (20.5) 22.6 (20.1)
96 50 60 23.1 (20.5) 22.9 (20.3) 22.8 (20.3) 22.6 (20) 22.1 (19.6) 21.4 (18.7)
80 60 50 23 (20.5) 22.8 (20.1) 22.6 (20) 22.4 (20) 21.9 (19.3) 21.2 (18.6)
32 150 20 22.7 (20) 22.4 (19.8) 22.2 (19.7) 21.9 (19.3) 21.4 (18.7) 20.6 (17.9)
16 300 10 22.3 (19.5) 22 (19.3) 21.8 (19.3) 21.4 (18.8) 20.8 (18.3) 20 (17.3)
5 960 3.13 21.3 (18.5) 21 (18.5) 20.9 (18.1) 20.6 (18) 20 (17.5) 19.2 (16.6)
2 2400 1.25 17.4 (14.9) 17.4 (14.9) 17.4 (14.8) 17.4 (14.7) 17.4 (14.7) 17.3 (14.6)
1 4800 0.625 14.5 (11.9) 14.5 (11.9) 14.4 (11.8) 14.4 (11.8) 14.4 (11.8) 14.4 (11.7)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. A | Page 14 of 44
Data Sheet AD7195
SINC4 CHOP ENABLED
Table 12. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 1.175 1702 198 85 41 18 7 6
640 1.875 1067 276 92 45 22 8.5 7
480 2.5 800 332 99 46 23 10 8
96 12.5 160 707 127 61 34 23 18
80 15 133 778 141 62 35 24 21
32 37.5 53.3 990 156 85 51 38 33
16 75 26.7 1344 191 106 67 51 45
5 240 8.33 2192 325 184 120 92 78
2 600 3.33 3606 523 297 191 148 134
1 1200 1.67 9900 1345 680 368 248 200

Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 1.175 1702 1131 474 212 92 46 40
640 1.875 1067 1556 495 248 106 57 46
480 2.5 800 2121 530 255 134 71 50
96 12.5 160 4243 707 368 198 127 120
80 15 133 5091 849 424 212 156 134
32 37.5 53.3 5870 1061 530 290 240 219
16 75 26.7 7780 1202 707 424 311 304
5 240 8.33 14,142 2121 1273 778 573 502
2 600 3.33 22,627 3606 1980 1202 990 850
1 1200 1.67 60,800 9192 4950 2475 1697 1345

Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 1 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
1023 1.175 1702 24 (23.1) 24 (21.8) 24 (21.8) 24 (21.7) 24 (21.7) 23.6 (20.9)
640 1.875 1067 24 (22.6) 23.9 (21.4) 23.9 (21.4) 23.9 (21.4) 23.9 (21.4) 23.3 (20.7)
480 2.5 800 24 (22.2) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.8 (21.1) 23.2 (20.6)
96 12.5 160 23.8 (21.2) 23.5 (20.9) 23.4 (20.9) 23.2 (20.6) 22.7 (20.2) 21.9 (19.3)
80 15 133 23.6 (20.9) 23.3 (20.6) 23.3 (20.5) 23 (20.5) 22.6 (19.9) 21.8 (19.1)
32 37.5 53.3 23.2 (20.7) 22.9 (20.2) 22.8 (20.2) 22.5 (20) 22 (19.3) 21.1 (18.4)
16 75 26.7 22.8 (20.3) 22.6 (20) 22.3 (19.8) 22.1 (19.5) 21.5 (18.9) 20.6 (18)
5 240 8.33 22.2 (19.4) 21.8 (19.2) 21.6 (18.9) 21.3 (18.6) 20.7 (18.1) 19.8 (17.2)
2 600 3.33 21.4 (18.8) 21.1 (18.4) 20.9 (18.2) 20.6 (18) 20 (17.3) 19.1 (16.5)
1 1200 1.67 19.9 (17.3) 19.8 (17.1) 19.8 (16.9) 19.6 (16.9) 19.3 (16.5) 18.5 (15.8)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.
When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode.

Rev. A | Page 15 of 44
AD7195 Data Sheet
SINC3 CHOP ENABLED
Table 15. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 1.56 1282 205 88 37 17 7.5 6.5
640 2.5 800 332 95 40 21 9 8
480 3.33 600 431 103 41 23 11.5 9
96 16.6 120 778 113 61 35 25 21
80 20 100 849 120 67 39 28 23
32 50 40 1061 163 92 57 41 35
16 100 20 1379 218 124 78 59 52
5 320 6.25 2828 417 233 141 106 94
2 800 2.5 40,022 4950 2475 1273 636 346
1 1600 1.25 312,540 38,890 19,800 9900 4950 2440

Table 16. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023 1.56 1282 1202 530 184 92 46 40
640 2.5 800 1697 566 240 120 59 42
480 3.33 600 2121 636 255 141 71 49
96 16.6 120 4667 686 318 198 141 127
80 20 100 4808 707 424 205 170 141
32 50 40 6293 990 474 382 255 219
16 100 20 9192 1414 707 474 332 354
5 320 6.25 17,680 2404 1556 849 601 566
2 800 2.5 219,200 29,000 15,560 8485 3960 2192
1 1600 1.25 1,838,500 212,200 120,200 55,870 29,000 16,970

Table 17. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word Output Data Settling
(Decimal) Rate (Hz) Time (ms) Gain of 1 1 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281
1023 1.56 1282 24 (23) 24 (21.5) 24 (21.5) 24 (21.5) 24 (21.5) 23.5 (20.9)
640 2.5 800 24 (22.5) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.8 (21.3) 23.2 (20.8)
480 3.33 600 24 (22.5) 23.7 (21) 23.7 (21) 23.7 (21) 23.7 (21) 23.1 (20.6)
96 16.6 120 23.6 (21) 23.4 (20.8) 23.3 (20.8) 23.1 (20.5) 22.6 (20.1) 21.9 (19.2)
80 20 100 23.5 (21) 23.3 (20.6) 23.1 (20.5) 22.9 (20.5) 22.4 (19.8) 21.7 (19.1)
32 320 40 23.2 (20.5) 22.9 (20.3) 22.7 (20.2) 22.4 (19.8) 21.9 (19.2) 21.1 (18.4)
16 100 20 22.8 (20) 22.5 (19.8) 22.3 (19.8) 21.9 (19.3) 21.3 (18.8) 20.5 (17.8)
5 320 6.25 21.8 (19) 21.5 (19) 21.4 (18.6) 21.1 (18.5) 20.5 (18) 19.7 (17.1)
2 800 2.5 17.9 (15.4) 17.9 (15.4) 17.9 (15.3) 17.9 (15.2) 17.9 (15.2) 17.8 (15.1)
1 1600 1.25 15 (12.4) 15 (12.4) 14.9 (12.3) 14.9 (12.3) 14.9 (12.3) 14.9 (12.2)
1
The output peak-to-peak (p-p) resolution is listed in parentheses.
When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode.

Rev. A | Page 16 of 44
Data Sheet AD7195

ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions,
the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.

Table 18. Register Summary

Register Addr. Dir. Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Communications 00 W 00 WEN R/W Register address CREAD 0 0
Status 00 R 80 RDY ERR NOREF PARITY 0 CHD2 CHD1 CHD0
Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 0 0
SINC3 0 ENPAR 0 SINGLE REJ60 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)
Configuration 02 R/W 000117 Chop (MSB) ACX 0 0 0 0 0 0
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
BURN REFDET 0 BUF U/B G2 G1 G0 (LSB)
Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
ID 04 R A6 1 0 1 0 0 1 1 0
GPOCON 05 R/W 00 0 BPDSW 0 0 0 0 0 0
Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16
OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB)
Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16
FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)

Rev. A | Page 17 of 44
AD7195 Data Sheet
COMMUNICATIONS REGISTER state of the interface and, on power-up or after a reset, the
(RS2, RS1, RS0 = 0, 0, 0) ADC is in this default state waiting for a write operation to
the communications register. In situations where the interface
The communications register is an 8-bit write-only register. sequence is lost, a write operation of at least 40 serial clock
All communications to the part must start with a write cycles with DIN high returns the ADC to this default state by
operation to the communications register. The data written resetting the entire part. Table 19 outlines the bit designations
to the communications register determines whether the next for the communications register. CR0 through CR7 indicate the
operation is a read or a write operation and in which register bit location, CR denoting that the bits are in the communications
this operation takes place. For read or write operations, when register. CR7 denotes the first bit of the data stream. The
the subsequent read or write operation to the selected register number in parentheses indicates the power-on/reset default
is complete, the interface returns to where it expects a write status of that bit.
operation to the communications register. This is the default

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0 0

Table 19. Communications Register Bit Designations

Bit Location Bit Name Description
CR7 WEN Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is
the first bit written, the part does not clock on to subsequent bits in the register; rather, it stays at this bit
location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to
the communications register. Idling the DIN pin high between data transfers minimizes the effects of
spurious SCLK pulses on the serial interface.
CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during
the serial interface communication (see Table 20).
CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read; that is, the contents of the data
register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin
goes low to indicate that a conversion is complete. The communications register does not have to be
written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written
to the communications register. To disable continuous read, the Instruction 01011000 must be written to
the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors
activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset
occurs if 40 consecutive 1s are seen on DIN. Therefore, hold DIN low until an instruction is written to the
device.
CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation.

Table 20. Register Selection

RS2 RS1 RS0 Register Register Size
0 0 0 Communications register during a write operation 8 bits
0 0 0 Status register during a read operation 8 bits
0 0 1 Mode register 24 bits
0 1 0 Configuration register 24 bits
0 1 1 Data register/data register plus status information 24 bits/32 bits
1 0 0 ID register 8 bits
1 0 1 GPOCON register 8 bits
1 1 0 Offset register 24 bits
1 1 1 Full-scale register 24 bits

Rev. A | Page 18 of 44
Data Sheet AD7195
STATUS REGISTER
(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 21 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data
stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1) ERR(0) NOREF(0) PARITY(0) 0 CHD2(0) CHD1(0) CHD0(0)

Table 21. Status Register Bit Designations

Bit Location Bit Name Description
SR7 RDY Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set
automatically after the ADC data register is read, or a period of time before the data register is updated,
with a new conversion result to indicate to the user that the conversion data should not be read. It is also
set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a
conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status
register for monitoring the ADC for conversion data.
SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result
written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or under-
range, or the absence of a reference voltage. This bit is cleared when the result written to the data register
is within the allowed analog input range again.
SR5 NOREF No external reference bit. This bit is set to indicate that the reference is at a voltage that is below a specified
threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid
reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in
the configuration register to 1.
SR4 PARITY Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is
an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register.
The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is
set, the contents of the status register are transmitted along with the data for each data register read.
SR3 0 This bit is set to 0.
SR2 to SR0 CHD2 to These bits indicate which channel corresponds to the data register contents. They do not indicate which
CHD0 channel is presently being converted but indicate which channel was selected when the conversion
contained in the data register was generated.

MODE REGISTER
(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)
The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, the output data rate, and the clock source. Table 22 outlines the bit designations for the mode register. MR0 through
MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and
filter and sets the RDY bit.
MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8
SINC3(0) 0 ENPAR(0) 0 SINGLE(0) REJ60(0) FS9(0) FS8(0)
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)

Rev. A | Page 19 of 44
AD7195 Data Sheet

Table 22. Mode Register Bit Designations

Bit Location Bit Name Description
MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7195 (see Table 23).
MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When
DAT_STA is set, the contents of the status register are transmitted along with each data register read.
This function is useful when several channels are selected because the status register identifies the
channel to which the data register value corresponds.
MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7195. Either the on-chip 4.92 MHz clock or an external
clock can be used. The ability to use an external clock allows several AD7195 devices to be synchro-
nized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7195.
CLK1 CLK0 ADC Clock Source
0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2.
0 1 External clock. The external clock is applied to the MCLK2 pin.
1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated.
1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2.
MR17, MR16 0 These bits must be programmed with a Logic 0 for correct operation.
MR15 SINC3 Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,
the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time.
For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a
settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no
missing codes for a given output data rate. At higher output data rates (FS values less than 5), the
sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes.
MR14 0 This bit must be programmed with a Logic 0 for correct operation.
MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit
in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the
contents of the status register are transmitted along with the data for each data register read.
MR12 0 This bit must be programmed with a Logic 0 for correct operation.
MR11 SINGLE Single cycle conversion enable bit. When this bit is set, the AD7195 settles in one conversion cycle so
that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected.
MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
MR9 to MR0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise (and, therefore, the effective
resolution) of the device (see Table 6 through Table 17). When chop is disabled and continuous
conversion mode is selected,
Output Data Rate = (MCLK/1024)/FS
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data
rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data
rate when converting on a single channel. When chop is enabled,
Output Data Rate = (MCLK/1024)/(N × FS)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate
from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency
is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output
data rate/2).

Rev. A | Page 20 of 44
Data Sheet AD7195

Table 23. Operating Modes

MD2 MD1 MD0 Mode
0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs
conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register
go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the commu-
nications register to 1, which enables continuous read. When continuous read is enabled, the conversions are
automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC
to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration
of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent
conversions are available at the selected output data rate, which is dependent on filter choice.
0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then
performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in
the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data
register until another conversion is performed. RDY remains active (low) until the data is read or another conversion
is performed.
0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are
still provided.
0 1 1 Power-down mode. In power-down mode, all AD7195 circuitry, except the bridge power-down switch, is powered
down. The bridge power-down switch remains active because the user may need to power up the sensor prior to
powering up the AD7195 for settling reasons. The external crystal, if selected, remains active.
1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed
in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the
selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-
scale error.
1 1 0 System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required
each time the gain of a channel is changed.
1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required
each time the gain of a channel is changed.

CONFIGURATION REGISTER
(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)
The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to
configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the
gain, and to select the analog input channel. Table 24 outlines the bit designations for the filter register. CON0 through CON23 indicate
the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number
in parentheses indicates the power-on/reset default status of that bit.
CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16
CHOP(0) ACX(0) 0 0 0 0 0 0
CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8
CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1)
CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0
BURN(0) REFDET(0) 0 BUF(1) U/B (0) G2(1) G1(1) G0(1)

Rev. A | Page 21 of 44
AD7195 Data Sheet

Table 24. Configuration Register Bit Designations

Bit Location Bit Name Description
CON23 CHOP Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is
enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed.
However, this increases the conversion time and settling time of the ADC. For example, when FS = 96
decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the
settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word
of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms.
However, at low gains, periodic calibrations may be required to remove the offset and offset drift.
When ax excitation is enabled, chop must be enabled also.
CON22 ACX AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For
dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the
AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles
(that is, chopped). Note that when the AD7195 is performing internal zero-scale or full-scale calibra-
tions, the ACX bit is treated as a 0, that is, the device performs these self-calibrations with dc excitation.
TheBitCHOP must be set to 1 when ac excitation is enabled.
CON21 to CON16 0 These bits must be programmed with a Logic 0 for correct operation.
CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7195 (see Table 25).
Several channels can be selected, and the AD7195 automatically sequences them. The conversion on
each channel requires the complete settling time. When performing calibrations or when accessing the
calibration registers, only one channel can be selected.
CON7 BURN When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
CON5 0 This bit must be programmed with a Logic 0 for correct operation.
CON4 BUF Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the
power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to
place source impedances on the front end without contributing gain errors to the system. With the
buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above
AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin
must be limited to 250 mV within the power supply rails.
CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar
operation is selected.
CON2 to CON0 G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows:
G2 G1 G0 Gain ADC Input Range (5 V Reference)
0 0 0 1 ±5 V
0 0 1 Reserved
0 1 0 Reserved
0 1 1 8 ±625 mV
1 0 0 16 ±312.5 mV
1 0 1 32 ±156.2 mV
1 1 0 64 ±78.125 mV
1 1 1 128 ±39.06 mV

Rev. A | Page 22 of 44
Data Sheet AD7195
Table 25. Channel Selection
Channel Enable Bits in the Configuration Register Channel Enabled
Positive Input Negative Input Status Register Calibration
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 AIN(+) AIN(−) Bits CHD[2:0] Register Pair
1 AIN1 AIN2 000 0
1 AIN3 AIN4 001 1
1 Temperature sensor 010 None
1 AIN2 AIN2 011 0
1 AIN1 AINCOM 100 0
1 AIN2 AINCOM 101 1
1 AIN3 AINCOM 110 2
1 AIN4 AINCOM 111 3

DATA REGISTER
(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation
from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are
appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status
register (CHD2 to CHD0) identify the channel from which the conversion originated.

ID REGISTER
(RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xA6)
The identification number for the AD7195 is stored in the ID register. This is a read-only register.

GPOCON REGISTER
(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)
The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the
general-purpose digital outputs.
Table 26 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are
in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default
status of that bit.
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
0 BPDSW(0) 0 0 0 0 0 0

Table 26. Register Bit Designations

Bit Location Bit Name Description
GP7 0 This bit must be programmed with a Logic 0 for correct operation.
GP 6 BPDSW Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch
BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-
down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.
GP5 to GP0 0 These bits must be programmed with a Logic 0 for correct operation.

Rev. A | Page 23 of 44
AD7195 Data Sheet

OFFSET REGISTER FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)
The offset register holds the offset calibration coefficient for the The full-scale register is a 24-bit register that holds the full-scale
ADC. The power-on reset value of the offset register is calibration coefficient for the ADC. The AD7195 has four full-
0x800000. The AD7195 has four offset registers; therefore, each scale registers; therefore, each channel has a dedicated full-scale
channel has a dedicated offset register (see Table 25). Each of register (see Table 25). The full-scale registers are read/write
these registers is a 24-bit read/write register. This register is registers. However, when writing to the full-scale registers, the
used in conjunction with its associated full-scale register to ADC must be placed in power-down mode or idle mode. These
form a register pair. The power-on reset value is automatically registers are configured at power-on with factory-calibrated
overwritten if an internal or system zero-scale calibration is full-scale calibration coefficients, the calibration being performed
initiated by the user. The AD7195 must be placed in power- at gain = 1. Therefore, every device has different default coeffic-
down mode or idle mode when writing to the offset register. ients. The default value is automatically overwritten if an
internal or system full-scale calibration is initiated by the user
or if the full-scale register is written to.

Rev. A | Page 24 of 44
Data Sheet AD7195

ADC CIRCUIT INFORMATION

AVDD AGND DVDD DGND REFIN(+) REFIN(–)

REFERENCE
DETECT
AIN1 AVDD
AIN2
AIN3 DOUT/RDY
SERIAL
AIN4 INTERFACE
MUX
PGA Σ-Δ AND
DIN
AINCOM ADC CONTROL SCLK
LOGIC
CS
SYNC
BPDSW AGND

TEMP
SENSOR
AC
EXCITATION CLOCK
CLOCK CIRCUITRY
AD7195

08771-001
ACX1 ACX1 ACX2 ACX2 MCLK1 MCLK2

Figure 18. Block Diagram

OVERVIEW Σ-Δ ADC and Filter

The AD7195 is an ultralow noise ADC that incorporates a Σ-Δ The AD7195 contains a fourth-order Σ-Δ modulator followed
modulator, a buffer, PGA, and on-chip digital filtering intended by a digital filter. The device offers the following filter options:
for the measurement of wide dynamic range signals, such as • Sinc4
those in pressure transducers, weigh scales, and strain gage • Sinc3
applications. Figure 18 shows the block diagram for the part. • Chop enabled/disabled
Analog Inputs • Zero latency
The device can be configured to have two differential or four AC Excitation
pseudo differential analog inputs. The analog inputs can be
The AD7195 supports ac excitation of load cells. It provides the
buffered or unbuffered.
four logic outputs needed to control the transistors in an ac
Multiplexer excited load cell design.
The on-chip multiplexer increases the channel count of the Serial Interface
device. Because the multiplexer is included on chip, any
The AD7195 has a 4-wire SPI. The on-chip registers are
channel changes are synchronized with the conversion process.
accessed via the serial interface.
PGA
Clock
The analog input signal can be amplified using the PGA. The
The AD7195 has an internal 4.92 MHz clock. Either this clock
PGA allows gains of 1, 8, 16, 32, 64, and 128.
or an external clock can be used as the clock source to the
Reference Detect AD7195. The internal clock can also be made available on a
The AD7195 is capable of monitoring the external reference. If pin if a clock source is required for external circuitry.
the reference is not present, a flag is set in the status register of Temperature Sensor
the device.
The on-chip temperature sensor monitors the die temperature.
Burnout Currents
Two 500 nA burnout currents are included on-chip to detect Calibration
the presence of the external sensor. Both internal and system calibration are included on chip; thus,
the user has the option of removing offset/gain errors internal
to the AD7195 only, or removing the offset/gain errors of the
complete end system.

Rev. A | Page 25 of 44
AD7195 Data Sheet
ANALOG INPUT CHANNEL AD7195 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain
The AD7195 has two differential/four pseudo differential in bipolar mode.
analog input channels, which can be buffered or unbuffered. In REFERENCE
buffered mode (the BUF bit in the configuration register is set The ADC has a fully differential input capability for the refer-
to 1), the input channel feeds into a high impedance input stage ence channel. The common-mode range for these differential
of the buffer amplifier. Therefore, the input can tolerate signi- inputs is from AGND to AVDD. The reference voltage REFIN
ficant source impedances and is tailored for direct connection (REFIN(+) − REFIN(−)) is AVDD nominal, but the AD7195
to external resistive-type sensors such as strain gages or resis- is functional with reference voltages from 1 V to AVDD. In
tance temperature detectors (RTDs). applications where the excitation (voltage or current) for the
When BUF = 0, the part operates in unbuffered mode. This transducer on the analog input also drives the reference voltage
results in a higher analog input current. Note that this unbuffered for the part, the effect of the low frequency noise in the excita-
input path provides a dynamic load to the driving source. tion source is removed because the application is ratiometric. If
Therefore, resistor/capacitor combinations on the input pins the AD7195 is used in a nonratiometric application, a low noise
can cause gain errors, depending on the output impedance of reference should be used.
the source that is driving the ADC input. Table 27 shows the The reference input is unbuffered; therefore, excessive R-C
allowable external resistance/capacitance values for unbuffered source impedances introduce gain errors. R-C values similar
mode at a gain of 1 such that no gain error at the 20-bit level is to those in Table 27 are recommended for the reference inputs.
introduced. Deriving the reference input voltage across an external resistor
Table 27. External R-C Combination for No 20-Bit Gain Error means that the reference input sees significant external source
C (pF) R (Ω) impedance. External decoupling on the REFINx pins is not
50 1.4 k recommended in this type of circuit configuration. Conversely,
100 850 if large decoupling capacitors are used on the reference inputs,
500 300 there should be no resistors in series with the reference inputs.
1000 230 Recommended 2.5 V reference voltage sources for the AD7195
5000 30 include the ADR421 and ADR431, which are low noise references.
The absolute input voltage range in buffered mode is restricted These references tolerate decoupling capacitors on REFIN(+)
to a range between AGND + 250 mV and AVDD − 250 mV. Care without introducing gain errors in the system. Figure 19 shows the
must be taken in setting up the common-mode voltage so that recommended connections between the ADR421 and the AD7195.
these limits are not exceeded. Otherwise, linearity and noise AVDD
ADR421 AD7195
performance degrades.
2 VIN VOUT 6 REFINx(+)
The absolute input voltage in unbuffered mode includes the 0.1µF 10µF 4.7µF
range between AGND − 50 mV and AVDD + 50 mV. The
negative absolute input voltage limit does allow the possibility 4 GND TRIM 5 REFINx(–)

08771-037
of monitoring small true bipolar signals with respect to AGND.
PGA Figure 19. ADR421 to AD7195 Connections

When the gain stage is enabled, the output from the buffer REFERENCE DETECT
is applied to the input of the PGA. The presence of the PGA
The AD7195 includes on-chip circuitry to detect whether the
means that signals of small amplitude can be gained within the
part has a valid reference for conversions or calibrations. This
AD7195 while still maintaining excellent noise performance.
feature is enabled when the REFDET bit in the configuration
For example, when the gain is set to 128, the rms noise is 8.5 nV,
register is set to 1. If the voltage between the REFIN(+) and
typically, when the output data rate is 4.7 Hz, which is equivalent
REFIN(−) pins is between 0.3 V and 0.6 V, the AD7195 detects
to 23 bits of effective resolution or 20.5 bits of noise-free resolution.
that it no longer has a valid reference. In this case, the NOREF
The AD7195 can be programmed to have a gain of 1, 8, 16, 32, bit of the status register is set to 1. If the AD7195 is performing
64, and 128 using Bit G2 to Bit G0 in the configuration register. normal conversions and the NOREF bit becomes active, the
Therefore, with an external 2.5 V reference, the unipolar ranges conversion result is all 1s.
are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar
Therefore, it is not necessary to continuously monitor the status
ranges are from ±19.53 mV to ±2.5 V.
of the NOREF bit when performing conversions. It is only
The analog input range must be limited to ±(AVDD − 1.25 V)/gain necessary to verify its status if the conversion result read from
because the PGA requires some headroom. Therefore, if AVDD = the ADC data register is all 1s. If the AD7195 is performing
5 V, the maximum analog input that can be applied to the either an offset or full-scale calibration and the NOREF bit
becomes active, the updating of the respective calibration
Rev. A | Page 26 of 44
Data Sheet AD7195
registers is inhibited to avoid loading incorrect coefficients to turned on, they flow in the external transducer circuit, and a
these registers, and the ERR bit in the status register is set. If measurement of the input voltage on the analog input channel
the user is concerned about verifying that a valid reference is can be taken. It will take some time for the burnout currents to
in place every time a calibration is performed, the status of the detect an open circuit condition as the currents will need to
ERR bit should be checked at the end of the calibration cycle. charge any external capacitors
BIPOLAR/UNIPOLAR CONFIGURATION There are several reasons why a fault condition might be
The analog input to the AD7195 can accept either unipolar or detected. The front-end sensor may be open circuit. The front-
bipolar input voltage ranges. A bipolar input range does not end sensor may be overloaded, or the reference may be absent
imply that the part can tolerate negative voltages with respect and the NOREF bit in the status register is set, thus clamping
to system AGND. In pseudo differential mode, signals are the data to all 1s. Check these possibilities first. If the voltage
referenced to AINCOM while in differential mode, signals are measured is 0 V, it may indicate that the transducer has short
referenced to the negative input of the differential pair. For circuited. The current sources work over the normal absolute
example, if AINCOM is 2.5 V and the AD7195 AIN1 analog input voltage range specifications when the analog inputs are
input is configured for unipolar mode with a gain of 2, the input buffered and chop is disabled.
voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V AC EXCITATION
reference is used. If AINCOM is 2.5 V and the AD7195 AIN1
analog input is configured for bipolar mode with a gain of 2, the AC excitation of the bridge addresses many of the concerns
analog input range on AIN1 is 1.25 V to 3.75 V. with thermocouple, offset, and drift effects encountered in
dc excited applications. In ac excitation, the polarity of the
The bipolar/unipolar option is chosen by programming the U/B excitation voltage to the bridge is reversed on alternate
bit in the configuration register. cycles. The result is the elimination of dc errors at the
DATA OUTPUT CODING expense of a more complex system design. Figure 50 outlines
the connections for an ac excited bridge application based
When the ADC is configured for unipolar operation, the output
on the AD7195.
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 00...00, a midscale voltage result- The excitation voltage to the bridge must be switched on
ing in a code of 100...000, and a full-scale input voltage resulting alternate cycles. Transistor T1 to Transistor T4 in Figure 50
in a code of 111...111. The output code for any analog input perform the switching of the excitation voltage. These transis-
voltage can be represented as tors can be discrete matched bipolar or MOS transistors, or a
dedicated bridge driver chip, such as the MIC4427 available
Code = (2N × AIN × Gain)/VREF
from Micrel Components, can be used to perform the task.
When the ADC is configured for bipolar operation, the output
Since the analog input voltage and the reference voltage are
code is offset binary with a negative full-scale voltage resulting
reversed on alternate cycles, the AD7195 must be synchronized
in a code of 000...000, a zero differential input voltage resulting
with this reversing of the excitation voltage. To allow the
in a code of 100...000, and a positive full-scale input voltage
AD7195 to synchronize itself with this switching, it provides
resulting in a code of 111...111. The output code for any analog
the logic control signals for the switching of the excitation
input voltage can be represented as
voltage. These signals are the nonoverlapping CMOS outputs
Code = 2N – 1 × [(AIN × Gain/VREF) + 1] ACX1/ACX1 and ACX2/ACX2.
where: One of the problems encountered with ac excitation is the
N = 24. settling time associated with the analog input signals after
AIN is the analog input voltage. the excitation voltage is switched. This is particularly true in
Gain is the PGA setting (1 to 128). applications where there are long lead lengths from the bridge
BURNOUT CURRENTS to the AD7195. It means that the converter could encounter
The AD7195 contains two 500 nA constant current generators, errors because it is processing signals that are not fully settled.
one sourcing current from AVDD to AIN(+) and one sinking The AD7195 includes a delay between the switching of the ac
current from AIN(−) to AGND, where AIN(+) is the positive excitation signals and the processing of data at the analog
analog input terminal and AIN(−) is the negative analog input inputs. The delay equals 100 μs when FS[9:0] equals 1 and
terminal in differential mode and AINCOM in pseudo differ- equals 200 μs for all other output data rates.
ential mode. The currents are switched to the selected analog The AD7195 also scales the ac excitation switching frequency
input pair. Both currents are either on or off, depending on the in accordance with the output data rate. This avoids situations
burnout current enable (BURN) bit in the configuration where the bridge is switched at an unnecessarily faster rate than
register. These currents can be used to verify that an external the system requires.
transducer remains operational before attempting to take The fact that the AD7195 can handle reference voltages, which
measurements on that channel. After the burnout currents are are the same as the excitation voltages, is particularly useful
Rev. A | Page 27 of 44
AD7195 Data Sheet
in ac excitation where resistor divider arrangements on the When several channels are enabled, the ADC must allow the
reference input add to the settling time associated with the complete settling time to generate a valid conversion each time
switching. that the channel is changed. The AD7195 takes care of this:
When the ACX bit in the configuration register is set to 0, when a channel is selected, the modulator and filter are reset,
the digital outputs ACX1 and ACX2 are high, while outputs and the RDY pin is taken high. The AD7195 then allows the
ACX2 and ACX1 are low. Therefore, the bridge is dc excited complete settling time to generate the first conversion. RDY
with the T2 and T4 transistors turned on and the T1 and T3 goes low only when a valid conversion is available. The AD7195
transistors turned off. When the AD7195 is in power-down then selects the next enabled channel and converts on that
mode, outputs ACX1 and ACX2 are low and outputs ACX1 channel. The user can then read the data register while the
ADC is performing the conversion on the next channel.
and ACX2 are high so that the excitation voltage is discon-
nected from the bridge. The time required to read a valid conversion from all enabled
channels is equal to
CHANNEL SEQUENCER
tSETTLE × number of enabled channels
The AD7195 includes a channel sequencer, which simplifies
communications with the device in multichannel applications. For example, if the sinc4 filter is selected, chop is disabled, and
The sequencer also optimizes the channel throughput of the zero latency is disabled, the settling time for each channel is
device because the sequencer switches channels at the optimum equal to
rate rather than waiting for instructions via the SPI interface. tSETTLE = 4/fADC
Bit CH0 to Bit CH7 in the configuration register are used to where fADC is the output data rate when continuously converting
enable the required channels. In continuous conversion mode, on a single channel. The time required to sample N channels is
the ADC selects each of the enabled channels in sequence and
4/(fADC× N)
performs a conversion on the channel. The RDY pin goes low
when a valid conversion is available on each channel. When RDY

several channels are enabled, the contents of the status register CONVERSIONS
should be attached to the 24-bit word so that the user can CHANNEL A CHANNEL B CHANNEL C

08771-028
identify the channel that corresponds to each conversion. To 1/fADC

attach the status register value to the conversion, Bit DAT_STA Figure 20. Channel Sequencer
in the mode register should be set to 1.

Digital Interface The DOUT/RDY pin functions as a data ready signal also; the
line goes low when a new data-word is available in the output
As indicated in the On-Chip Registers section, the program- register. It is reset high when a read operation from the data
mable functions of the AD7195 are controlled using a set of register is complete. It also goes high prior to the updating of the
on-chip registers. Data is written to these registers via the serial data register to indicate when not to read from the device to
interface of the part. Read access to the on-chip registers is also ensure that a data read is not attempted while the register is being
provided by this interface. All communication with the part must updated. CS is used to select a device. It can be used to decode the
start with a write to the communications register. After power-on AD7195 in systems where several components are connected to
or reset, the device expects a write to its communications register. the serial bus.
The data written to this register determines whether the next oper- Figure 3 and Figure 4 show timing diagrams for interfacing to the
ation is a read operation or a write operation and determines to AD7195, with CS being used to decode the part. Figure 3 shows
which register this read or write operation occurs. Therefore, the timing for a read operation from the output shift register of
write access to any of the other registers on the part begins with the AD7195, and Figure 4 shows the timing for a write operation
a write operation to the communications register, followed by a to the input shift register.
write to the selected register. A read operation from any other
It is possible to read the same word from the data register several
register (except when continuous read mode is selected) starts
times even though the DOUT/RDY line returns high after the
with a write to the communications register, followed by a read
first read operation. However, care must be taken to ensure that
operation from the selected register.
the read operations are completed before the next output update
The serial interface of the AD7195 consists of four signals: CS, occurs. In continuous read mode, the data register can be read
DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer only once.
data into the on-chip registers and DOUT/RDY is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT/RDY) occur with respect to the SCLK signal.

Rev. A | Page 28 of 44
Data Sheet AD7195
The serial interface can operate in 3-wire mode by tying CS low. Single Conversion Mode
In this case, the SCLK, DIN, and DOUT/RDY lines are used to In single conversion mode, the AD7195 is placed in power-
communicate with the AD7195. The end of the conversion can down mode after conversions. When a single conversion is
be monitored using the RDY bit or pin. This scheme is suitable initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,
for interfacing to microcontrollers. If CS is required as a decoding in the mode register, the AD7195 powers up, performs a single
signal, it can be generated from a port pin. For microcontroller conversion, and then returns to power-down mode. The on-
interfaces, it is recommended that SCLK idle high between data chip oscillator requires 1 ms, approximately, to power up.
transfers. DOUT/RDY goes low to indicate the completion of a conver-
The AD7195 can be operated with CS used as a frame synchro- sion. When the data-word has been read from the data register,
nization signal. This scheme is useful for DSP interfaces. In this DOUT/RDY goes high. If CS is low, DOUT/RDY remains high
case, the first bit (MSB) is effectively clocked out by CS because until another conversion is initiated and completed. The data
CS normally occurs after the falling edge of SCLK in DSPs. The register can be read several times, if required, even when
SCLK can continue to run between data transfers, provided the DOUT/RDY has gone high.
timing numbers are obeyed. If several channels are enabled, the ADC sequences through the
The serial interface can be reset by writing a series of 1s to the enabled channels and performs a conversion on each channel.
DIN input. If a Logic 1 is written to the AD7195 DIN line for When a conversion is started, DOUT/RDY goes high and
at least 40 serial clock cycles, the serial interface is reset. This remains high until a valid conversion is available. As soon as
ensures that the interface can be reset to a known state if the the conversion is available, DOUT/RDY goes low. The ADC
interface gets lost due to a software error or some glitch in the then selects the next channel and begins a conversion. The user
system. Reset returns the interface to the state in which it expects can read the present conversion while the next conversion is
a write to the communications register. This operation resets the being performed. As soon as the next conversion is complete,
contents of all registers to their power-on values. Following a the data register is updated; therefore, the user has a limited
reset, the user should allow a period of 500 µs before addressing period in which to read the conversion. When the ADC has
the serial interface. performed a single conversion on each of the selected channels,
The AD7195 can be configured to continuously convert or to it returns to power-down mode.
perform a single conversion (see Figure 21 through Figure 23). If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.

CS

0x08 0x280060 0x58

DIN

DATA
DOUT/RDY
08771-029

SCLK

Figure 21. Single Conversion

Rev. A | Page 29 of 44
AD7195 Data Sheet
Continuous Conversion Mode When several channels are enabled, the ADC continuously
Continuous conversion is the default power-up mode. The loops through the enabled channels, performing one conversion
AD7195 converts continuously, and the RDY bit in the status on each channel per loop. The data register is updated as soon
register goes low each time a conversion is complete. If CS is as each conversion is available. The DOUT/RDY pin pulses low
each time a conversion is available. The user can then read the
low, the DOUT/RDY line also goes low when a conversion
conversion while the ADC converts on the next enabled channel.
is completed. To read a conversion, the user writes to the
communications register, indicating that the next operation is If the DAT_STA bit in the mode register is set to 1, the contents
a read of the data register. When the data-word has been read of the status register are output along with the conversion each
from the data register, DOUT/RDY goes high. The user can time that the data read is performed. The status register
read this register additional times, if required. However, the indicates the channel to which the conversion corresponds.
user must ensure that the data register is not being accessed at
the completion of the next conversion or else the new conversion
word is lost.

CS

0x58 0x58
DIN

DATA DATA
DOUT/RDY

08771-030
SCLK

Figure 22. Continuous Conversion

Rev. A | Page 30 of 44
Data Sheet AD7195
Continuous Read conversion is complete, and the new conversion is placed in
Rather than write to the communications register each time the output serial register.
a conversion is complete to access the data, the AD7195 can To exit the continuous read mode, Instruction 01011000 must
be configured so that the conversions are placed on the be written to the communications register while the RDY pin
DOUT/RDY line automatically. By writing 01011100 to is low. While in continuous read mode, the ADC monitors
the communications register, the user need only apply the activity on the DIN line so that it can receive the instruction
appropriate number of SCLK cycles to the ADC, and the to exit the continuous read mode. Additionally, a reset occurs
conversion word is automatically placed on the DOUT/RDY if 40 consecutive 1s are seen on DIN. Therefore, DIN should
line when a conversion is complete. The ADC should be be held low in continuous read mode until an instruction is to
configured for continuous conversion mode. be written to the device.
When DOUT/RDY goes low to indicate the end of a conversion, When several channels are enabled, the ADC continuously
sufficient SCLK cycles must be applied to the ADC; the data steps through the enabled channels and performs one con-
conversion is then placed on the DOUT/RDY line. When the version on each channel each time that it is selected. DOUT/
conversion is read, DOUT/RDY returns high until the next RDY pulses low when a conversion is available. When the user
conversion is available. In this mode, the data can be read only applies sufficient SCLK pulses, the data is automatically placed
once. Also, the user must ensure that the data-word is read on the DOUT/RDY pin. If the DAT_STA bit in the mode
before the next conversion is complete. If the user has not read register is set to 1, the contents of the status register are output
the conversion before the completion of the next conversion, along with the conversion. The status register indicates the
or if insufficient serial clocks are applied to the AD7195 to channel to which the conversion corresponds.
read the word, the serial output register is reset when the next

CS

0x5C
DIN

DATA DATA DATA

DOUT/RDY

08771-031
SCLK

Figure 23. Continuous Read

Rev. A | Page 31 of 44
AD7195 Data Sheet
RESET the AD7195. The clock source is selected using the CLK1 and
The circuitry and serial interface of the AD7195 can be reset CLK0 bits in the mode register. When an external crystal is
by writing consecutive 1s to the device; 40 consecutive 1s are used, it must be connected across the MCLK1 and MCLK2
required to perform the reset. This resets the logic, the digital pins. The crystal manufacturer recommends the load capacitances
filter, and the analog modulator, whereas all on-chip registers required for the crystal. The MCLK1 and MCLK2 pins of the
are reset to their default values. A reset is automatically AD7195 have a capacitance of 15 pF, typically. If an external
performed on power-up. When a reset is initiated, the user clock source is used, the clock source must be connected to the
MCLK2 pin, and the MCLK1 pin can be left floating.
must allow a period of 500 µs before accessing any of the
on-chip registers. A reset is useful if the serial interface loses The internal clock can also be made available at the MCLK2
synchronization due to noise on the SCLK line. pin. This is useful when several ADCs are used in an application
and the devices must be synchronized. The internal clock from
SYSTEM SYNCHRONIZATION
one device can be used as the clock source for all ADCs in the
The SYNC input allows the user to reset the modulator and the system. Using a common clock, the devices can be synchro-
digital filter without affecting any of the setup conditions on nized by applying a common reset to all devices, or the SYNC
the part. This allows the user to start gathering samples of the pin can be pulsed.
analog input from a known point in time, that is, the rising edge
of SYNC. SYNC needs to be taken low for at least four master
ENABLE PARITY
clock cycles to implement the synchronization function. The AD7195 also has an on-chip parity check function that
detects 1-bit errors in the serial communications between
If multiple AD7195 devices operate from a common master
the ADC and the microprocessor. When the ENPAR bit in
clock, they can be synchronized so that their data registers are
the mode register is set to 1, parity is enabled. The contents of
updated simultaneously. A falling edge on the SYNC pin resets
the status register must be transmitted along with each 24-bit
the digital filter and the analog modulator and places the AD7195
conversion when the parity function is enabled. To append the
into a consistent, known state. While the SYNC pin is low, the contents of the status register to each conversion read, the
AD7195 is maintained in this state. On the SYNC rising edge, DAT_STA bit in the mode register should be set to 1.
the modulator and filter are taken out of this reset state and, on
For each conversion read, the parity bit in the status register is
the next clock edge, the part starts to gather input samples again.
programmed so that the overall number of 1s transmitted in the
In a system using multiple AD7195 devices, a common signal to
24-bit data-word is even. Therefore, for example, if the 24-bit
their SYNC pins synchronizes their operation. This is normally
conversion contains eleven 1s (binary format), the parity bit is
done after each AD7195 has performed its own calibration or
set to 1 so that the total number of 1s in the serial transmission
has calibration coefficients loaded into its calibration registers.
is even. If the microprocessor receives an odd number of 1s, it
The conversions from the AD7195s are then synchronized.
knows that the data received has been corrupted.
The part is taken out of reset on the master clock falling edge
The parity function only detects 1-bit errors. For example, two
following the SYNC low to high transition. Therefore, when
bits of corrupt data can result in the microprocessor receiving an
multiple devices are being synchronized, the SYNC pin should even number of 1s. Therefore, an error condition is not detected.
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the TEMPERATURE SENSOR
SYNC pin is not taken high in sufficient time, a difference of Embedded in the AD7195 is a temperature sensor. This is
one master clock cycle may result between the devices; that is, selected using the CH2 bit in the configuration register. When
the instant at which conversions are available differs from part the CH2 bit is set to 1, the temperature sensor is enabled. When
to part by a maximum of one master clock cycle. the temperature sensor is selected and bipolar mode is selected,
the device should return a code of 0x800000 when the temper-
The SYNC pin can also be used as a start conversion command.
ature is 0 K. A one-point calibration is needed to get the optimum
In this mode, the rising edge of SYNC starts conversion, and the
performance from the sensor. Therefore, a conversion at 25°C
falling edge of RDY indicates when the conversion is complete.
should be recorded and the sensitivity calculated. The sensitivity
The settling time of the filter has to be allowed for each data is approximately 2815 codes/°C. The equation for the temperature
register update. For example, if the ADC is configured to use sensor is
the sinc4 filter, zero latency is disabled, and chop is disabled, the
settling time equals 4/fADC where fADC is the output data rate Temp (K) = (Conversion − 0x800000)/2815 K
when continuously converting on a single channel. Temp (°C) = Temp (K) − 273
CLOCK Following the one point calibration, the internal temperature
The AD7195 includes an internal 4.92 MHz clock on-chip. This sensor has an accuracy of ±2 °C, typically.
internal clock has a tolerance of ±4%. Either the internal clock
or an external crystal/clock can be used as the clock source to
Rev. A | Page 32 of 44
Data Sheet AD7195
BRIDGE POWER-DOWN SWITCH To perform an internal full-scale calibration, a full-scale input
In bridge applications, such as strain gauges and load cells, the voltage is automatically connected to the selected analog input
bridge itself consumes the majority of the current in the system. for this calibration. For a gain of 1, the time required for an
For example, a 350 Ω load cell requires 15 mA of current when internal full-scale calibration is equal to tSETTLE. For higher gains,
excited with a 5 V supply. To minimize the current consumption the internal full-scale calibration requires a time of 2 × tSETTLE.
of the system, the bridge can be disconnected (when it is not A full-scale calibration is recommended each time the gain of a
being used) using the bridge power-down switch. Figure 50 channel is changed to minimize the full-scale error.
shows how the bridge power-down switch is used. The switch A system full-scale calibration requires a time of tSETTLE. With
can withstand 30 mA of continuous current, and it has an on chop disabled, the zero-scale calibration (internal or system
resistance of 10 Ω maximum. zero-scale) should be performed before the system full-scale
calibration is initiated.
CALIBRATION
An internal zero-scale calibration, system zero-scale calibration
The AD7195 provides four calibration modes that can be pro-
and system full-scale calibration can be performed at any output
grammed via the mode bits in the mode register. These modes
data rate. An internal full-scale calibration can be performed at
are internal zero-scale calibration, internal full-scale calibration,
any output data rate for which the filter word FS[9:0] is divisible
system zero-scale calibration, and system full-scale calibration.
by 16, FS[9:0] being the decimal equivalent of the 10-bit word
A calibration can be performed at any time by setting the MD2
written to Bit FS9 to Bit FS0 in the mode register. Therefore,
to MD0 bits in the mode register appropriately. A calibration
internal full-scale calibrations can be performed at output data
should be performed when the gain is changed. After each
rates such as 10 Hz or 50 Hz when chop is disabled. Using these
conversion, the ADC conversion result is scaled using the ADC
lower output data rates results in better calibration accuracy.
calibration registers before being written to the data register.
The offset calibration coefficient is subtracted from the result The offset error is, typically, 100 µV/gain. If the gain is changed,
prior to multiplication by the full-scale coefficient. it is advisable to perform a calibration. A zero-scale calibration
(an internal zero-scale calibration or system zero-scale
To start a calibration, write the relevant value to the MD2 to
calibration) reduces the offset error to the order of the noise.
MD0 bits. The DOUT/RDY pin and the RDY bit in the status
register go high when the calibration is initiated. When the The gain error of the AD7195 is factory calibrated at a gain of 1
calibration is complete, the contents of the corresponding with a 5 V power supply at ambient temperature. Following this
calibration registers are updated, the RDY bit in the status calibration, the gain error is 0.001%, typically, at 5 V. Table 28
register is reset, the DOUT/ RDY pin returns low (if CS is shows the typical uncalibrated gain error for the different gain
low), and the AD7195 reverts to idle mode. settings. An internal full-scale calibration reduces the gain error
to 0.001%, typically, when the gain is equal to 1. For higher
During an internal zero-scale or full-scale calibration, the res- gains, the gain error post internal full-scale calibration is
pective zero input and full-scale input are automatically connected 0.0075%, typically. A system full-sale calibration reduces the
internally to the ADC input pins. A system calibration, however, gain error to the order of the noise.
expects the system zero-scale and system full-scale voltages to
be applied to the ADC pins before initiating the calibration Table 28. Typical Precalibration Gain Error vs. Gain
mode. In this way, errors external to the ADC are removed. Gain Precalibration Gain Error (%)
From an operational point of view, treat a calibration like 8 −0.11
another ADC conversion. A zero-scale calibration, if required, 16 −0.20
must always be performed before a full-scale calibration. Set the 32 −0.23
system software to monitor the RDY bit in the status register or 64 −0.29
the DOUT/RDY pin to determine the end of calibration via a 128 −0.39
polling sequence or an interrupt-driven routine. The AD7195 gives the user access to the on-chip calibration
With chop disabled, both an internal zero-scale calibration and a registers, allowing the microprocessor to read the calibration
system zero-scale calibration require a time equal to the settling coefficients of the device and also to write its own calibration
time, tSETTLE, (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter). coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
With chop enabled, an internal zero-scale calibration is not must be placed in power-down or idle mode when writing to
needed because the ADC itself minimizes the offset continuously. the registers. The values in the calibration registers are 24-bits
However, if an internal zero-scale calibration is performed, the wide. The span and offset of the part can also be manipulated
settling time, tSETTLE, (2/fADC) is required to perform the calibra- using the registers.
tion. Similarly, a system zero-scale calibration requires a time of
tSETTLE to complete.

Rev. A | Page 33 of 44
AD7195 Data Sheet
DIGITAL FILTER When conversions are performed on a single channel and a
The AD7195 offers a lot of flexibility in the digital filter. The step change occurs, the ADC does not detect the change in
device has four filter options. The device can be operated analog input. Therefore, it continues to output conversions
with a sinc3 or sinc4 filter, chop can be enabled or disabled, and at the programmed output data rate. However, it is at least four
zero latency can be enabled. The option selected affects the conversions later before the output data accurately reflect the
output data rate, settling time, and 50 Hz/60 Hz rejection. The analog input. If the step change occurs while the ADC is
following sections describe each filter type, indicating the processing a conversion, then the ADC takes five conversions
available output data rates for each filter option. The filter res- after the step change to generate a fully settled result.
ANALOG
ponse along with the settling time and 50 Hz/60 Hz rejection INPUT
is also discussed. FULLY
SETTLED
4 ADC
SINC FILTER (CHOP DISABLED) OUTPUT

When the AD7195 is powered up, the sinc4 filter is selected

08771-039
by default and chop is disabled. This filter gives excellent noise 1/fADC
performance over the complete range of output data rates. It Figure 26. Asynchronous Step Change in Analog Input
also gives the best 50 Hz/60 Hz rejection, but it has a long
settling time. The 3 dB frequency for the sinc4 filter is equal to
ADC f3dB = 0.23 × fADC
Table 29 gives some examples of the relationship between the
values in Bits FS[9:0] and the corresponding output data rate
CHOP MODULATOR SINC3/SINC4 and settling time.

Table 29. Examples of Output Data Rates and the

08771-033

Corresponding Settling Time

Figure 24. Sinc4 Filter (Chop Disabled) FS[9:0] Output Data Rate (Hz) Settling Time (ms)
Sinc4 Output Data Rate/Settling Time 480 10 400
96 50 80
The output data rate (the rate at which conversions are available
80 60 66.6
on a single channel when the ADC is continuously converting)
is equal to Sinc4 Zero Latency
fADC = fCLK/(1024 × FS[9:0]) Zero latency is enabled by setting the single bit (Bit 11) in the
where: mode register to 1. With zero latency, the complete settling time
fADC is the output data rate. is allowed for each conversion. Therefore, the conversion time
fCLK is the master clock (4.92 MHz nominal). when converting on a single channel or when converting on
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the several channels is constant. The user does not need to consider
mode register. the effects of channel changes on the output data rate.

The output data rate can be programmed from 4.7 Hz to The output data rate equals
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. fADC = 1/tSETTLE = fCLK/(4 × 1024 × FS[9:0])
4
The settling time for the sinc filter is equal to where:
tSETTLE = 4/fADC fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
When a channel change occurs, the modulator and filter are FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
reset. The settling time is allowed to generate the first conver- mode register.
sion after the channel change. Subsequent conversions on this
channel occur at 1/fADC.
CHANNEL CHANNEL A CHANNEL B

CONVERSIONS CH A CH A CH A CH B CH B CH B
08771-038

1/fADC

Figure 25. Sinc4 Channel Change

Rev. A | Page 34 of 44
Data Sheet AD7195
When the analog input is constant or a channel change occurs, Figure 29 shows the frequency response when FS[9:0] is
valid conversions are available at a constant output data rate. programmed to 80 and the master clock is equal to 4.92 MHz.
When conversions are being performed on a single channel and The output data rate is 60 Hz when zero latency is disabled and
a step change occurs on the analog input, the ADC continues to 15 Hz when zero latency is enabled. The sinc4 filter provides
output fully settled conversions if the step change is synchronized 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable
with the conversion process. If the step change is asynchronous, master clock.
one conversion is output from the ADC, which is not completely 0

settled (see Figure 27). –10

ANALOG –20
INPUT
–30
FULLY
SETTLED –40

FILTER GAIN (dB)

ADC
OUTPUT –50
–60

08771-040
–70
1/fADC
–80
Figure 27. Sinc4 Zero Latency Operation –90

Table 30 shows examples of output data rate and the corres- –100

ponding FS values. –110

–120

08771-042
0 30 60 90 120 150
Table 30. Examples of Output Data Rates and the
FREQUENCY (Hz)
Corresponding Settling Time (Zero Latency)
Figure 29. Sinc4 Filter Response (FS[9:0] = 80)
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
480 2.5 400 Simultaneous 50 Hz and 60 Hz rejection is obtained when
96 12.5 80 FS[9:0] is programmed to 480 and the master clock equals
80 15 66.6 4.92 MHz. The output data rate is 10 Hz when zero latency is
disabled and 2.5 Hz when zero latency is enabled. The sinc4
Sinc4 50 Hz/60 Hz Rejection filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of
Figure 28 shows the frequency response of the sinc4 filter when 120 dB minimum, assuming a stable master clock.
FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero 0

latency disabled, the output data rate is equal to 50 Hz. With –10

zero latency enabled, the output data rate is 12.5 Hz. The sinc4 –20

filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB –30

minimum, assuming a stable master clock. –40

FILTER GAIN (dB)

0 –50

–10 –60

–20 –70

–30 –80

–40 –90
FILTER GAIN (dB)

–50 –100

–60 –110

–70 –120 08771-043

0 30 60 90 120 150
–80
FREQUENCY (Hz)
–90
Figure 30. Sinc4 Filter Response (FS[9:0] = 480)
–100
–110 Simultaneous 50 Hz/60 Hz rejection can also be achieved using
–120 the REJ60 bit in the mode register. When FS[9:0] is set to 96
08771-041

0 25 50 75 100 125 150

and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.
FREQUENCY (Hz)

Figure 28. Sinc4 Filter Response (FS[9:0] = 96)

Rev. A | Page 35 of 44
AD7195 Data Sheet
The output data rate is 50 Hz when zero latency is disabled and The 3 dB frequency is equal to
12.5 Hz when zero latency is enabled. Figure 31 shows the f3dB = 0.272 × fADC
frequency response of the sinc4 filter. The filter provides 50 Hz
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming Table 31 gives some examples of FS settings and the corres-
a stable 4.92 MHz master clock. ponding output data rates and settling times.
0
Table 31. Examples of Output Data Rates and the
–10
Corresponding Settling Time
–20
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
–30
480 10 300
–40
FILTER GAIN (dB)

96 50 60
–50
80 60 50
–60
–70 When a channel change occurs, the modulator and filter reset.
–80 The complete settling time is allowed to generate the first
–90 conversion after the channel change (see Figure 33). Subsequent
–100 conversions on this channel are available at 1/fADC.
–110
CHANNEL A CHANNEL B
–120 CHANNEL
08771-044

0 25 50 75 100 125 150

FREQUENCY (Hz) CONVERSIONS CH A CH A CH A CH B CH B CH B CH B

Figure 31. Sinc4 Filter Response (FS[9:0] = 96, REJ60 = 1)

08771-045
1/fADC
SINC3 FILTER (CHOP DISABLED)
Figure 33. Sinc3 Channel Change
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the SINC3 bit in the mode register. The sinc3 When conversions are performed on a single channel and a step
filter is selected when the SINC3 bit is set to 1. change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the program-
This filter has good noise performance when operating with med output data rate. However, it is at least three conversions later
output data rates up to 1 kHz. It has moderate settling time and before the output data accurately reflects the analog input. If the
moderate 50 Hz/60 Hz (±1 Hz) rejection. step change occurs while the ADC is processing a conversion, the
ADC ADC takes four conversions after the step change to generate a fully
settled result.
ANALOG
INPUT
CHOP MODULATOR SINC3/SINC4 FULLY
SETTLED
ADC
08771-034

OUTPUT

08771-046
Figure 32. Sinc3 Filter (Chop Disabled)
1/fADC
Sinc3 Output Data Rate and Settling Time Figure 34. Asynchronous Step Change in Analog Input
The output data rate (the rate at which conversions are available 3
Sinc Zero Latency
on a single channel when the ADC is continuously converting)
is equal to Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
fADC = fCLK/(1024 × FS[9:0])
is allowed for each conversion. Therefore, the conversion time
where: when converting on a single channel or when converting on
fADC is the output data rate. several channels is constant. The user does not need to consider
fCLK is the master clock (4.92 MHz nominal). the effects of channel changes on the output data rate.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
tSETTLE = 3/fADC

Rev. A | Page 36 of 44
Data Sheet AD7195
The output data rate equals Sinc3 50 Hz/60 Hz Rejection
fADC = 1/tSETTLE = fCLK/(3 × 1024 × FS[9:0]) Figure 36 show the frequency response of the sinc3 filter when
where: FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
fADC is the output data rate. output data rate is equal to 50 Hz when zero latency is disabled
fCLK is the master clock (4.92 MHz nominal). and 16.7 Hz when zero latency is enabled. The sinc3 filter gives
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
mode register. 0

–10
When the analog input is constant or a channel change occurs,
–20
valid conversions are available at a constant output data rate.
–30
When conversions are being performed on a single channel and –40

FILTER GAIN (dB)

a step change occurs on the analog input, the ADC continues to –50
output fully settled conversions if the step change is synchronized –60
with the conversion process. If the step change is asynchronous, –70
one conversion is output from the ADC that is not completely –80
settled (see Figure 35). –90

ANALOG –100
INPUT
FULLY –110
SETTLED –120
ADC

08771-048
0 25 50 75 100 125 150
OUTPUT
FREQUENCY (Hz)

Figure 36. Sinc3 Filter Response (FS[9:0] = 96)

08771-047

1/fADC When FS[9:0] is set to 80 and the master clock equals

Figure 35. Sinc3 Zero Latency Operation 4.92 MHz, 60 Hz rejection is achieved (see Figure 37). The
output data rate is equal to 60 Hz when zero latency is disabled
Table 32 provides examples of output data rates and the corres-
and 20 Hz when zero latency is enabled. The sinc3 filter has
ponding FS values.
rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable
Table 32. Examples of Output Data Rates and the master clock.
Corresponding Settling Time (Zero Latency) 0

FS[9:0] Output Data Rate (Hz) Settling Time (ms) –10

–20
480 3.3 300
–30
96 16.7 60
FILTER GAIN (dB)

–40
80 20 50
–50
–60
–70
–80
–90
–100
–110
–120
08771-049

0 30 60 90 120 150
FREQUENCY (Hz)

Figure 37. Sinc3 Filter Response (FS[9:0] = 80)

Rev. A | Page 37 of 44
AD7195 Data Sheet
Simultaneous 50 Hz and 60 Hz rejection is obtained when CHOP ENABLED (SINC4 FILTER)
FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in With chop enabled, the ADC offset and offset drift are minimized.
Figure 38. The output data rate is 10 Hz when zero latency is The analog input pins are continuously swapped. With the
disabled and 3.3 Hz when zero latency is enabled. The sinc3 analog input pins connected in one direction, the settling time
filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and of the sinc filter is allowed and a conversion is recorded. The
60 Hz ± 1 Hz. analog input pins are then inverted, and another settled conver-
sion is obtained. Subsequent conversions are averaged to
0
minimize the offset. This continuous swapping of the analog
–10
input pins and the averaging of subsequent conversions means
–20
that the offset drift is also minimized. With chop enabled, the
–30
resolution increases by 0.5 bits.
–40
FILTER GAIN (dB)

ADC
–50
–60
–70
–80 CHOP MODULATOR SINC3/SINC4

–90

08771-035
–100
–110
Figure 40. Chop Enabled
–120
08771-050

0 30 60 90 120 150
Output Data Rate and Settling Time (Sinc4 Chop
FREQUENCY (Hz)
Enabled)
Figure 38. Sinc3 Filter Response (FS[9:0] = 480)
For the sinc4 filter, the output data rate is equal to
Simultaneous 50 Hz/60 Hz rejection is also achieved using the
fADC = fCLK/(4 × 1024 × FS[9:0])
REJ60 bit in the mode register. When FS[9:0] is programmed to
96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz where:
and 60 Hz for a stable 4.92 MHz master clock. Figure 39 shows fADC is the output data rate.
the frequency response of the sinc3 filter with this configuration. fCLK is the master clock (4.92 MHz nominal).
Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
is in excess of 67 dB minimum. mode register.
0 The value of FS[9:0] can be varied from 1 to 1023. This results
–10 in an output data rate of 1.17 Hz to 1200 Hz. The settling time is
–20 equal to
–30
–40
tSETTLE = 2/fADC
FILTER GAIN (dB)

–50 Table 33 gives some examples of FS[9:0] values and the corres-
–60 ponding output data rates and settling times.
–70
–80 Table 33. Examples of Output Data Rates and the
–90 Corresponding Settling Time
–100 FS[9:0] Output Data Rate (Hz) Settling Time (ms)
–110 96 12.5 160
–120 80 15 133
08771-051

0 25 50 75 100 125 150

FREQUENCY (Hz)

Figure 39. Sinc3 Filter Response (FS[9:0] = 96, REJ60 = 1)

Rev. A | Page 38 of 44
Data Sheet AD7195
0
When a channel change occurs, the modulator and filter reset. –10
The complete settling time is required to generate the first –20
conversion after the channel change. Subsequent conversions –30
on this channel occur at 1/fADC. –40

FILTER GAIN (dB)

CHANNEL A CHANNEL B –50
CHANNEL
–60
CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B –70
–80

08771-052
1/fADC –90
4
Figure 41. Channel Change (Sinc Chop Enabled) –100

–110
When conversions are performed on a single channel and a –120

08771-054
step change occurs, the ADC does not detect the change in 0 25 50 75 100 125 150
FREQUENCY (Hz)
analog input; therefore, it continues to output conversions at
the programmed output data rate. However, it is at least two Figure 43. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)
conversions later before the output data accurately reflects the The 50 Hz/60 Hz rejection can be improved by setting the
analog input. If the step change occurs while the ADC is REJ60 bit in the mode register to 1. With FS[9:0] set to 96
processing a conversion, the ADC takes three conversions after and REJ60 set to 1, the filter response shown Figure 44
the step change to generate a fully settled result. is achieved. The output data rate is unchanged but the 50 Hz/
ANALOG 60 Hz (± 1 Hz) rejection is increased to 83 dB typically.
INPUT
0
FULLY
SETTLED –10
ADC
OUTPUT –20
–30
08771-053

–40
FILTER GAIN (dB)

1/fADC

4
–50
Figure 42. Asynchronous Step Change in Analog Input (Sinc Chop Enabled)
–60
The cutoff frequency f3dB is equal to –70

f3dB = 0.24 × fADC –80

–90
50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) –100
When FS[9:0] is set to 96 and chopping is enabled, the output –110
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The –120

08771-055
0 25 50 75 100 125 150
filter response shown in Figure 43 is obtained. The chopping
FREQUENCY (Hz)
introduces notches at odd integer multiples of fADC/2. The
Figure 44. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
notches due to the sinc filter in addition to the notches intro-
duced by the chopping mean that simultaneous 50 Hz and
60 Hz rejection is achieved for an output data rate of 12.5 Hz.
The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB,
assuming a stable master clock.

Rev. A | Page 39 of 44
AD7195 Data Sheet
CHOP ENABLED (SINC3 FILTER) If conversions are performed on a single channel and a step
With chop enabled, the ADC offset and offset drift are change occurs, the ADC does not detect the change in analog
minimized. The analog input pins are continuously swapped. input; therefore, it continues to output conversions at the
With the analog input pins connected in one direction, the programmed output data rate. However, it is at least two
settling time of the sinc filter is allowed and a conversion is conversions later before the output data accurately reflects
recorded. The analog input pins invert and another settled the analog input. If the step change occurs while the ADC is
conversion is obtained. Subsequent conversions are averaged processing a conversion, then the ADC takes three conversions
to minimize the offset. This continuous swapping of the analog after the step change to generate a fully settled result.
ANALOG
input pins and the averaging of subsequent conversions means INPUT
that the offset drift is also minimized. With chop enabled, the FULLY
SETTLED
resolution increases by 0.5 bits. Using the sinc3 filter with chop ADC
OUTPUT
enabled is suitable for output data rates up to 320 Hz.

08771-057
ADC
1/fADC

Figure 47. Asynchronous Step Change in Analog Input (Sinc3 Chop Enabled)

CHOP MODULATOR SINC3/SINC4 The cutoff frequency f3dB is equal to

f3dB = 0.24 × fADC
08771-036

50 Hz/60 Hz Rejection (Sinc3 Chop Enabled)

3
Figure 45. Chop Enabled (Sinc Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the filter
Output Data Rate and Settling Time (Sinc3 Chop response shown in Figure 48 is obtained. The output data rate
Enabled) is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping
For the sinc3 filter, the output data rate is equal to introduces notches at odd integer multiples of fADC/2. The
notches due to the sinc filter in addtion to the notches intro-
fADC = fCLK/(3 × 1024 × FS[9:0])
duced by the chopping means that simultaneous 50 Hz and
where: 60 Hz rejection is achieved for an output data rate of 16.7 Hz.
fADC is the output data rate. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 53 dB,
fCLK is the master clock (4.92 MHz nominal). assuming a stable master clock.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the 0
mode register. –10

The value of FS[9:0] can be varied from 1 to 1023. This results –20
–30
in an output data rate of 1.56 Hz to 1600 Hz. The settling time
–40
FILTER GAIN (dB)

is equal to
–50
tSETTLE = 2/fADC –60
–70
Table 34. Examples of Output Data Rates and the
–80
Corresponding Settling Time (Chop Enabled, Sinc3 Filter)
–90
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
–100
96 16.7 120
–110
80 20 100 –120
08771-058

0 25 50 75 100 125 150

When a channel change occurs, the modulator and filter are
FREQUENCY (Hz)
reset. The complete settling time is required to generate the first
Figure 48. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled)
conversion after the channel change. Subsequent conversions on
this channel occur at 1/fADC.
CHANNEL CHANNEL A CHANNEL B

CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B
08771-056

1/fADC

Figure 46. Channel Change (Sinc3 Chop Enable)

Rev. A | Page 40 of 44
Data Sheet AD7195
The 50 Hz/60 Hz rejection can be improved by setting the SUMMARY OF FILTER OPTIONS
REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and The AD7195 has several filter options. The filter that is chosen
REJ60 set to 1, the filter response shown in Figure 49 is achieved. affects the output data rate, settling time, the rms noise, the stop
The output data rate is unchanged, but the 50 Hz/60 Hz ± 1 Hz band attenuation, and the 50 Hz/60 Hz rejection.
rejection improves to 73 dB typically.
0
Table 35 shows some sample configurations and the corres-
–10
ponding performance in terms of throughput, settling time and
–20 50 Hz/60 Hz rejection.
–30
–40
FILTER GAIN (dB)

–50
–60
–70
–80
–90
–100
–110
–120
08771-059

0 25 50 75 100 125 150

FREQUENCY (Hz)

Figure 49. Sinc3 Filter Response

(FS[9:0] = 96, Chop Enabled, REJ60 = 1)

Table 35. Filter Summary 1

Output Data Settling
Filter FS[9:0] Rate (Hz) Time (ms) Throughput 2 (Hz) REJ60 50 Hz Rejection (dB)
Sinc4, Chop Disabled 3 1 4800 0.83 1200 0 No 50 Hz or 60 Hz rejection
Sinc4, Chop Disabled 5 960 4.17 240 0 No 50 Hz or 60 Hz rejection
Sinc3, Chop Disabled 5 960 3.125 320 0 No 50 Hz or 60 Hz rejection
Sinc4, Chop Disabled 480 10 400 2.5 0 120 dB ( 50 Hz and 60 Hz)
Sinc3, Chop Disabled 480 10 300 3.33 0 100 dB (50 Hz and 60 Hz)
Sinc4, Chop Disabled 96 50 80 12.5 0 120 dB (50 Hz only)
Sinc4, Chop Disabled 96 50 80 12.5 1 82 dB ( 50 Hz and 60 Hz)
Sinc3, Chop Disabled 96 50 60 16.7 0 95 dB (50 Hz only)
Sinc3, Chop Disabled 96 50 60 16.7 1 67 dB ( 50 Hz and 60 Hz)
Sinc4, Chop Disabled 80 60 66.67 15 0 120 dB (60 Hz only)
Sinc3, Chop Disabled 80 60 50 20 0 95 dB (60 Hz only)
Sinc4, Chop Disabled, Zero 96 12.5 80 12.5 0 120 dB (50 Hz only)
Latency
Sinc4, Chop Disabled, Zero 96 12.5 80 12.5 1 82 dB ( 50 Hz and 60 Hz)
Latency
Sinc4, Chop Disabled, Zero 80 15 66.67 15 0 120 dB (60 Hz only)
Latency
Sinc4, Chop Enabled 96 12.5 160 6.25 1 80 dB (50 Hz and 60 Hz)
Sinc3, Chop Enabled 96 16.7 120 8.33 1 67 dB (50 Hz and 60 Hz)
1
These calculations assume a 4.92 MHz stable master clock.
2
Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal.
3
For output dates rates greater than 1 kHz, the sinc4 filter is recommended.

Rev. A | Page 41 of 44
AD7195 Data Sheet
GROUNDING AND LAYOUT situations, it is recommended that the ground pins of the
Because the analog inputs and reference inputs are differential, AD7195 be tied to the AGND plane.
most of the voltages in the analog modulator are common- In any layout, the user must keep in mind the flow of currents
mode voltages. The high common-mode rejection of the part in the system, ensuring that the paths for all currents are as close
removes common-mode noise on these inputs. The analog and as possible to the paths the currents took to reach their destin-
digital supplies to the AD7195 are independent and separately ations. Avoid forcing digital currents to flow through the AGND.
pinned out to minimize coupling between the analog and digi- Avoid running digital lines under the device because this
tal sections of the device. The digital filter provides rejection couples noise onto the die and allow the analog ground plane
of broadband noise on the power supplies, except at integer to run under the AD7195 to prevent noise coupling. The power
multiples of the modulator sampling frequency. supply lines to the AD7195 must use as wide a trace as possible
Connect an R-C filter to each analog input pin to provide to provide low impedance paths and reduce the effects of
rejection at the modulator sampling frequency. The digital filter glitches on the power supply line. Shield fast switching signals
also removes noise from the analog and reference inputs pro- like clocks with digital ground to prevent radiating noise to
vided these noise sources do not saturate the analog modulator. other sections of the board, and never run clock signals near
As a result, the AD7195 is more immune to noise interference the analog inputs. Avoid crossover of digital and analog signals.
than a conventional high resolution converter. However, Run traces on opposite sides of the board at right angles to
because the resolution of the AD7195 is so high and the noise each other. This reduces the effects of feedthrough through
levels from the converter so low, care must be taken with regard the board. A microstrip technique is by far the best but is not
to grounding and layout. always possible with a double-sided board. In this technique,
The printed circuit board (PCB) that houses the ADC must be the component side of the board is dedicated to ground planes,
designed so that the analog and digital sections are separated whereas signals are placed on the solder side.
and confined to certain areas of the board. This facilitates the Good decoupling is important when using high resolution ADCs.
use of ground planes that can be easily separated. A minimum Decouple all analog supplies with 10 μF tantalum in parallel with
etch technique is generally best for ground planes because it 0.1 μF capacitors to AGND. To achieve the best from these
gives the best shielding. decoupling components, place them as close as possible to the
Although the AD7195 has separate pins for analog and digital device, ideally right up against the device. Decouple all logic chips
ground, the AGND and DGND pins are tied together internally with 0.1 μF ceramic capacitors to DGND. In systems in which a
via the substrate. Therefore, the user must not tie these two common supply voltage is used to drive both the AVDD and DVDD
pins to separate ground planes unless the ground planes are of the AD7195, it is recommended that the system AVDD supply
connected together near the AD7195. be used. For this supply, place the recommended analog supply
decoupling capacitors between the AVDD pin of the AD7195 and
In systems where AGND and DGND are connected elsewhere AGND and the recommended digital supply decoupling capa-
in the system, they should not be connected again at the citor between the DVDD pin of the AD7195 and DGND.
AD7195 because this would result in a ground loop. In these

Rev. A | Page 42 of 44
Data Sheet AD7195

APPLICATIONS INFORMATION
The AD7195 provides a low-cost, high resolution analog-to- ACX2 and ACX2. In this phase, the excitation voltage to the
digital function. Because the analog-to-digital function is bridge is reversed while the analog input signal and the
provided by a Σ-∆ architecture, the part is more immune reference voltage are also reversed. The AD7195 averages the
to noisy environments, making it ideal for use in sensor conversions from the two phases so that any offsets and thermal
measurement and industrial and process control applications. affects are cancelled.
WEIGH SCALES AC excitation is enabled by setting Bit ACX in the configuration
Figure 50 shows the AD7195 being used in a weigh scale applica- register to 1. When the ACX bit is set to 0, the bridge is dc
tion which uses ac excitation. The load cell is arranged in a bridge excited. When the AD7195 is in power-down mode, the bridge
network and gives a differential output voltage between its OUT+ is disconnected from the excitation voltage, which minimizes
and OUT– terminals. Assuming a 5 V excitation voltage, the full power consumption of the system. Following a reset, the ac
-scale output range from the transducer is 10 mV when the excitation pins are undefined for a few milliseconds. Thus, pull-
sensitivity is 2 mV/V. The excitation voltage for the bridge can up/pull-down resistors should be used on the pins to prevent
be used to directly provide the reference for the ADC because the excitation voltage being shorted to AGND.
the reference input range includes the supply voltage. For simplicity, external filters are not included in Figure 50.
With ac-excitation, the excitation voltage to the load cell is However, an R-C antialias filter must be included on each
changed on each phase. In Phase 1, the T2 and T4 transistors analog input. This is required because the on-chip digital filter
are turned on using ACX1 and ACX1 while the T1 and T3 does not provide any rejection around the modulator sampling
transistors are turned off. The bridge is forward biased. During frequency or multiples of this frequency.
Phase 2, Transistor T1 and Transistor T3 are turned on using
+5V

T1 T2

REFIN(+) AVDD AGND DVDD DGND REFERENCE

DETECT
IN+ AIN1 AVDD
AIN2
OUT– OUT+ AIN3
AIN4 SERIAL DOUT/RDY
MUX Σ-Δ INTERFACE DIN
IN– AINCOM PGA AND
ADC
CONTROL SCLK
REFIN(–) LOGIC
CS
SYNC
AGND
T3 T4
TEMP
SENSOR
BPDSW AC
AVDD EXCITATION CLOCK
CLOCK CIRCUITRY
AD7195
ACX1 ACX1 ACX2 ACX2
1MΩ
MCLK1 MCLK2
08771-032
1MΩ

Figure 50. Typical Application (Weigh Scale)

Rev. A | Page 43 of 44
AD7195 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.18
INDICATOR PIN 1
25 32 INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24 1

0.50
BSC
EXPOSED 3.75
PAD
3.60 SQ
3.55

17 8
16 9
0.50 0.25 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 TOP VIEW THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

02-22-2017-B
PKG-004570

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.

Figure 51. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7195BCPZ –40°C to +105°C 32-Lead LFCSP CP-32-12
AD7195BCPZ-RL –40°C to +105°C 32-Lead LFCSP CP-32-12
AD7195BCPZ-RL7 –40°C to +105°C 32-Lead LFCSP CP-32-12
EVAL-AD7195EBZ Evaluation Board
1
Z = RoHS Compliant Part.

©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D08771-0-7/17(A)

Rev. A | Page 44 of 44