8-Channel DAS with 16-Bit, 800 kSPS

Bipolar Input, Simultaneous Sampling ADC

Data Sheet AD7606B
FEATURES APPLICATIONS
16-bit ADC with 800 kSPS on all channels Power line monitoring
Input buffer with 5 MΩ analog input impedance Protective relays
Pin to pin compatible with the AD7606 Multiphase motor control
1 ppm/°C typical positive and negative full-scale error drift Instrumentation and control systems
−40°C to +125°C operating temperature range Data acquisition systems
Single 5 V analog supply and 1.71 V to 3.6 V VDRIVE supply
COMPANION PRODUCTS
±21 V input clamp protection with 8 kV ESD
Extra modes available in software mode Voltage References: ADR4525, LT6657, LTC6655
Per channel selectable analog input ranges Digital Isolators: ADuM142E, ADuM6422A, ADuM5020,
Single-ended, bipolar: ±10 V, ±5 V, and ±2.5 V ADuM5028
Per channel system phase, offset, and gain calibration AD7606x Family Software Model
Analog input open circuit detection feature Additional companion products on the AD7606B product page
≤22 LSB (typical) open circuit code error (RPD = 10 kΩ)
Self diagnostics and monitoring features
CRC error checking on read/write data and registers

FUNCTIONAL BLOCK DIAGRAM

5V 5V 1.71V TO 3.6V
100nF 100nF
100nF
1µF 1µF
AV CC REGCAP AV CC REGCAP VDRIVE

ALDO DLDO

V1 5MΩ
CLAMP CLK OSC CONVST
V1GND 5MΩ PGA SAR
LPF RESET
CLAMP
RANGE
CONTROL
INPUTS
OS0 TO OS2

V8 5MΩ
CLAMP BUSY
5MΩ PGA SAR PROGRAMMABLE FRSTDATA
V8GND DIGITAL FILTER
CLAMP LPF
OPTIONAL SERIAL D OUTA TO DOUT D1
RC FILTER
ADC, PGA, AND SDI2
REFCAPA CHANNEL
CONFIGURATION SCLK3
PARALLEL/
10µF + SERIAL CS
INTERFACE
OPTIONAL EXTERNAL REFCAPB GAIN, OFFSET PARALLEL DB0 TO DB151
REFERENCE AND PHASE
AVCC CALIBRATION RD3
REFIN/REFOUT INTERNAL
+2.5V REFERENCE
V IN VOUT WR
+
100nF 2.5V DIAGNOSTICS PAR/SER SEL
1µF 0.1µF ADR4525 REF AND SENSOR
REF SELECT DISCONNECT
GND REFGND AD7606B

AGND

1D
OUTA TO DOUTD ARE SINGLE FUNCTIONS OF MULTIFUNCTION PINS, DB7/DOUTA TO DB10/D OUTD.
26071-001

2SDI IS A SINGLE FUNCTION OF THE DB11/SDI MULTIFUNCTION PIN.

3RD AND SCLK ARE SINGLE FUNCTIONS OF THE RD/SCLK MULTIFUNCTION PIN.

Figure 1.

Rev. A Document Feedback

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AD7606B Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 System Calibration Features .......................................................... 31
Applications ....................................................................................... 1 System Phase Calibration .......................................................... 31
Companion Products ....................................................................... 1 System Gain Calibration............................................................ 31
Functional Block Diagram .............................................................. 1 System Offset Calibration ......................................................... 32
Revision History ............................................................................... 3 Analog Input Open Circuit Detection .................................... 32
General Description ......................................................................... 4 Digital Interface .............................................................................. 34
Specifications..................................................................................... 5 Hardware Mode .......................................................................... 34
Timing Specifications .................................................................. 8 Software Mode ............................................................................ 34
Absolute Maximum Ratings.......................................................... 12 Parallel Interface ......................................................................... 34
Thermal Resistance .................................................................... 12 Serial Interface ............................................................................ 37
Electrostatic Discharge (ESD) Ratings .................................... 12 Diagnostics ...................................................................................... 41
ESD Caution ................................................................................ 12 Reset Detection ........................................................................... 41
Pin Configuration and Function Descriptions ........................... 13 Overvoltage and Undervoltage Events .................................... 41
Typical Performance Characteristics ........................................... 16 Digital Error ................................................................................ 41
Terminology .................................................................................... 22 Diagnostics Multiplexer ............................................................ 44
Theory of Operation ...................................................................... 24 Typical Connection Diagram ....................................................... 46
Analog Front End ....................................................................... 24 Applications Information .............................................................. 48
SAR ADC..................................................................................... 25 Layout Guidelines....................................................................... 49
Reference ..................................................................................... 26 Register Summary .......................................................................... 51
Operation Modes ........................................................................ 26 Register Details ............................................................................... 53
Digital Filter .................................................................................... 29 Outline Dimensions ....................................................................... 72
Padding Oversampling .............................................................. 30 Ordering Guide .......................................................................... 72
External Oversampling Clock................................................... 30

Rev. A | Page 2 of 72
Data Sheet AD7606B
REVISION HISTORY
4/2021—Rev. 0 to Rev. A Changes to Analog Input Open Circuit Detection Section and
Changed ADC Mode to ADC Read Mode ................ Throughout Figure 60 ........................................................................................... 32
Changes to Features Section and Figure 1 ..................................... 1 Changes to Automatic Mode Section and Table 20 .................... 33
Added Companion Products Section ............................................. 1 Changes to Table 23 ........................................................................ 34
Changes to Table 1 ............................................................................ 4 Changes to Reading During Conversion Section ....................... 35
Changes to Table 2 ............................................................................ 5 Added Figure 64; Renumbered Sequentially ............................... 36
Added Note 9, Table 2....................................................................... 7 Changed Reading During Conversion Section to Reading
Changes to tD_BSY Parameter, Table 3; and Figure 2 ....................... 8 During Conversion—Serial Interface Section............................. 38
Change to tH_SCK_DO Parameter, Table 5 .........................................10 Changes to Reading During Conversion—Serial Interface
Changes to Table 6 ..........................................................................11 Section .............................................................................................. 38
Added Electrostatic Discharge (ESD) Ratings Section, ESD Changes to Memory Map CRC Section ....................................... 41
Ratings for AD7606B Section, and Table 8; Renumbered Change to Interface CRC Checksum Section ............................. 42
Sequentially ......................................................................................11 Added Internal Clock Counters Section and Figure 84 ............. 44
Change to Figure 8 ..........................................................................12 Changes to Table 31, Figure 83, and Temperature Sensor
Replaced Figure 31 ..........................................................................19 Section .............................................................................................. 44
Changes to Figure 27 to Figure 29 and Figure 30 ......................19 Changes to Internal LDOs Section ............................................... 45
Changes to Figure 36 to Figure 38 ................................................20 Changes to Applications Information Section ............................ 48
Changes to Terminology Section ..................................................21 Added Figure 88 .............................................................................. 48
Changes to Figure 47 ......................................................................25 Changes to Table 71 ........................................................................ 67
Changes to Reference Section........................................................26 Changes to Table 72 ........................................................................ 68
Added Simultaneous Sampling of Multiple AD7606B Devices Changes to Table 73 ........................................................................ 69
Section and Figure 55; Renumbered Sequentially ......................30 Changes to Table 76 ........................................................................ 71
Changes to System Gain Calibration Section and Figure 59 .....31
6/2019—Revision 0: Initial Version

Rev. A | Page 3 of 72
AD7606B Data Sheet

GENERAL DESCRIPTION
The AD7606B is a 16-bit, simultaneous sampling, analog-to- In hardware mode, the AD7606B is fully compatible with the
digital data acquisition system (DAS) with eight channels. AD7606. In software mode, the following advanced features are
Each channel contains analog input clamp protection, a available:
programmable gain amplifier (PGA), a low-pass filter, and a
• Additional ±2.5 V analog input range.
16-bit successive approximation register (SAR), analog-to-digital
• Analog input range (±10 V, ±5 V, and ±2.5 V), selectable
converter (ADC). The AD7606B also contains a flexible digital
per channel.
filter, low drift, 2.5 V precision reference and reference buffer to
• Additional oversampling (OS) options, up to OS × 256.
drive the ADC and flexible parallel and serial interfaces.
• System gain, system offset, and system phase calibration
The AD7606B operates from a single 5 V supply and accommo- per channel.
dates ±10 V, ±5 V, and ±2.5 V true bipolar input ranges when • Analog input open circuit detector.
sampling at throughput rates of 800 kSPS for all channels. The
• Diagnostic multiplexer.
input clamp protection tolerates voltages up to ±21 V. The
• Monitoring functions (serial peripheral interface (SPI))
AD7606B has a 5 MΩ analog input impedance, resulting in less
invalid read/write, cyclic redundancy check (CRC),
than 20 LSB bipolar zero code when the input signal is discon-
overvoltage and undervoltage events, busy stuck monitor,
nected and pulled to ground through a 10 kΩ external resistor.
and reset detection).
The single supply operation, on-chip filtering, and high input
impedance eliminates the need for external driver op amps, which Note that throughout this data sheet, multifunction pins, such
require bipolar supplies. For applications with lower throughput as the RD/SCLK pin, are referred to either by the entire pin
rates, the AD7606B flexible digital filter can be used to improve name or by a single function of the pin, for example, the SCLK pin,
noise performance. when only that function is relevant.

Table 1. Bipolar Input, Simultaneous Sampling, Pin to Pin Compatible Family of Devices
Input Type Resolution (Bits) RIN 1 = 1 MΩ, 200 kSPS RIN = 5 MΩ, 800 kSPS RIN = 1 MΩ, 1 MSPS Number of Channels
Single-Ended 18 AD7608 AD7606C-182 8
16 AD7606 AD7606B 2 AD7606C-162 8
AD7606-6 6
AD7606-4 4
14 AD7607 8
True Differential 18 AD7609 AD7606C-182 8
16 AD7606C-162 8
1
RIN is input impedance.
2
This state-of-the-art device is recommended for newer designs as an alternative to the AD7606, AD7608, and AD7609.

Rev. A | Page 4 of 72
Data Sheet AD7606B

SPECIFICATIONS
Voltage reference (VREF) = 2.5 V external and internal, analog supply voltage (AVCC) = 4.75 V to 5.25 V, logic supply voltage (VDRIVE) =
1.71 V to 3.6 V, sample frequency (fSAMPLE) = 800 kSPS, with no oversampling, TA = −40°C to +125°C, single-ended input, and all input
voltage ranges, unless otherwise noted.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE Input frequency (fIN) = 1 kHz sine wave, unless
otherwise noted
Signal-to-Noise Ratio (SNR) 1 No oversampling (OS), ±10 V range 87.5 89.5 dB
No OS, ±5 V range 86.5 88.5 dB
No OS, ±2.5 V range 83.5 86 dB
Oversampling ratio (OSR) = 16×, ±10 V range 92 93.5 dB
OSR = 16×, ±5 V range 90.5 92 dB
OSR = 16×, ±2.5 V range 87.5 89 dB
Total Harmonic Distortion (THD) All input ranges
fSAMPLE = 200 kSPS −105 −94 dB
fSAMPLE = 800 kSPS −100 −90 dB
Signal-to-Noise-and-Distortion No OS, ±10 V range 86.5 88.5 dB
No OS, ±5 V range 85.5 87.7 dB
No OS, ±2.5 V range 83 85.5 dB
OSR = 16×, ±10 V range 89 92 dB
OSR = 16×, ±5 V range 89 91.3 dB
OSR = 16×, ±2.5 V range 86.5 88.7 dB
Spurious-Free Dynamic Range −104 dB
(SFDR)
Channel to Channel Isolation fIN on unselected channels up to 160 kHz −110 dB
Full-Scale Step Settling Time 0.01% of full scale
±10 V range 70 µs
±5 V range 110 μs
±2.5V range 130 μs
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 22.5 kHz
−3 dB, ±5 V range 13.5 kHz
−3 dB, ±2.5 V range 11.5 kHz
−0.1 dB, ±10 V range 3 kHz
−0.1 dB, ±5 V range 2 kHz
−0.1 dB, ±2.5 V range 2 kHz
Phase Delay ±10 V range 7.5 µs
±5 V range 12 µs
±2.5 V range 14 µs
Phase Delay Matching ±10 V range 240 ns
±5 V range 365 ns
±2.5 V range 445 ns
DC ACCURACY
Resolution No missing codes 16 Bits
Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB 2
Integral Nonlinearity (INL) fSAMPLE = 200 kSPS ±1 ±2 LSB2
fSAMPLE = 800 kSPS ±1 ±2.5 LSB2
Total Unadjusted Error (TUE) External reference ±3 ±47 LSB

Rev. A | Page 5 of 72
AD7606B Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Positive and Negative Full-Scale (FS) ±2 ±30 LSB
Error 3
RFILTER 4 = 20 kΩ, system gain calibration disabled 126 LSB
RFILTER4 = 0 kΩ to 65 kΩ, system gain calibration enabled 4 LSB
Positive and Negative FS Error Drift ±1 ±3 ppm/°C
Positive and Negative FS Error 3 20 LSB
Matching
Bipolar Zero Code Error ±1 ±20 LSB2
TA = −40°C to +85°C ±1 ±14 LSB
Bipolar Zero Code Error Drift ±0.5 ±2.5 ppm/°C
Bipolar Zero Code Error Matching 1.5 23 LSB2
TA = −40°C to +85°C 1.4 14 LSB
Open Circuit Code Error Pull-down resistor (RPD) 5 = 10 kΩ, ±10 V range ±12 ±30 LSB
RPD = 10 kΩ, ±10 V range, TA = −40°C to +85°C ±12 ±20 LSB
RPD = 10 kΩ, ±5 V range ±17 ±35 LSB
RPD = 10 kΩ, ±5 V range, TA = −40°C to +85°C ±17 ±25 LSB
RPD = 10 kΩ, ±2.5 V range ±22 ±40 LSB
RPD = 10 kΩ, ±2.5 V range, TA = −40°C to +85°C ±22 ±30 LSB
SYSTEM CALIBRATION
Positive Full-Scale (PFS) and Series resistor in front of the Vx+ and VxGND inputs 0 64 kΩ
Negative Full-Scale (NFS)
Calibration Range
Offset Calibration Range −128 +127 LSB
Phase Calibration Range 0 318.75 μs
PFS and NFS Error After gain calibration ±5 LSB
Offset Error After offset calibration ±0.5 LSB
Phase Error After phase calibration ±1 μs
ANALOG INPUT
Input Voltage Ranges Vx − VxGND
±10 V range −10 +10 V
±5 V range −5 +5 V
±2.5 V range −2.5 +2.5 V
Input Voltage Ranges VxGND − AGND
±10 V range −0.7 +1.9 V
±5 V range −0.1 +2.7 V
±2.5 V range −0.1 +3.1 V
Analog Input Current See the Typical Performance Characteristics section (VIN − 2)/RIN µA
Input Capacitance (CIN) 6 5 pF
Input Impedance (RIN) 7 5 MΩ
Input Impedance Drift ±1 ±25 ppm/°C
REFERENCE INPUT/OUTPUT
Reference Input Voltage REF SELECT = 0, external reference 2.495 2.5 2.505 V
DC Leakage Current ±0.12 µA
Input Capacitance6 7.5 pF
Reference Output Voltage REF SELSECT = 1, internal reference, TA = 25°C 2.4975 2.5 2.5025 V
Reference Temperature Coefficient ±3 ±10 ppm/°C
Reference Voltage to the ADC REFCAPA (Pin 44) and REFCAPB (Pin 45) 4.39 4.41 V
LOGIC INPUTS
Input High Voltage (VINH) 0.7 × VDRIVE V
Input Low Voltage (VINL) 0.3 × VDRIVE V
Input Current (IIN) ±1 µA
Input Capacitance6 5 pF

Rev. A | Page 6 of 72
Data Sheet AD7606B
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC OUTPUTS
Output High Voltage (VOH) Current source (ISOURCE) = 100 µA VDRIVE − 0.2 V
Output Low Voltage (VOL) Current sink (ISINK) = 100 µA 0.2 V
Floating State Leakage Current ±1 µA
Output Capacitance6 5 pF
Output Coding Twos complement N/A 8
CONVERSION RATE
Conversion Time See Table 3 0.75 µs
Acquisition Time (tACQ) 9 0.5 µs
Throughput Rate Per channel 800 kSPS
POWER REQUIREMENTS
AVCC 4.75 5 5.25 V
VDRIVE 1.71 3.6 V
REGCAP 1.875 1.93 V
AVCC Current (IAVCC)
Normal Mode (Static) 7.5 9.5 mA
Normal Mode (Operational) fSAMPLE = 800 kSPS 43 47.5 mA
fSAMPLE = 10 kSPS 8 10 mA
Standby 3.5 4.5 mA
Shutdown Mode 0.5 5 µA
VDRIVE Current (IDRIVE)
Normal Mode (Static) 1.8 3.5 µA
Normal Mode (Operational) fSAMPLE = 800 kSPS 1.1 1.5 mA
fSAMPLE = 10 kSPS 30 75 µA
Standby 1.6 3 µA
Shutdown Mode 0.8 2 µA
Power Dissipation
Normal Mode (Static) 40 50 mW
Normal Mode (Operational) fSAMPLE = 800 kSPS 230 255 mW
fSAMPLE = 10 kSPS 42 50 mW
Standby 18 24 mW
Shutdown Mode 2.5 25 µW
1
No OS means no oversampling is applied.
2
LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 76.293 µV. With a ±5 V input range, 1 LSB = 152.58 µV. With a ±10 V input range, 1 LSB = 305.175 µV.
3
These specifications include the full temperature range variation and contribution from the reference buffer.
4
RFILTER is a resistor placed in a series to the analog input front end. See Figure 57.
5
See Figure 60.
6
Not production tested. Sample tested during initial release to ensure compliance.
7
Input impedance variation is factory trimmed and accounted for in the System Gain Calibration section.
8
N/A means not applicable.
9
The ADC input is settled by the internal PGA. Therefore, the acquisition time is the time between the end of the conversion and the start of the next conversion with
no impact on external components

Rev. A | Page 7 of 72
AD7606B Data Sheet
TIMING SPECIFICATIONS
Universal Timing Specifications
AVCC = 4.75 V to 5.25 V, VDRIVE = 1.71 V to 3.6 V, VREF = 2.5 V external reference and internal reference, and TA = −40°C to +125°C, unless
otherwise noted. Interface timing is tested using a load capacitance of 20 pF, dependent on VDRIVE and load capacitance for serial interface.
Table 3.
Parameter Min Typ Max Unit Description
tCYCLE 1.25 µs Minimum time between consecutive CONVST rising edges (excluding oversampling
modes) 1
tLP_CNV 10 ns CONVST low pulse width
tHP_CNV 10 ns CONVST high pulse width
tD_CNV_BSY CONVST high to BUSY high delay time
20 ns VDRIVE > 2.7 V
25 ns VDRIVE < 2.7 V
tS_BSY 0 ns Minimum time from BUSY falling edge to RD falling edge setup time (in parallel interface)
or to MSB being available on DOUTx line (in serial interface)
tD_BSY 25 ns Minimum time between last RD falling edge (in parallel interface) or last LSB being
clocked out (serial interface) and the following BUSY falling edge; read during conversion
tCONV 0.65 0.85 μs Conversion time; no oversampling
2.2 2.3 μs Oversampling by 2
4.65 4.8 μs Oversampling by 4
9.6 9.9 μs Oversampling by 8
19.4 20 μs Oversampling by 16
39.2 40.2 μs Oversampling by 32
78.7 80.8 μs Oversampling by 64
157.6 161.9 μs Oversampling by 128
315.6 324 μs Oversampling by 256
tRESET
Partial Reset 55 2000 ns Partial RESET high pulse width
Full Reset 3000 ns Full RESET high pulse width
tDEVICE_SETUP µs Time between RESET falling edge and first CONVST rising edge
Partial Reset 50 ns
Full Reset 253 µs
tWAKE_UP Wake-up time after standby/shutdown mode
Standby 1 µs
Shutdown 10 ms
tPOWER-UP 10 ms Time between stable AVCC/VDRIVE and assertion of RESET
1
Applies to serial mode when all four DOUTx lines are selected.

AVCC
VDRIVE
tPOWER-UP
tRESET

RESET

tDEVICE_SETUP tCYCLE
tHP_CNV
tLP_CNV
CONVST
tCONV tACQ
tD_CNV_BSY
BUSY
tS_BSY tD_BSY
15137-002

DOUTx
DBx

Figure 2. Universal Timing Diagram

Rev. A | Page 8 of 72
Data Sheet AD7606B
Parallel Mode Timing Specifications
Table 4.
Parameter Min Typ Max Unit Description
tS_CS_RD 0 ns CS falling edge to RD falling edge setup time
tH_RD_CSi 0 ns RD rising edge to CS rising edge hold time
tHP_RD 10 ns RD high pulse width
tLP_RD 10 ns RD low pulse width
tHP_CS 10 ns CS high pulse width
tD_CS_DB 35 ns Delay from CS until DBx three-state disabled
tH_CS_DB 0 ns CS to DBx hold time
tD_RD_DB Data access time after falling edge of RD
27 ns VDRIVE > 2.7 V
37 ns VDRIVE < 2.7 V
tH_RD_DB 12 ns Data hold time after falling edge of RD
tDHZ_CS_DB 40 ns CS rising edge to DBx high impedance
tCYC_RD RD falling edge to next RD falling edge
30 ns VDRIVE > 2.7 V
40 ns VDRIVE < 2.7 V
tD_CS_FD 26 ns Delay from CS falling edge until FRSTDATA three-state disabled
tD_RD_FDH 30 ns Delay from RD falling edge until FRSTDATA high
tD_RD_FDL 30 ns Delay from RD falling edge until FRSTDATA low
tDHZ_FD 28 ns Delay from CS rising edge until FRSTDATA three-state enabled
tS_CS_WR 0 ns CS to WR setup time
tHP_WR 213 ns WR high pulse width
tLP_WR WR low pulse width
88 ns VDRIVE > 2.7 V
213 ns VDRIVE < 2.7 V
tH_WR_CS 0 ns WR hold time
tS_DB_WR 5 ns Configuration data to WR setup time
tH_WR_DB 5 ns Configuration data to WR hold time
tCYC_WR 230 ns Configuration data settle time, WR rising edge to next WR rising edge

CS

tS_CS_RD tHP_RD tLP_RD tH_RD_CS

RD
tD_RD_DB tCYC_RD
tD_CS_DB tH_CS_DB
tH_RD_DB tDHZ_CS_DB
DB0 TO DB15 x VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
tD_CS_FD tD_RD_FDL
tD_RD_FDH tDHZ_FD
15137-003

FRSTDATA

Figure 3. Parallel Mode Read Timing Diagram, Separate CS and RD Pulses

Rev. A | Page 9 of 72
AD7606B Data Sheet
tCYC_RD
tHP_CS

CS AND RD

tD_RD_DB tLP_RD tH_CS_DB

tDHZ_CS_DB
DB0 TO DB15 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8

tD_CS_FD tD_RD_FDL tDHZ_FD

15137-004
FRSTDATA

Figure 4. Parallel Mode Read Timing Diagram, Linked CS and RD

CS
tHP_WR tH_WR_CS
tS_CS_WR
tCYC_WR
WR
tS_DB_WR tLP_WR
tH_WR_DB

15137-005
DB0 TO DB15

Figure 5. Parallel Mode Write Operation Timing Diagram

Serial Mode Timing Specifications

Table 5.
Parameter Min Typ Max Unit Description
fSCLK SCLK frequency; fSCLK = 1/tSCLK
60 MHz VDRIVE > 2.7 V
40 MHz VDRIVE < 2.7 V
tSCLK 1/fSCLK μs Minimum SCLK period
tS_CS_SCK 2 ns CS to SCLK falling edge setup time
tH_SCK_CS 2 ns SCLK to CS rising edge hold time
tLP_SCK 0.4 × tSCLK ns SCLK low pulse width
tHP_SCK 0.4 × tSCLK ns SCLK high pulse width
tD_CS_DO Delay from CS until DOUTx three-state disabled
9 ns VDRIVE > 2.7 V
18 ns VDRIVE < 2.7 V
tD_SCK_DO Data out access time after SCLK rising edge
15 ns VDRIVE > 2.7 V
25 ns VDRIVE < 2.7 V
tH_SCK_DO 5 ns Data out hold time after SCLK rising edge
tS_SDI_SCK 8 ns Data in setup time before SCLK falling edge
tH_SCK_SDI 0 ns Data in hold time after SCLK falling edge
tDHZ_CS_DO CS rising edge to DOUTx high impedance
7 ns VDRIVE > 2.7 V
22 ns VDRIVE < 2.7 V
tWR 25 ns Time between writing and reading the same register or between two writes;
if fSCLK >50 MHz
tD_CS_FD 26 ns Delay from CS until DOUTx three-state disabled/delay from CS until MSB valid
tD_SCK_FDL 18 ns 16th SCLK falling edge to FRSTDATA low
tDHZ_FD 28 ns CS rising edge until FRSTDATA three-state enabled

Rev. A | Page 10 of 72
Data Sheet AD7606B
CS

tHP_SCK
tS_CS_SCK tSCLK tH_SCK_CS

SCLK 1 2 3 14 15 16
tLP_SCK
tD_CS_DO tDHZ_CS_DO
tD_SCK_DO tH_SCK_DO
DOUTx DB15 DB14 DB13 DB2 DB1 DB0

tD_SCK_FDL
tD_CS_FD
tDHZ_FD

15137-006
FRSTDATA

Figure 6. Serial Timing Diagram, ADC Read Mode (Channel 1)

CS
tS_CS_SCK tSCLK
tHP_SCK tH_SCK_CS

SCLK 1 2 3 8 9 16

tH_SCK_SDI tLP_SCK
tS_SDI_SCK
tWR
SDI WEN R/W ADD5 ADD0 DIN7 DIN0

15137-007
tD_CS_DO tD_SCK_DO
DOUTx DOUT7 DOUT0

Figure 7. Serial Interface Timing Diagram, Register Map Read/Write Operations

Rev. A | Page 11 of 72
AD7606B Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 6. Thermal performance is directly linked to printed circuit
Parameter Rating board (PCB) design and operating environment. Close
attention to PCB thermal design is required.
AVCC to AGND −0.3 V to +6.5 V
VDRIVE to AGND −0.3 V to AVCC + 0.3 V θJA is the natural convection junction to ambient thermal
Analog Input Voltage to AGND1 ±21 V resistance measured in a one cubic foot sealed enclosure. θJC is
Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V the junction to case thermal resistance.
Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V
Table 7. Thermal Resistance
REFIN/REFOUT to AGND −0.3 V to AVCC + 0.3 V
Package Type θJA1 θJC Unit
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +125°C ST-64-2 40 7 °C/W
Storage Temperature Range −65°C to +150°C 1
Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural
Junction Temperature 150°C convention environment.
Pb/Sn Temperature, Soldering ELECTROSTATIC DISCHARGE (ESD) RATINGS
Reflow (10 sec to 30 sec) 240 (+0)°C
The following ESD information is provided for handling of
Pb-Free Temperature, Soldering Reflow 260 (+0)°C
ESD-sensitive devices in an ESD protected area only.
1
Transient currents of up to 100 mA do not cause silicon controlled Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
rectifier (SCR) latch-up.
Stresses at or above those listed under Absolute Maximum
ESD Ratings for AD7606B
Ratings may cause permanent damage to the product. This is a Table 8. AD7606B, 64-lead LQFP
stress rating only; functional operation of the product at these ESD Model Withstand Threshold (V) Class
or any other conditions above those indicated in the operational HBM
section of this specification is not implied. Operation beyond All Pins Except Analog 3500 3A
the maximum operating conditions for extended periods may Inputs
affect product reliability. Analog Input Pins Only 8000 3A

ESD CAUTION

Rev. A | Page 12 of 72
Data Sheet AD7606B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V8GND

V7GND

V6GND

V5GND

V4GND

V3GND

V2GND

V1GND
V8

V7

V6

V5

V4

V3

V2

V1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AVCC 1 48 AVCC
AGND 2 47 AGND
OS0 3 46 REFGND
OS1 4 45 REFCAPB
OS2 5 44 REFCAPA
PAR/SER SEL 6 43 REFGND
AD7606B 42
STBY 7
TOP VIEW REFIN/REFOUT
RANGE 8 (Not to Scale) 41 AGND
CONVST 9 40 AGND
WR 10 39 REGCAP
RESET 11 38 AVCC
RD/SCLK 12 37 AVCC
CS 13 36 REGCAP
BUSY 14 35 AGND
FRSTDATA 15 34 REF SELECT
DB0 16 33 DB15

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DB7/DOUTA

DB11/SDI
DB1
DB2
DB3
DB4
DB5
DB6

DB8/DOUTB
AGND
DB9/DOUTC
DB10/DOUTD
VDRIVE

DB12
DB13
DB14
ANALOG INPUT DATA OUTPUT

15137-008
DECOUPLING CAPACITOR PIN DIGITAL OUTPUT
POWER SUPPLY DIGITAL INPUT
GROUND PIN REFERENCE INPUT/OUTPUT

Figure 8. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Type 1 Mnemonic Description
1, 37, 38, 48 P AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. Decouple these supply pins to AGND.
2, 26, 35, 40, P AGND Analog Ground. These pins are the ground reference points for all analog circuitry on the
41, 47 AD7606B. All analog input signals and external reference signals must be referred to these pins. All
six of the AGND pins must connect to the AGND plane of a system.
3 to 5 DI OS0 to OS2 Oversampling Mode Pins. These inputs select the oversampling ratio or enable software mode
(see Table 13 for oversampling pin decoding). See the Digital Filter section for more details about
the oversampling mode of operation.
6 DI PAR/SER SEL Parallel/Serial Interface Selection Input. If this pin is tied to a logic low, the parallel interface is
selected. If this pin is tied to a logic high, the serial interface is selected. See the Digital Interface
section for more information on each interface available.
7 DI STBY Standby Mode Input. In hardware mode, this pin, in combination with the RANGE pin, places the
AD7606B in one of two power-down modes: standby mode or shutdown mode. In software mode,
this pin is ignored. Therefore, it is recommended to connect this pin to logic high. See the Power-
Down Modes section for more information on both hardware mode and software mode.
8 DI RANGE Analog Input Range Selection Input. In hardware mode, this pin determines the input range of the
analog input channels (see Table 10). If the STBY pin is at logic low, this pin determines the power-
down mode (see Table 15). In software mode, the RANGE pin is ignored. However, this pin must be
tied high or low.
9 DI CONVST Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is
sampled on all eight SAR ADCs. In software mode, this pin can be configured as external
oversampling clock. Providing a low jitter external clock improves the SNR performance for large
oversampling ratios. See the External Oversampling Clock section for further details.
10 DI WR Digital Input. In hardware mode, this pin has no function. Therefore, it can be tied high, tied low,
or shorted to CONVST. In software mode, this pin is an active low write pin for writing registers
using the parallel interface. See the Parallel Interface section for more information.

Rev. A | Page 13 of 72
AD7606B Data Sheet
Pin No. Type 1 Mnemonic Description
11 DI RESET Reset Input, Active High. Full and partial reset options are available on the AD7606B. The type of
reset is determined by the length of the reset pulse. Ensure that the device receives a full reset
pulse after power-up. See the Reset Functionality section for further details.
12 DI RD/SCLK Parallel Data Read Control Input when the Parallel Interface is Selected (RD).
Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for
more details.
13 DI CS Chip Select. This pin is the active low chip select input for ADC data read or register data read and
write, in both serial and parallel interface. See the Digital Interface section for more details.
14 DO BUSY Busy Output. This pin transitions to a logic high along with the CONVST rising edge. The BUSY
output remains high until the conversion process for all channels is complete.
15 DO FRSTDATA First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read
back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital
Interface section for more details.
16 to 22 DO/DI DB0 to DB6 Parallel Output/Input Data Bits. When using parallel interface, these pins act as three-state parallel
digital input and output pins (see the Parallel Interface section). When using serial interface, tie
these pins to AGND. See Table 22 and Table 23 for more details on each data interface and
operation mode.
23 P VDRIVE Logic Power Supply Input. The voltage (1.71 V to 3.6 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the
host interface, that is, data signal processing (DSP) and field-programmable gate array (FPGA).
24 DO/DI DB7/DOUTA Parallel Output/Input Data Bit 7 (DB7). When using the parallel interface, this pin acts as a three-
state parallel digital input/output pin.
Serial Interface Data Output Pin (DOUTA). When using the serial interface, this pin functions as
DOUTA.
See Table 22 and Table 23 for more details on each data interface and operation mode.
25 DO/DI DB8/DOUTB Parallel Output/Input Data Bit 8 (DB8). When using the parallel interface, this pin acts as a three-
state parallel digital input and output pin.
Serial Interface Data Output Pin (DOUTB). When using the serial interface, this pin functions
as DOUTB.
See Table 22 and Table 23 for more details on each data interface and operation mode.
27 DO/DI DB9/DOUTC Parallel Output/Input Data Bit 9 (DB9). When using the parallel interface, this pin acts as a three-
state parallel digital input and output pin.
Serial Interface Data Output Pin (DOUTC). When using the serial interface, this pin functions
as DOUTC if in software mode and using four data output lines option.
See Table 22 and Table 23 for more details on each data interface and operation mode.
28 DO/DI DB10/DOUTD Parallel Output/Input Data Bit 10 (DB10). When using the parallel interface, this pin acts as a three-
state parallel digital input/output pin.
Serial Interface Data Output Pin (DOUTD). When using the serial interface, this pin functions
as DOUTD if in software mode and using the four data output lines option.
See Table 22 and Table 23 for more details on each data interface and operation mode.
29 DO/DI DB11/SDI Parallel Output/Input Data Bit 11 (DB11). When using the parallel interface, this pin acts as a three-
state parallel digital input and output pin.
Serial Data Input (SDI). When using the serial interface in software mode, this pin functions as a
serial data input.
See Table 22 and Table 23 for more details on each data interface and operation mode.
30 to 33 DO/DI DB12 to Parallel Output/Input Data Bits, DB12 to DB15. When using the parallel interface, these pins act as
DB15 three-state parallel digital input and output pins (see the Parallel Interface section). When using
the serial interface, tie these pins to AGND.
34 DI REF SELECT Internal/External Reference Selection Logic Input. If this pin is set to logic high, the internal
reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled
and an external reference voltage must be applied to the REFIN/REFOUT pin.
36, 39 P REGCAP Decoupling Capacitor Pins for Voltage Output from 1.9 V Internal Regulator, Analog Low
Dropout (ALDO) and Digital Low Dropout (DLDO). These output pins must be decoupled
separately to AGND using a 1 μF capacitor.

Rev. A | Page 14 of 72
Data Sheet AD7606B
Pin No. Type 1 Mnemonic Description
42 REF REFIN/ Reference Input (REFIN)/Reference Output (REFOUT). The internal 2.5 V reference is available on
REFOUT the REFOUT pin for external use while the REF SELECT pin is set to logic high. Alternatively, by
setting the REF SELECT pin to logic low, the internal reference is disabled and an external
reference of 2.5 V must be applied to this input (REFIN). A 100 nF capacitor must be applied from
the REFIN pin to ground, close to the REFGND pins, for both internal and external reference
options. See the Reference section for more details.
43, 46 REF REFGND Reference Ground Pins. These pins must be connected to AGND.
44, 45 REF REFCAPA, Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled
REFCAPB to AGND using a low effective series resistance (ESR), 10 μF ceramic capacitor. The voltage on
these pins is typically 4.4 V.
49 AI V1 Channel 1 Positive Analog Input Pin.
50 AI GND V1GND Channel 1 Negative Analog Input Pin.
51 AI V2 Channel 2 Positive Analog Input Pin.
52 AI GND V2GND Channel 2 Negative Analog Input Pin.
53 AI V3 Channel 3 Positive Analog Input Pin.
54 AI GND V3GND Channel 3 Negative Analog Input Pin.
55 AI V4 Channel 4 Positive Analog Input Pin.
56 AI GND V4GND Channel 4 Negative Analog Input Pin.
57 AI V5 Channel 5 Positive Analog Input Pin.
58 AI GND V5GND Channel 5 Negative Analog Input Pin.
59 AI V6 Channel 6 Positive Analog Input Pin.
60 AI GND V6GND Channel 6 Negative Analog Input Pin.
61 AI V7 Channel 7 Positive Analog Input Pin.
62 AI GND V7GND Channel 7 Negative Analog Input Pin.
63 AI V8 Channel 8 Positive Analog Input Pin.
64 AI GND V8GND Channel 8 Negative Analog Input Pin.
1
P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground.

Rev. A | Page 15 of 72
AD7606B Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0 0
AVCC = 5V, VDRIVE = 3.3V AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFERENCE INTERNAL REFERENCE
–20 ±10V RANGE –20 ±5V RANGE
fSAMPLE = 800kSPS fSAMPLE = 800kSPS
–40 fIN = 1kHz –40 fIN = 1kHz
32768 POINT FFT 32768 POINT FFT
SNR = 89.2dB SNR = 88.3dB
–60 –60
AMPLITUDE (dB)

AMPLITUDE (dB)
THD = –108.3dB THD = –103dB

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180
15137-009

15137-012
0.1 1 10 100 0.1 1 10 100
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 9. Fast Fourier Transform (FFT), ±10 V Range Figure 12. FFT, ±5 V Range

0 0
AVCC = 5V, VDRIVE = 3.3V AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFERENCE –20 INTERNAL REFERENCE
–20 ±10V RANGE
±2.5V RANGE
fSAMPLE = 800kSPS fSAMPLE = 800kSPS
–40 fIN = 146Hz
–40 fIN = 1kHz
32768 POINT FFT 8192 POINT FFT
–60 SNR = 93.6dB
–60 SNR = 86dB
AMPLITUDE (dB)

AMPLITUDE (dB)

THD = –98.5dB THD = –110dB

–80
–80
–100
–100
–120
–120
–140
–140
–160

–160 –180

–180 –200
15137-010

15137-013
0.1 1 10 100 0 5 10 15 20 25
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 10. FFT, ±2.5 V Range Figure 13. FFT Oversampling by 16, ±10 V Range

2.0 2.0
AVCC = 5V, VDRIVE = 3.3V AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFERENCE INTERNAL REFERENCE
1.5 fSAMPLE = 800kSPS 1.5 fSAMPLE = 800kSPS
T = 25°C T = 25°C
1.0 1.0

0.5 0.5
DNL (LSB)
INL (LSB)

0 0

–0.5 –0.5

–1.0 –1.0

–1.5 –1.5

–2.0 –2.0
15137-311

15137-316

0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000
ADC CODE ADC CODE

Figure 11. Typical INL, ±10 V Range Figure 14. Typical DNL

Rev. A | Page 16 of 72
Data Sheet AD7606B
100 100
NO OS
OS BY 2
98 OS BY 4 98
OS BY 8
96 OS BY 16 96
OS BY 32
OS BY 64 94
94 OS BY 128
OS BY 256
92 92

SNR (dB)
SNR (dB)

90 90

88 88
NO OS
OS BY 2
86 86 OS BY 4
AVCC = 5V, VDRIVE = 3.3V OS BY 8
84 AVCC = 5V, VDRIVE = 3.3V 84 OS BY 16
fSAMPLE = 800kSPS/OSR fSAMPLE = 800KSPS/OSR OS BY 32
INTERNAL REFERENCE INTERNAL REFERENCE OS BY 64
82 82 T = 25°C
T = 25°C OS BY 128
±10V RANGE ±10V RANGE OS BY 256
80 80

15137-034
15137-415
0.01 0.1 1 10 100 0.01 0.1 1 10 100
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 15. SNR vs. Input Frequency for Different OSR Values, ±10 V Range, Figure 18. SNR vs. Input Frequency for Different OSR Values, ±10 V Range,
Internal OS Clock External OS Clock

100 100
NO OS
OS BY 2
98 OS BY 4 98
OS BY 8
96 OS BY 16 96
OS BY 32
OS BY 64 94
94 OS BY 128
OS BY 256
92 92
SNR (dB)
SNR (dB)

90 90

88 88
NO OS
OS BY 2
86 86 OS BY 4
AVCC = 5V, VDRIVE = 3.3V OS BY 8
84 AVCC = 5V, VDRIVE = 3.3V 84 OS BY 16
fSAMPLE = 800kSPS/OSR fSAMPLE = 800kSPS/OSR OS BY 32
INTERNAL REFERENCE INTERNAL REFERENCE OS BY 64
82 82 T = 25°C
T = 25°C OS BY 128
±5V RANGE ±5V RANGE OS BY 256
80 80

15137-032
15137-031

0.01 0.1 1 10 100 0.01 0.1 1 10 100

INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 16. SNR vs. Input Frequency for Different OSR Values, ±5 V Range, Figure 19. SNR vs. Input Frequency for Different OSR Values, ±5 V Range,
Internal OS Clock External OS Clock
100 100
NO OS
OS BY 2
98 OS BY 4
OS BY 8
96 OS BY 16
OS BY 32 95
OS BY 64
94 OS BY 128
OS BY 256
92
SNR (dB)

SNR (dB)

90 90

88

86 NO OS
OS BY 2
85 OS BY 4
AVCC = 5V, VDRIVE = 3.3V AVCC = 5V, VDRIVE = 3.3V OS BY 8
84
fSAMPLE = 800kSPS/OSR fSAMPLE = 800kSPS/OSR OS BY 16
INTERNAL REFERENCE OS BY 32
82 INTERNAL REFERENCE OS BY 64
T = 25°C T = 25°C OS BY 128
±2.5V RANGE ±2.5V RANGE OS BY 256
80 80
15137-035

15137-036

0.01 0.1 1 10 100 0.01 0.1 1 10 100

INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)

Figure 17. SNR vs. Input Frequency for Different OSR Values, ±2.5 V Range, Figure 20. SNR vs. Input Frequency for Different OSR Values, ±2.5 V Range,
Internal OS Clock External OS Clock

Rev. A | Page 17 of 72
AD7606B Data Sheet
91 –60
AVCC = 5V VDRIVE = 3.3V ±10V RANGE
fSAMPLE = 800kSPS fSAMPLE = 800kSPS
90 RSOURCE MATCHED ON Vx AND VxGND
–70

89
–80
SNR (dB)

THD (dB)
88
–90
87

–100
86 0Ω
1.2kΩ
5kΩ
85
–110 10kΩ
±2.5V 23.7kΩ
±5V 48.7kΩ
±10V 105kΩ
84 –120

15137-333

15137-326
–40 –20 0 20 40 60 80 100 120 0.01 0.1 1 10 100
TEMPERATURE (°C) INPUT FREQUENCY (kHz)

Figure 21. SNR vs. Temperature Figure 24. THD vs. Input Frequency for Various Source Impedances (RSOURCE),
±10 V Range

2.505 –60
AVCC = 5V, VDRIVE = 3.3V ±5V RANGE 0Ω
f = 800kSPS fSAMPLE = 800kSPS 1.2kΩ
2.504 SAMPLE 5kΩ
T = 25°C RSOURCE MATCHED ON Vx AND VxGND
–70 10kΩ
2.503 23.7kΩ
48.7kΩ
REFERENCE VOLTAGE (V)

2.502 105kΩ
–80
2.501
THD (dB)

2.500 –90

2.499
–100
2.498

2.497
–110
2.496

2.495 –120
15137-343

15137-327
–40 –20 0 20 40 60 80 100 120 0.01 0.1 1 10 100
TEMPERATURE (°C) INPUT FREQUENCY (kHz)

Figure 22. Reference Drift Figure 25. THD vs. Input Frequency for Various Source Impedances,
±5 V Range
25 –60
±2.5V RANGE 0Ω
fSAMPLE = 800kSPS 1.2kΩ
RSOURCE MATCHED ON Vx AND VxGND 5kΩ
–70 10kΩ
20 23.7kΩ
48.7kΩ
105kΩ
NUMBER OF HITS

–80
15
THD (dB)

–90

10
–100

5
–110

0 –120
15137-423

15137-330

–10 –5 0 5 10 0.01 0.1 1 10 100

REFERENCE DRIFT (ppm/°C) INPUT FREQUENCY (kHz)

Figure 23. Reference Drift Histogram Figure 26. THD vs. Input Frequency for Various Source Impedances,
±2.5 V Range

Rev. A | Page 18 of 72
Data Sheet AD7606B
100
PFS CH0 NFS CH0
PFS CH1 NFS CH1 PFS
PFS CH2 NFS CH2 90 NFS
PFS CH3 NFS CH3
PFS CH4 NFS CH4 80
PFS CH5 NFS CH5
PFS/NFS ERROR (LSBs)

PFS CH6 NFS CH6 70

PFS CH7 NFS CH7

NUMBER OF HITS
60

50

40

30

20

10

15137-430
0

15137-527
–40 –20 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0
TEMPERATURE (°C) NFS DRIFT (ppm/°C)

Figure 27. PFS/NFS Error vs. Temperature, ±10 V Range Figure 30. PFS/NFS Drift Histogram, External Reference

PFS CH0 NFS CH0 –50

PFS CH1 NFS CH1 ±10V RANGE AVCC = 5V,VDRIVE = 3.3V
PFS CH2 NFS CH2 ±5V RANGE INTERNAL REFERENCE

CHANNEL TO CHANNEL ISOLATION (dB)

PFS CH3 NFS CH3 –60 ±2.5V RANGE
PFS CH4 NFS CH4 fSAMPLE = 800kSPS
PFS CH5 NFS CH5 T = 25°C
PFS/NFS ERROR (LSBs)

PFS CH6 NFS CH6 –70 INTERFERER IN ALL

PFS CH7 NFS CH7 UNSELECTED CHANNELS
–80

–90

–100

–110

–120

–130
15137-528

–40 –20 0 20 40 60 80 100 120 –140

15137-043
TEMPERATURE (°C) 0 20 40 60 80 100 120 140 160
NOISE FREQUENCY (kHz)
Figure 28. PFS/NFS Error vs. Temperature, ±5 V Range
Figure 31. Channel to Channel Isolation vs. Noise Frequency

PFS CH0 NFS CH0 –40

PFS CH1 NFS CH1 ±10V RANGE
PFS CH2 NFS CH2 ±5V RANGE
PFS CH3 NFS CH3 ±2.5V RANGE
PFS CH4 NFS CH4 –50
PFS CH5 NFS CH5
PFS/NFS ERROR (LSBs)

PFS CH6 NFS CH6

PFS CH7 NFS CH7
–60
AC PSRR (dB)

–70

–80

AVCC = 5V, VDRIVE = 3.3V

–90 INTERNAL REFERENCE
RECOMMENDED DECOUPLING USED
fSAMPLE = 800kSPS
T = 25°C
15137-529

–40 –20 0 20 40 60 80 100 120 –100

15137-042

0.1 1 10 100
TEMPERATURE (°C)
AVCC NOISE FREQUENCY (kHz)
Figure 29. PFS/NFS Error vs. Temperature, ±2.5 V Range
Figure 32. AC PSRR

Rev. A | Page 19 of 72
AD7606B Data Sheet
6.0 1400
CH1 Vx AND VxGND 1303
CH2 SHORTED TOGETHER
4.8 CH3 T = 25°C
1200 1163
BIPOLAR ZERO CODE ERROR (LSB)

CH4 4096 SAMPLES

3.6 CH5 MEAN = 32767.8
CH6 SIGMA = 1.2
2.4 CH7 1000
CH8

NUMBER OF HITS
1.2 782
800
0
600
–1.2
458
–2.4 400

–3.6 246
AVCC = 5V, VDRIVE = 3.3V 200
–4.8 INTERNALREFERENCE 91
fSAMPLE = 800kSPS
–6.0 0

15137-039
15137-022
–40 –20 0 20 40 60 80 100 120 –3 –2 –1 0 1 2 3 4
TEMPERATURE (°C) ADC CODE

Figure 33. Bipolar Zero Code Error vs. Temperature, ±10 V Range Figure 36. Histogram of Codes, ±10 V Range

12.0 2000
CH1 Vx AND VxGND
CH2 1800 SHORTED TOGETHER
9.6 CH3 1727
T = 25°C
BIPOLAR ZERO CODE ERROR (LSB)

CH4 4096 SAMPLES

7.2 CH5 1600
MEAN = 32767.8
CH6
CH7 SIGMA = 0.92
4.8 1400
CH8 NUMBER OF HITS
1200 1182
2.4

0 1000
878

–2.4 800

–4.8 600

–7.2 400
AVCC = 5V, VDRIVE = 3.3V
200 177
–9.6 INTERNAL REFERENCE 119
fSAMPLE = 800kSPS 6

15137-037
–12.0 0
15137-023

–40 –20 0 20 40 60 80 100 120 –3 –2 –1 0 1 2 3 4

TEMPERATURE (°C) ADC CODE

Figure 34. Bipolar Zero Code Error vs. Temperature, ±5 V Range Figure 37. Histogram of Codes, ±5 V Range

24.0 1800
CH1 Vx AND VxGND 1702
1667
CH2 SHORTED TOGETHER
19.2 CH3 1600 T = 25°C
BIPOLAR ZERO CODE ERROR (LSB)

CH4 4096 SAMPLES

14.4 CH5 1400 MEAN = 32767.5
CH6 SIGMA = 0.8
9.6 CH7
CH8 1200
NUMBER OF HITS

4.8
1000
0
800
–4.8
600
–9.6
415
400
–14.4 281
AVCC = 5V, VDRIVE = 3.3V
–19.2 200
INTERNAL REFERENCE
fSAMPLE = 800kSPS 8 23
–24.0 0
15137-038
15137-024

–40 –20 0 20 40 60 80 100 120 –3 –2 –1 0 1 2 3 4

TEMPERATURE (°C) ADC CODE

Figure 35. Bipolar Zero Code Error vs. Temperature, ±2.5 V Range Figure 38. Histogram of Codes, ±2.5 V Range

Rev. A | Page 20 of 72
Data Sheet AD7606B
6 50
AVCC = 5V, VDRIVE = 3.3V NORMAL MODE
fSAMPLE = 800kSPS 45 AUTOSTANDBY MODE
T = 25°C
4
40
ANALOG INPUT CURRENT (μA)

AVCC SUPPLY CURRENT (mA)

35
2
30

0 25

20
–2
15

10
–4
±10V AVCC = 5V, VDRIVE = 3.3V
±5V 5 INTERNAL REFERENCE
±2.5V T = 25°C
–6 0

15137-441
15137-341
–10 –8 –6 –4 –2 0 2 4 6 8 10 0 200 400 600 800 1000
INPUT VOLTAGE (V) THROUGHPUT RATE (kSPS)

Figure 39. Analog Input Current vs. Input Voltage Figure 41. AVCC Supply Current vs. Throughput Rate

50
T = –40°C
45 T = +25°C
T = +125°C
40
AVCC SUPPLY CURRENT (mA)

35

30

25

20

15

10
AVCC = 5V, VDRIVE = 3.3V
5 INTERNAL REFERENCE
T = 25°C
0
15137-440

0 100 200 300 400 500 600 700 800

THROUGHPUT RATE (kSPS)

Figure 40. AVCC Supply Current vs. Throughput Rate

Rev. A | Page 21 of 72
AD7606B Data Sheet

TERMINOLOGY
Integral Nonlinearity (INL) The ratio depends on the number of quantization levels in
INL is the maximum deviation from a straight line passing the digitization process: the more levels, the smaller the
through the endpoints of the ADC transfer function. The quantization noise.
endpoints of the transfer function are zero scale at ½ LSB below The theoretical SINAD for an ideal N-bit converter with a sine
the first code transition and full scale at ½ LSB above the last code wave input is given by
transition.
SINAD = (6.02 N + 1.76) (dB)
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal 1 LSB Thus, for a 16-bit converter, the SINAD is 98 dB.
change between any two adjacent codes in the ADC. Total Harmonic Distortion (THD)
Bipolar Zero Code Error THD is the ratio of the rms sum of the harmonics to the
Bipolar zero code error is the deviation of the midscale fundamental. For the AD7606B, THD is defined as
transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. THD (dB) =
Bipolar Zero Code Error Match V22 + V32 + V4 2 + V52 + V62 + V7 2 + V82 + V92
Bipolar zero code error match is the absolute difference in 20log
bipolar zero code error between any two input channels. V1

Open Circuit Code Error where:

Open circuit code error is the ADC output code when there is an V1 is the rms amplitude of the fundamental.
open circuit on the analog input, and a pull-down resistor (RPD) V2 to V9 are the rms amplitudes of the second through ninth
connected between the analog input pair of pins. See Figure 60 harmonics.
for more details. Spurious-Free Dynamic Range (SFDR)
Positive Full-Scale (PFS) Error SFDR is the ratio of the rms signal amplitude of the input signal
PFS error is the deviation of the actual last code transition from to the rms value of the peak spurious spectral component.
the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V − Power Supply Rejection Ratio (PSRR)
1½ LSB (4.99977), and 2.5 V − 1½ LSB (2.49988)) after the Variations in power supply affect the full-scale transition but
bipolar zero code error is adjusted out. The positive full-scale not the linearity of the converter. The power supply rejection (PSR)
error includes the contribution from the internal reference and is the maximum change in full-scale transition point due to a
reference buffer. change in power supply voltage from the nominal value. The
Positive Full-Scale Error Matching PSRR is defined as the ratio of the 100 mV p-p sinewave applied
PFS error matching is the absolute difference in positive full- to the AVCC supplies of the ADC frequency, fS, to the power of
scale error between any two input channels. the ADC output at that frequency, fS.

Negative Full-Scale (NFS) Error PSRR (dB) = 20 log (0.1/PfS)

NFS error is the deviation of the first code transition from the where:
ideal first code transition (−10 V + ½ LSB (−9.99984), −5 V + ½ PfS is equal to the power at frequency, fS, coupled on the AVCC
LSB (−4.99992), and −2.5 V + ½ LSB (−2.49996)) after the supply.
bipolar zero code error is adjusted out. The negative full-scale Channel to Channel Isolation
error includes the contribution from the internal reference and Channel to channel isolation is a measure of the level of
reference buffer. crosstalk between all input channels. It is measured by applying
Negative Full-Scale Error Matching a full-scale sine wave signal, up to 160 kHz, to all unselected
NFS error matching is the absolute difference in negative full- input channels and then determining the degree to which the
scale error between any two input channels. signal attenuates in the selected channel with a 1 kHz sine wave
Total Unadjusted Error (TUE) signal applied (see Figure 31).
TUE is the maximum deviation of the output code from the
ideal. TUE includes INL errors, bipolar zero code and positive
and negative full-scale errors, and reference errors.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD ratio is the measured ratio of signal-to-noise-and-
distortion at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2, excluding dc).
Rev. A | Page 22 of 72
Data Sheet AD7606B
Phase Delay Phase Delay Drift
Phase delay is a measure of the absolute time delay between Phase delay drift is the change in phase delay per unit temperature
when an input is sampled by the converter and when the result across the entire operating temperature of the device.
associated with that sample is available to be read back from the Phase Delay Matching
ADC, including delay induced by the analog front end of the Phase delay matching is the maximum phase delay seen between
device. any simultaneously sampled pair.

Rev. A | Page 23 of 72
AD7606B Data Sheet

THEORY OF OPERATION
ANALOG FRONT END Figure 43 shows the input clamp current vs. the source voltage
The AD7606B is a 16-bit, simultaneous sampling, analog-to- characteristic of the clamp circuit. For input voltages of up to
digital DAS with eight channels. Each channel contains analog ±21 V, no current flows in the clamp circuit. For input voltages
input clamp protection, a PGA, a low-pass filter, and a 16-bit that are above ±21 V, the AD7606B clamp circuitry turns on.
SAR ADC. 15
TA = –40°C
TA = +25°C
Analog Input Ranges 10
TA = +125°C

INPUT CLAMP CURRENT (mA)

The AD7606B can handle true bipolar, single-ended input
voltages. In hardware mode, the logic level on the RANGE pin 5
determines either ±10 V or ±5 V as the analog input range of all
analog input channels, as shown in Table 10. 0

A logic change on the RANGE pin has an immediate effect on

the analog input range. However, there is typically a settling –5

time of approximately 80 µs in addition to the normal acquisition

–10
time requirement. Changing the RANGE pin during a conversion
is not recommended for fast throughput rate applications.
–15

15137-248
In software mode, it is possible to configure an individual –30 –20 –10 0 10 20 30
SOURCE VOLTAGE (V)
analog input range per channel using Address 0x03 through
Figure 43. Input Protection Clamp Profile
Address 0x06. The logic level on the RANGE pin is ignored in
software mode. It is recommended to place a series resistor on the analog input
channels to limit the current to ±10 mA for input voltages
Table 10. Analog Input Range Selection greater than ±21 V. In an application where there is a series
Range (V) Hardware Mode1 Software Mode2 resistance (R) on an analog input channel, Vx, it is recommended
±10 RANGE pin high Address 0x03 through to match the resistance (R) with the resistance on VxGND to
Address 0x06 eliminate any offset introduced to the system, as shown in
±5 RANGE pin low Address 0x03 through Figure 44. However, in software mode, a per channel system
Address 0x06
offset calibration removes the offset of the full system (see the
±2.5 Not applicable Address 0x03 through
System Offset Calibration section).
Address 0x06
1
The same analog input range, ±10 V or ±5 V, applies to all eight channels. During normal operation, it is not recommended to leave the
2
The analog input range (±10 V, ±5 V, or ±2.5 V) is selected on a per channel AD7606B in a condition where the analog input is greater than
basis using the memory map. the input range for extended periods of time because this
Analog Input Impedance condition can degrade the bipolar zero code error performance.
The analog input impedance (RIN) of the AD7606B is typically In shutdown or standby mode, there is no such concern.
5 MΩ. RIN is a fixed input impedance that does not vary with AD7606B
the AD7606B sampling frequency. This high analog input R Vx
CLAMP
5MΩ

impedance eliminates the need for a driver amplifier in front of the R C VxGND 5MΩ
CLAMP
AD7606B, allowing direct connection to the source or sensor.
15137-049

Therefore, bipolar supplies can be removed from the signal

chain. Figure 44. Input Resistance Matching on the Analog Input of the AD7606B

Analog Input Clamp Protection PGA

Figure 42 shows the analog input circuitry of the AD7606B. A PGA is provided at each input channel. The gain is configured
Each analog input of the AD7606B contains clamp protection depending on the analog input range selected (see Table 10) to
circuitry. Despite single, 5 V supply operation, this analog input scale the single-ended analog input signal to the ADC fully
clamp protection allows an input overvoltage of up to ±21 V. differential input range.

5MΩ
Input impedance on each input of the PGA is accurately trimmed
Vx CLAMP
16-BIT to maintain the overall gain error. This trimmed value is then
5MΩ SAR ADC
VxGND used when the gain calibration is enabled to compensate for the
15137-047

CLAMP
LPF
gain error introduced by an external series resistor. See the System
Figure 42. Analog Input Circuitry for Each Channel Gain Calibration section for more information on the PGA feature.

Rev. A | Page 24 of 72
Data Sheet AD7606B
Analog Input Antialiasing Filter New data can be read from the output register via the parallel or
An analog antialiasing filter is provided on the AD7606B. serial interface after the BUSY output goes low. Alternatively,
Figure 45 and Figure 46 show the frequency response and phase data from the previous conversion can be read while the BUSY pin
response, respectively, of the analog antialiasing filter. In the is high, as explained in the Reading During Conversion section.
±10 V range, the −3 dB frequency is typically 22.5 kHz. The AD7606B contains an on-chip oscillator that performs the
conversions. The conversion time for all ADC channels is tCONV
(see Table 3). In software mode, there is an option to apply an
external clock through the CONVST pin. Providing a low jitter
external clock improves SNR performance for large oversampling
ratios. See the Digital Filter section and Figure 15 to Figure 20
ATTENUATION (dB)

for further information.

Connect all unused analog input channels to AGND. The
results for any unused channels are still included in the data
read because all channels are always converted.
ADC Transfer Function
±10V RANGE
±5V RANGE
±2.5V RANGE
The output coding of the AD7606B is twos complement. The
designed code transitions occur midway between successive
15137-050

100 1k 10k 100k

INPUT FREQUENCY (Hz) integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is
Figure 45. Analog Antialiasing Filter Frequency Response FSR/65,536 for the AD7606B. The ideal transfer characteristics for
the AD7606B are shown in Figure 47. The LSB size is dependent on
AVCC = 5V, VDRIVE = 3.3V
fSAMPLE = 800kSPS the analog input range selected, as shown in Table 11.
T = 25°C
Vx 2.5V
±10V CODE = × 32,768 ×
10V REFIN/REFOUT
Vx 2.5V
±5V CODE = × 32,768 ×
PHASE DELAY (μs)

5V REFIN/REFOUT
Vx 2.5V
±2.5V CODE = × 32,768 ×
2.5V REFIN/REFOUT

011...111
011...110
ADC CODE

000...001 +FS – (–FS)

000...000 LSB =
±10V 2N
111...111
±5V
±2.5V
15137-051

100 1k 10k 100k 300k 100...010

100...001
INPUT FREQUENCY (Hz) 100...000

15137-052
–FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB
Figure 46. Analog Antialiasing Filter Phase Response
ANALOG INPUT
SAR ADC Figure 47. Ideal Transfer Characteristics
The AD7606B allows the ADC to accurately acquire an input Table 11. Input Voltage Ranges
signal of full-scale amplitude to 16-bit resolution. All eight SAR
Range (V) PFS (V) Midscale (V) NFS (V) LSB (μV)
ADCs sample the respective inputs simultaneously on the rising
±10 10 0 −10 305
edge of the CONVST signal.
±5 5 0 −5 152
The BUSY signal indicates when conversions are in progress. ±2.5 2.5 0 −2.5 76
Therefore, when the rising edge of the CONVST signal is applied,
the BUSY pin goes logic high and transitions low at the end of
the entire conversion process. The end of the conversion process
across all eight channels is indicated by the falling edge of the
BUSY signal. When the BUSY signal edge falls, the acquisition
time for the next set of conversions begins. The rising edge of the
CONVST signal has no effect while the BUSY signal is high.

Rev. A | Page 25 of 72
AD7606B Data Sheet
REFERENCE AD7606B AD7606B AD7606B
REF SELECT REF SELECT REF SELECT
The AD7606B contains an on-chip, 2.5 V, band gap reference.
REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT
The REFIN/REFOUT pin allows the following:
• Access to the internal 2.5 V reference, if the REF SELECT pin
100nF 100nF 100nF
is tied to logic high.
• Application of an external reference of 2.5 V, like the REF

15137-054
1µF
ADR4525 or LT6657, if the REF SELECT pin is tied to
logic low. Figure 49. Single External Reference Driving Multiple AD7606B
REFIN/REFOUT Pins
Table 12. Reference Configuration
REF SELECT Pin Reference Selected Internal Reference Mode
Logic High Internal reference enabled One AD7606B device, configured to operate in internal reference
Logic Low Internal reference disabled; an external 2.5 V mode, can drive the remaining AD7606B devices, which are
reference voltage must be applied to the configured to operate in external reference mode (see Figure 50).
REFIN/REFOUT pin Decouple the REFIN/REFOUT pin of the AD7606B, configured
The AD7606B contains a reference buffer configured to amplify in internal reference mode, using a 10 µF ceramic decoupling
the reference voltage up to approximately 4.4 V, as shown in capacitor. The other AD7606B devices, configured in external
Figure 48. The 4.4 V buffered reference is the reference used by reference mode, must use at least a 100 nF decoupling capacitor
the SAR ADC, as shown in Figure 48. After a reset, the AD7606B on their REFIN/REFOUT pins.
operates in the reference mode selected by the REF SELECT pin. VDRIVE

The REFCAPA and REFCAPB pins must be shorted together AD7606B AD7606B AD7606B
externally, and a ceramic capacitor of 10 μF must be applied to REF SELECT REF SELECT REF SELECT
the REFGND pin to ensure that the reference buffer is in closed- REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT
loop operation. A 10 µF ceramic capacitor is required on the
REFIN/REFOUT pin. +

15137-055
10µF 100nF 100nF
When the AD7606B is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin. Figure 50. Internal Reference Driving Multiple AD7606B REFIN/REFOUT Pins
REFIN/REFOUT
OPERATION MODES
SAR
The AD7606B can be operated in hardware or software mode
REFCAPA
BUF by controlling the OSx pins (Pin 3, Pin 4, and Pin 5), described
REFCAPB
10µF in Table 13.

2.5V
In hardware mode, the AD7606B is configured depending on
REF
the logic level on the RANGE, OSx, or STBY pins.
15137-053

In software mode, that is, when all three OSx pins are connected
Figure 48. Reference Circuitry to logic high level, the AD7606B is configured by the corre-
Using Multiple AD7606B Devices sponding registers accessed via the serial or parallel interface.
Additional features are available, as described in Table 14.
For applications using multiple AD7606B devices, the following
configurations are recommended, depending on the application The reference and the data interface is selected using the
requirements. REF SELECT and PAR/SER SEL pins, in both hardware and
software modes.
External Reference Mode
Table 13. Oversampling Pin Decoding
One external reference can drive the REFIN/REFOUT pins of
OSx Pins AD7606B
all AD7606B devices (see Figure 49). In this configuration,
000 No OS
decouple each REFIN/REFOUT pin of the AD7606B with at
least a 100 nF decoupling capacitor. 001 2
010 4
011 8
100 16
101 32
110 64
111 Enters software mode

Rev. A | Page 26 of 72
Data Sheet AD7606B
Table 14. Functionality Matrix
Parameter Hardware Mode Software Mode
Analog Input Range 1 ±10 V or ±5 V 2 ±10 V, ±5 V, or ±2.5 V 3
System Gain, Phase, and Offset Calibration Not accessible Available3
OSR From no OS to OSR = 64 From no OS to OSR = 256
Analog Input Open Circuit Detection Not accessible Available3
Serial Data Output Lines 2 Selectable: 1, 2, or 4
Diagnostics Not accessible Available
Power-Down Modes Standby and shutdown Standby, shutdown, and autostandby
1
See Table 10 for the analog input range selection.
2
Same input range configured in all input channels.
3
On a per channel basis.
Power-Down Modes
Reset Functionality
In hardware mode, two power-down modes are available on the
The AD7606B has two reset modes: full or partial. The reset
AD7606B: standby mode and shutdown mode. The STBY pin
mode selected is dependent on the length of the reset high
controls whether the AD7606B is in normal mode or in one of
pulse. A partial reset requires the RESET pin to be held high
the two power-down modes, as shown in Table 15. If the STBY
between 55 ns and 2 μs. After 50 ns from the release of the
pin is low, the power-down mode is selected by the state of the
RESET pin (tDEVICE_SETUP, partial reset), the device is fully functional
RANGE pin.
and a conversion can be initiated. A full reset requires the
RESET pin to be held high for a minimum of 3 µs. After 253 μs Table 15. Power-Down Mode Selection, Hardware Mode
(tDEVICE_SETUP, full reset) from the release of the RESET pin, the Power Mode STBY Pin RANGE Pin
device is completely reconfigured and a conversion can be Normal Mode 1 X1
initiated. Standby 0 1
A partial reset reinitializes the following modules: Shutdown 0 0
• Digital filter 1
X means don’t care.
• SPI and parallel, resetting to ADC read mode In software mode, the power-down mode is selected through
• SAR ADCs the OPERATION_MODE bits on the CONFIG register
• CRC logic (Address 0x02, Bits[1:0]) within the memory map. There is an
After the partial reset, the RESET_DETECT bit of the status extra power-down mode available in software mode called
register asserts (Address 0x01, Bit 7).The current conversion autostandby mode.
result is discarded after the completion of a partial reset. The Table 16. Power-Down Mode Selection, Software Mode,
partial reset does not affect the register values programmed in Through CONFIG Register (Address 0x02)
software mode or the latches that store the user configuration in
Operation Mode Address 0x02, Bit 1 Address 0x02, Bit 0
both hardware and software modes.
Normal 0 0
A full reset returns the device to the default power-on state, the Standby 0 1
RESET_DETECT bit of the status register asserts (Address 0x01, Autostandby 1 0
Bit 7), and the current conversion result is discarded. The Shutdown 1 1
following features, in addition to those listed previously, are
When the AD7606B is placed in shutdown mode, all circuitry is
configured when the AD7606B is released from full reset:
powered down and the current consumption reduces to 5 µA,
• Hardware mode or software mode maximum. The power-up time is approximately 10 ms. When
• Interface type (serial or parallel) the AD7606B is powered up from shutdown mode, a full reset
must be applied to the AD7606B after the required power-up
time elapses.
When the AD7606B is placed in standby mode, all the PGAs
and all the SAR ADCs enter a low power mode, such that the
overall current consumption reduces to 4.5 mA, maximum. No
reset is required after exiting standby mode.

Rev. A | Page 27 of 72
AD7606B Data Sheet
When the AD7606B is placed in autostandby mode, available CONVST

only in software mode, the device automatically enters standby BUSY

mode on the BUSY signal falling edge. The AD7606B exits
standby mode automatically on the CONVST signal rising edge. POWER MODE STANDBY NORMAL STANDBY

15137-056
Therefore, the CONVST signal low pulse time is longer than tWAKE_UP
tWAKE_UP (standby mode) = 1 μs. Figure 51. Autostandby Mode Operation

Rev. A | Page 28 of 72
Data Sheet AD7606B

DIGITAL FILTER
The AD7606B contains an optional digital averaging filter that averaging of multiple samples leads to an improvement in SNR
can be enabled in slower throughput rate applications that require performance, at the expense of reducing the maximum throughput
higher SNR or dynamic range. rate. When the oversampling function is turned on, the BUSY
In hardware mode, the oversampling ratio of the digital filter is signal high time (tCONV) extends, as shown in Table 3. Table 17
controlled using the oversampling pins, OSx, as shown in Table 13. shows the trade-off in SNR vs. bandwidth and throughput for
The OSx pins are latched on the falling edge of the BUSY signal. the ±10 V, ±5 V, and ±2.5 V ranges.
tCYCLE
In software mode, that is, if all OSx pins are tied to logic high, CONVST
the oversampling ratio is selected through the oversampling OS CLOCK
register (Address 0x08). Two additional oversampling ratios BUSY
(OS × 128 and OS × 256) are available in software mode. tCONV
CS
In oversampling mode, the ADC takes the first sample for each

15137-057
RD
channel on the rising edge of the CONVST signal. After DATA:
DB0 TO DB15
converting the first sample, the subsequent samples are taken by
Figure 52. Oversampling by 8 Example, Read After Conversion, Parallel
the internally generated sampling signal, as shown in Figure 52. Interface, OS Clock Internally Generated Sampling Signal
Alternatively, this sampling signal can be applied externally as
Figure 52 shows that the conversion time (tCONV) extends when
described in the External Oversampling Clock section.
oversampling is turned on. The throughput rate (1/tCYCLE) must be
For example, if oversampling by eight is configured, eight reduced to accommodate the longer conversion time and to allow
samples are taken, averaged, and the result is provided on the the read operation to occur. To achieve the fastest throughput rate
output. A CONVST signal rising edge triggers the first sample, possible when oversampling is turned on, the read can be
and the remaining seven samples are taken with an internally performed during the BUSY signal high time as explained in the
generated sampling signal. Consequently, turning on the Reading During Conversion section.
Table 17. Oversampling Performance
OS Input ±10 V Range ±5 V Range ±2.5 V Range Maximum
Ratio Frequency (Hz) SNR (dB) 3 dB BW (kHz) SNR (dB) 3 dB BW (kHz) SNR (dB) 3 dB BW (kHz) Throughput (kSPS)
No OS 1000 89.5 23.0 88.5 13.9 86 11.6 800
2 1000 91 22.7 89.9 13.8 87.2 11.5 400
4 1000 92.2 22.0 90.8 13.6 88 11.4 200
8 1000 93 20.0 91.5 13.0 88.4 11.1 100
16 1000 93.5 15.4 92 11.4 89 10.0 50
32 130 95.4 9.7 93.7 8.4 90.4 7.7 25
64 130 96.3 5.3 95 5.0 91.8 4.9 12.5
1281 50 97.1 2.7 95.9 2.7 93.3 2.7 6.25
2561 50 97.6 1.4 96.8 1.4 94.7 1.4 3.125
1
Only available in software mode.

Rev. A | Page 29 of 72
AD7606B Data Sheet
PADDING OVERSAMPLING input is sampled at regular time intervals, which is optimum for
As shown in Figure 52, an internally generated clock triggers antialiasing performance.
the samples to be averaged, and then the ADC remains idle To enable the external oversampling clock, Bit 5 in the CONFIG
until the following CONVST signal rising edge. In software register (Address 0x02, Bit 5) must be set. Then, the throughput
mode, through the oversampling register (Address 0x08), the rate is the following:
internal clock (OS clock) frequency can be changed such that idle 1
time is minimized, that is, sampling instants are equally spaced, as Throughput =
tCNVST × OSR
shown in Figure 53.
That is, the sampling signal is provided externally through the
tCYCLE
CONVST
CONVST pin, and every OSR number of clocks, an output is
OS CLOCK
averaged and provided, as shown in Figure 55. This feature is
available using either the parallel interface or the serial interface.

15137-158
BUSY
tCONV
Simultaneous Sampling of Multiple AD7606B Devices
Figure 53. Oversampling by 8 Example, Oversampling Padding Enabled
In general, synchronizing several SAR ADCs can easily be
Table 18. OS_PAD Bit Decoding achieved by using a common CNVST signal. However, when
OS_PAD (Address 0x08, Bits[7:4]) OS Clock Frequency (kHz) oversampling is enabled, an internal clock is used by default to
0000 800 trigger the subsequent samples. Any deviation between these
0001 753 internal clocks may impede device to device synchronization.
0010 711 This deviation can be minimized by using external oversampling
0011 673.5 because the CNVST signal of all the samples are managed
0100 640 externally.
0101 609.5 A partial reset (tRESET < 2 μs) interrupts the oversampling process
0110 582 and empties the data register. Therefore, if by any reason one of
0111 556.5 the AD7606B devices is not in synchrony, issuing a partial reset
1000 533 easily resynchronizes them all, as shown in Figure 54.
1001 512 RESET
1010 492.5
1011 474
1100 457 AD7606B AD7606B AD7606B
BUSY 1 BUSY 2 BUSY 3
1101 441.5
1110 426.5
1111 413
CNVST
CNVST
RESET
EXTERNAL OVERSAMPLING CLOCK BUSY1

15137-155
In software mode, there is an option to apply an external clock BUSY2
BUSY3
through the CONVST pin when oversampling mode is enabled.
Figure 54. Synchronizing Multiple AD7606B Devices with External
Providing a low jitter external clock improves SNR performance Oversampling Clock Enabled
for large oversampling ratios. By applying an external clock, the

tCNVST
CONVST

BUSY

CS

RD
15137-159

DB0 TO DB15

Figure 55. External Oversampling Clock Applied on the CONVST Pin (OSR = 4); Parallel Interface

Rev. A | Page 30 of 72
Data Sheet AD7606B

SYSTEM CALIBRATION FEATURES

The following system calibration features are available in AD7606B
software mode by writing to corresponding registers in the ANALOG RFILTER Vx 5MΩ
INPUT
memory map: SIGNAL C 5MΩ
VxGND
• Phase calibration RFILTER

15137-060
• Gain calibration
• Offset calibration Figure 57. System Gain Error
• Analog input open circuit detection
For example, if a 27 kΩ resistor is placed in series to the analog
SYSTEM PHASE CALIBRATION input of Channel 5, the resistor generates a −170 LSB positive
full-scale error on the system (at ±10 V range), as shown in
When using an external filter, as shown in Figure 57, any
Figure 58. In software mode, this error is eliminated by writing
mismatch on the discrete components, or in the sensor being
27 (decimal) to the CH5_GAIN register (Address 0x0D), which
used, can cause phase mismatch between channels. This phase
mismatch can be compensated for in software mode, on a per keeps the error within 0.01% of FSR, no matter the RFILTER value
channel basis, by delaying the sampling instant on individual of the series resistor, as shown in Figure 59.
channels. 50 0.05
0
0
The sampling instant on any particular channel can be delayed –0.05
–50 –0.10
with regard to the CONVST signal rising edge, with a resolution of –0.15
1.25 μs, and up to 318.75 μs, by writing to the corresponding –100
–0.20

ERROR (% OF FSR)
CHx_PHASE register (Address 0x19 through Address 0x20). ERROR (LSB)
–150 –0.25
–200 –0.30
For example, if the CH4_PHASE register (Address 0x1C) is –0.35
–250
written with 10 (decimal), Channel 4 is effectively sampled –0.40
–0.45
12.5 μs (tPHASE_REG) after the CONVST signal rising edge, as –300
–0.50
shown in Figure 56. –350 –0.55
–400 –0.60
–0.65
–450 ON-CHIP CALIBRATION ENABLE
ON-CHIP CALIBRATION DISABLE
–0.70
INPUT V1
–500 –0.75

15137-162
INPUT V4 0 10 20 30 40 50 60
RFILTER (kΩ)
CONVST
Figure 58. System Gain Calibration with and Without Calibration
INTERNAL
CONVST CH1 tPHASE_REG 25
INTERNAL
CONVST CH4 20 –0.03
tCONV
BUSY
15
–0.02
V1 CODE 10

ERROR (% OF FSR)
V4 CODE –0.01
15137-160

ERROR (LSB)

0 0
Figure 56. System Phase Calibration Functionality
–5
–0.01
The BUSY signal high time equals tCONV plus tPHASE_REG, as shown in
–10
Figure 56. In the previously explained example and Figure 56, if –0.02
–15
only the CH4_PHASE register is programmed, tCONV increases
by 12.5 μs. Therefore, this scenario must be taken into account –20 –0.03

when running at higher throughput rates. –25

15137-163

0 10 20 30 40 50 60
RFILTER (kΩ)
SYSTEM GAIN CALIBRATION
Figure 59. System Error with Gain Calibration Enabled
Using an external RFILTER, as shown in Figure 57, generates a
system gain error. This gain error can be compensated for in
software mode, on a per channel basis, by writing the series
resistor value used on the corresponding register, Address 0x09
through Address 0x10. These registers can compensate up to
65 kΩ series resistors, with a resolution of 1024 Ω.

Rev. A | Page 31 of 72
AD7606B Data Sheet
SYSTEM OFFSET CALIBRATION Manual Mode
A potential offset on the sensor, or any offset caused by a mismatch In manual mode, enabled by writing 0x01 to OPEN_DETECT_
between the RFILTER pair placed on a particular channel (as QUEUE (Address 0x2C), each PGA common-mode voltage is
described in the Analog Front End section), can be compensated controlled by the corresponding CHx_OPEN_DETECT_EN bit
in software mode, on a per channel basis. The CHx_OFFSET on the OPEN_DETECT_ENABLE register (Address 0x23).
registers (Address 0x11 through Address 0x18) allow the ability Setting this bit high shifts up the PGA common-mode voltage.
to add or subtract up to 128 LSB from the ADC code If there is an open circuit on the analog input, the ADC output
automatically, with a resolution of 1 LSB, as shown in Table 19. changes proportionally to the RPD resistor, as shown in Figure 61. If
there is no open circuit, any change on the PGA common-mode
For example, if the signal connected to Channel 3 has a 9 mV
voltage has no effect on the ADC output.
offset, and the analog input range is set to the ±10 V range
120
(where LSB size = 305 μV) to compensate for this offset, 10V
program −30 LSB to the corresponding register. Writing 5V
2.5V
100
128 (decimal) − 30 (decimal) = 0x80 − 0x1E = 0x62 to the

ADC CODE INCREMENT (LSB)

CH3_OFFSET register (Address 0x13) removes such offset.
80

Table 19. CHx_OFFSET Register Bit Decoding

CHx_OFFSET Register Offset Calibration (LSB) 60

0x00 −128
0x45 −59 40

0x80 (Default) 0
0x83 3 20

0xFF 127
0

15137-460
ANALOG INPUT OPEN CIRCUIT DETECTION
0 20 40 60 80 100
RPD (kΩ)

The AD7606B has an analog input open circuit detection Figure 61. Open Circuit Code Error Increment, Dependent of RPD
feature available in software mode. To use this feature, RPD must
be placed as shown in Figure 60. If the analog input is Automatic Mode
disconnected, for example, if a switch opens in Figure 60, the Automatic mode is enabled by writing any value greater than
source impedance changes from the burden resistor (RBURDEN) to 0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C), as
RPD, as long as RBURDEN < RPD. It is recommended to use RPD = shown in Table 20. If the AD7606B detects that the ADC reported a
50 kΩ so that the AD7606B can detect changes in the source number (specified in the OPEN_DETECT_QUEUE register) of
impedance by internally switching the PGA common-mode consecutive unchanged conversions, the analog input open circuit
voltage. Analog input open circuit detection operates in manual detection algorithm is performed internally and automatically.
mode or in automatic mode. The analog input open circuit detection algorithm automatically
changes the PGA common-mode voltage, checks the ADC
AD7606B
RFILTER
Vx+ 5MΩ output, and returns to the initial common-mode voltage, as
CFILTER SAR
shown in Figure 62. If the ADC code changes in any channel
RBURDEN RPD
VxGND
ADC with the PGA common-mode change, this implies that there is
RFILTER 5MΩ no input signal connected to that analog input, and the
15137-061

corresponding flag asserts within the OPEN_DETECTED

Figure 60. Analog Front End with RPD register (Address 0x24). Each channel can be individually
enabled or disabled through the OPEN_DETECT_
ENABLE register (Address 0x23).

Rev. A | Page 32 of 72
Data Sheet AD7606B
START If no oversampling is used, the recommended minimum
CONVERSION
number of conversions to be programmed for the AD7606B to
automatically detect an open circuit on the analog input is
NO OPEN _ DETECT _ QUEUE =
0 < ADC CODE < 350 LSB
10 × f SAMPLE ( RPD + 2 × RFILTER ) × (CFILTER + 10 pF)
i=0

YES
where CFILTER is the capacitor shown in Figure 60.
N = NUMBER OF
NO
i = N? CONSECUTIVE REPEATED However, when oversampling mode is enabled, the
i=i+1 (WITHIN 10 LSB)
ADC OUTPUT CODE recommended minimum number of conversions to use is
YES; SET
COMMON MODE HIGH
OPEN _ DETECT _ QUEUE =

NO
ΔADC CODE > 20 LSB
(
1 + f SAMPLE × 2 ( RPD + 2 × RFILTER ) × (CFILTER + 10 pF) × OSR )
i=0

YES; SET
COMMON MODE LOW

NO ADC CODE BACK

i=0 TO ORIGINAL?

YES
15137-165

ERROR FLAG

Figure 62. Automatic Analog Input Open Circuit Detect Flowchart

Table 20. Analog Input Open Circuit Detect Mode Selection and Register Functionality
OPEN_DETECT_QUEUE
(Address 0x2C) Open Detect Mode OPEN_DETECT_ENABLE (Address 0x23)
0x00 (Default) Disabled Not applicable
0x01 Manual mode Sets common-mode voltage high or low,
on a per channel basis
0x02 to 0xFF Automatic; OPEN_DETECT_QUEUE is the number of consecutive Enables or disables automatic analog input
conversions before asserting any CHx_OPEN flag; the minimum open circuit detection on a per channel basis
value for this register is 5

Rev. A | Page 33 of 72
AD7606B Data Sheet

DIGITAL INTERFACE
The AD7606B provides two interface options: a parallel interface SOFTWARE MODE
and a high speed serial interface. The required interface mode is In software mode, which is active only when all three
selected via the PAR/SER SEL pin. oversampling pins are tied high, both ADC read mode and
Table 21. Interface Mode Selection register mode are available. ADC data can be read from the
AD7606B, and registers can also be read from and written to
PAR/SER SEL Interface Mode
the AD7606B via the parallel data bus with standard CS, RD,
0 Parallel interface mode
and WR signals or via the serial interface with standard CS,
1 Serial interface mode
SCLK, SDI, and DOUTA lines.
Operation of the interface modes is discussed in the following
See the Parallel Register Mode (Writing Register Data) section
sections.
and the Parallel Register Mode (Reading Register Data) section
HARDWARE MODE for more details on how register mode operates.
In hardware mode, only ADC read mode is available. ADC data Pin functions differ depending on the interface selected
can be read from the AD7606B via the parallel data bus with (parallel or serial) and the operation mode (hardware or
standard CS and RD signals or via the serial interface with software), as shown in Table 22 and Table 23.
standard CS, SCLK, and two DOUTx signals.
See the Reading Conversion Results (Parallel ADC Read Mode)
section and the Reading Conversion Results (Serial ADC Read
Mode) section for more details on how ADC read mode
operates.
Table 22. Data Interface Pin Function per Mode of Operation (Parallel Interface)
Software Mode
Pin Name Pin No. Hardware Mode ADC Read Mode Register Mode
DB0 to DB6 16 to 22 DB0 to DB6 Register data
DB7/DOUTA 24 DB7 Register data (MSB)
DB8/DOUTB 25 DB8 ADD0
DB9/DOUTC 27 DB9 ADD1
DB10/DOUTD 28 DB10 ADD2
DB11/SDI 29 DB11 ADD3
DB12 to DB14 30 to 32 DB12 to DB14 ADD4 to ADD6
DB15 33 DB15 R/W

Table 23. Data Interface Pin Function per Mode of Operation (Serial Interface)
Software Mode
Pin Name Pin No. Hardware Mode ADC Read Mode Register Mode
DB0 to DB6 16 to 22 N/A1 N/A N/A
DB7/DOUTA 24 DOUTA DOUTA DOUTA
DB8/DOUTB 25 DOUTB DOUTB2 Unused
DB9/DOUTC 27 N/A DOUTC3 Unused
DB10/DOUTD 28 N/A DOUTD3 Unused
DB11/SDI 29 N/A Unused SDI
DB12 to DB14 30 to 32 N/A N/A N/A
DB15 33 N/A N/A N/A
1
N/A means not applicable. Tie all N/A pins to AGND.
2
Only used if 2 DOUTx or 4 DOUTx mode is selected in the CONFIG register. Otherwise, leave unconnected.
3
Only used if 4 DOUTx mode is selected in the CONFIG register. Otherwise, leave unconnected.

Rev. A | Page 34 of 72
Data Sheet AD7606B
PARALLEL INTERFACE Reading During Conversion
To read ADC data or to read/write the register content over the The data read operation from the AD7606B, as shown in Figure 64,
parallel interface, tie the PAR/SER SEL pin low. can occur in the following three scenarios:
 After conversion, such as when the BUSY line is low
AD7606B
INTERRUPT  During conversion, such as when the BUSY line is high
BUSY 14
 Starts when the BUSY line is low and ends during the
CS 13 following conversion (see the Universal Timing
RD/SCLK 12 Specifications section)
DIGITAL
WR 10 HOST
Reading during conversion has little effect on the performance
DB[33:24] of the converter, and it allows a faster throughput rate to be

15137-166
DB[15:0]
DB[22:16]
achieved. Data can be read from the AD7606B at any time other
Figure 63. AD7606B Interface Diagram—One AD7606B Using the Parallel than on the falling edge of the BUSY signal because this falling
Bus, with CS and RD Shorted Together edge is when the output data registers are updated with the new
conversion data. Any data read while the BUSY signal is high
The rising edge of the CS input signal three-states the bus, and
must be completed before the falling edge of the BUSY signal.
the falling edge of the CS input signal takes the bus out of the
high impedance state. CS is the control signal that enables the Parallel ADC Read Mode with CRC Enabled
data lines and it is the function that allows multiple AD7606B In software mode, the parallel interface supports reading the
devices to share the same parallel data bus. ADC data with the CRC appended, when enabled through the
Reading Conversion Results (Parallel ADC Read Mode) INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is
16 bits, and it is clocked out after reading all eight channel
The falling edge of the RD pin reads data from the output conversions, as shown in Figure 67. The CRC calculation includes
conversion results register. Applying a sequence of RD pulses to all data on the DBx pins: data, status (when appended), and zeros.
the RD pin clocks the conversion results out from each channel See the Diagnostics section for more details on the CRC.
to the parallel bus, Bits[DB15:DB0], in ascending order, from
Parallel ADC Read Mode with Status Enabled
V1 to V8, as shown in Figure 65.
In software mode, the 8-bit status header is enabled (see Table 25)
The CS signal can be permanently tied low, and the RD signal by setting STATUS_HEADER in the CONFIG register (Address
can access the conversion results, as shown in Figure 3. A read 0x02, Bit 6), and each channel then takes two frames of data:
operation of new data can take place after the BUSY signal goes
low (see Figure 2). Alternatively, a read operation of data from  The first frame clocks the ADC data out through DBx.
the previous conversion process can take place while the  The second frame clocks out the status header of the
BUSY pin is high. channel on DB15 to DB8, DB15 being the MSB and DB8
the LSB, while DB7 to DB0 clock out zeros.
When there is only one AD7606B in a system and it does not share
the parallel bus, data can be read using one control signal from the This sequence is shown in Figure 66.Table 25 explains the status
digital host. The CS and RD signals can be tied together, as shown header content and describes each bit.
in Figure 4. In this case, the falling edge of the CS and RD signals Table 24. CH.IDx Bits Decoding in Status Header
bring the data bus out of three-state and clocks out the data. CH.ID2 CH.ID1 CH.ID0 Channel Number
The FRSTDATA output signal indicates when the first channel, 0 0 0 Channel 1 (V1)
V1, is being read back, as shown in Figure 4. When the CS input 0 0 1 Channel 2 (V2)
is high, the FRSTDATA output pin is in three-state. The falling 0 1 0 Channel 3 (V3)
edge of CS takes the FRSTDATA pin out of three-state. The 0 1 1 Channel 4 (V4)
falling edge of the RD signal corresponding to the result of V1 sets 1 0 0 Channel 5 (V5)
the FRSTDATA pin high, indicating that the result from V1 is 1 0 1 Channel 6 (V6)
available on the output data bus. The FRSTDATA pin returns to a 1 1 0 Channel 7 (V7)
logic low following the next falling edge of RD. 1 1 1 Channel 8 (V8)
Table 25. Status Header, Parallel Interface
Bit Details Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Bit Name RESET_DETECT DIGITAL_ERROR OPEN_DETECTED AIN_OV_DIAG_ERR AIN_UV_DIAG_ERR CH.ID2 CH.ID1 CH.ID0
Bit Description Reset detected Error flag on The analog input Overvoltage Undervoltage Channel ID (see Table 24)
Address 0x22 of this channel is detected on this detected on this
open channel channel
1
See the Diagnostics section for more information.

Rev. A | Page 35 of 72
AD7606B Data Sheet
CONVST
tACQ_B tACQ_C
BUSY
tCONV_A tCONV_B

15137-266
DOUTx
DBx ADC DATAA ADC DATAB

Figure 64. ADC Data Read After Conversion and/or During Conversion
CONVST

BUSY

CS
RD

15137-167
DB0 TO DB15 V1 V2 V3 V4 V5 V6 V7 V8

FRSTDATA

Figure 65. Parallel Interface, ADC Read Mode

CONVST

BUSY

CS
RD
DB8 TO V1[15:8] STATUS_CH1 V2[15:8] STATUS_CH2 V7[15:8] STATUS_CH7 V8[15:8] STATUS_CH8

15137-168
DB15
DB0 TO V1[7:0] V2[7:0] V7[7:0] V8[7:0]
DB7

Figure 66. Parallel Interface, ADC Read Mode with Status Header Enabled
CONVST

BUSY

CS

15137-169
RD
DB0 TO V1 V2 V3 V4 V5 V6 V7 V8 CRC
DB15

Figure 67. Parallel Interface, ADC Read Mode with CRC Enabled

Parallel Register Mode (Reading Register Data) To revert to ADC read mode, write to Address 0x00, as shown
In software mode, all the registers in Table 32 can be read over in the Parallel Register Mode (Writing Register Data) section.
the parallel interface. Bits[DB15:DB0] leave a high impedance No ADC data can be read while the device is in register mode.
state when both the CS signal and RD signal are logic low for Parallel Register Mode (Writing Register Data)
reading register content, or when both the CS signal and WR signal In software mode, all the R/W registers in Table 32 can be
are logic low for writing register address and/or register content. written to over the parallel interface. To write a sequence of
A register read is performed through two frames: first, a read registers, exit ADC read mode (default mode) by reading any
command is sent to the AD7606B and second, the AD7606B clocks register on the memory map. A register write command is
out the register content. The format for a register read command is performed by a single frame, via the parallel bus (Bits[DB15:DB0]),
shown in Figure 68. On the first frame, the following occurs: CS signal, and WR signal. The format for a write command is
shown in Figure 68. The format of a write command, as shown
 Bit DB15 must be set to 1 to select a read command. The
in Figure 68, is structured as follows:
read command places the AD7606B in register mode.
 Bits[DB14:DB8] must contain the register address.  Bit DB15 must be set to 0 to select a write command.
 The subsequent eight bits, Bits[DB7:DB0], are ignored.  Bits[DB14:DB8] contain the register address.
 The subsequent eight bits, Bits[DB7:DB0], contain the data
The register address is latched on the AD7606B on the rising
to be written to the selected register.
edge of the WR signal. The register content can then be read
from the latched register by bringing the RD line low on the Data is latched onto the device on the rising edge of the WR
following frame, as follows: pin. To revert to ADC read mode, write to Address 0x00. No
ADC data can be read while the device is in register mode.
 Bit DB15 is pulled to 0 by the AD7606B.
 Bits[DB14:DB8] provide the register address being read.
 The subsequent eight bits, Bits[DB7:DB0], provide the
register content.

Rev. A | Page 36 of 72
Data Sheet AD7606B
CS

RD

WR

DB15 R/W = 1 R/W = 0 R/W = 0 R/W = 0

DB8 TO REG. ADDRESS REG. ADDRESS REG. ADDRESS ADDRESS = 0x00

DB14
DB0 TO DON’T CARE REGISTER DATA REGISTER DATA DON’T CARE
DB7

15137-170
MODE ADC READ MODE REGISTER MODE ADC READ MODE

Figure 68. Parallel Interface Register Read Operation, Followed by a Write Operation
CS

FRSTDATA

SCLK

DOUTA V1 V2 V3 V4 V5 V6 V7 V8

DOUTB

DOUTC

15137-171
DOUTD

Figure 69. Serial Interface ADC Reading, One DOUTx Line

SERIAL INTERFACE In hardware mode, only the 2 DOUTx lines option is available.
To read ADC data or to read/write the registers content over the However, all channels can be read from DOUTA by providing
serial interface, tie the PAR/SER SEL pin high. eight 16-bit SPI frames between two CONVST pulses.
CNVST
AD7606B
INTERRUPT
BUSY 14
CS
CS 13
SCLK
RD/SCLK 12
DOUTA V1 V2 V3 V4
DB11/SDI 29
DOUTB V5 V6 V7 V8
DB7/DOUTA 24 DIGITAL
HOST DOUTC

15137-173
DB8/DOUTB 25
DOUTD
DB9/DOUTC 27
Figure 71. Serial Interface ADC Reading, Two DOUTx Lines
15137-172

DB10/D OUTD 28

CS
Figure 70. AD7606B Interface Diagram—One AD7606B Using the Serial
Interface with Four DOUTx Lines SCLK

Reading Conversion Results (Serial ADC Read Mode) DOUTA V1 V2

The AD7606B has four serial data output lines: DOUTA, DOUTB, DOUTB V3 V4
DOUTC, and DOUTD. In software mode, data can be read back
from the AD7606B using either one (see Figure 70), two (see DOUTC V5 V6
15137-174

Figure 71), or four DOUTx lines (see Figure 72), depending on the DOUTD V7 V8
configuration set in the CONFIG register.
Figure 72. Serial Interface ADC Reading, Four DOUTx Lines
Table 26. DOUTx Format Selection, Using the CONFIG The CS falling edge takes the data output lines, DOUTA to DOUTD,
Register (Address 0x02) out of three-state and clocks out the MSB of the conversion result.
DOUTx Format Address 0x02, Bit 4 Address 0x02, Bit 3
1 DOUTx 0 0
In 3-wire mode (CS tied low), instead of CS clocking out the MSB,
2 DOUTx 0 1 the falling edge of the BUSY signal clocks out the MSB. The rising
4 DOUTx 1 0 edge of the SCLK signal clocks all the subsequent data bits on the
1 DOUTx 1 1 serial data outputs, DOUTA to DOUTD, as shown in Figure 6. The CS
input can be held low for the entire serial read operation, or it can
be pulsed to frame each channel read of 16 SCLK cycles (see

Rev. A | Page 37 of 72
AD7606B Data Sheet
Figure 71). However, if CS is pulsed during a channel If SDI is tied low or high, nothing is clocked to the AD7606B.
conversion result transmission, the channel that was interrupted Therefore, the device remains clocking out conversion results.
retransmits on the next frame, completely starting from the MSB. When using the AD7606B in 3-wire mode, keep SDI at a high
level. While in ADC read mode, single-write operations can be
Data can also be clocked out using only the DOUTA line, as
performed, as shown in Figure 73. For writing a sequence of
shown in Figure 69. For the AD7606B to access all eight
registers, switch to register mode, as described in the Serial
conversion results on one DOUTx line, a total of 128 SCLK cycles
Register Mode (Writing Register Data) section.
is required. In hardware mode, these 128 SCLK cycles must be
framed in groups of 16 SCLK cycles by the CS signal. The Reading During Conversion—Serial Interface
disadvantage of using just one DOUTx line is that the throughput The data read operation from the AD7606B, as shown in Figure 64,
rate is reduced if reading occurs after conversion. Leave the unused occurs in the following three scenarios:
DOUTx lines unconnected in serial mode.
• After conversion, such as when the BUSY line is low
Figure 72 shows a read of eight simultaneous conversion results • During conversion, such as when the BUSY line is high
using four DOUTx lines on the AD7606B, available in software • Starts when the BUSY is low and ends during the following
mode. In this case, a 32 SCLK transfer accesses data from the conversion (see the Universal Timing Specifications section)
AD7606B, and CS is either held low to frame the entire 32 SCLK
cycles or is pulsed between two 16-bit frames. This mode is only Reading during conversion has little effect on the performance
available in software mode, and it is configured using the of the converter, and it allows a faster throughput rate to be
CONFIG register (Address 0x02). achieved. Data can be read from the AD7606B at any time other
than on the falling edge of the BUSY signal because this falling
Figure 6 shows the timing diagram for reading one channel of
edge is when the output data registers are updated with the new
data, framed by the CS signal, from the AD7606B in serial conversion data. Any data read while the BUSY signal is high
mode. The SCLK input signal provides the clock source for the must be completed before the falling edge of the BUSY signal.
serial read operation. The CS signal goes low to access the data
Serial ADC Read Mode, with CRC Enabled
from the AD7606B.
In software mode, the CRC can be enabled by writing to the
The FRSTDATA output signal indicates when the first channel,
register map. In this case, the CRC is appended on each DOUTx
V1, is being read back. When the CS input is high, the FRSTDATA
line after the last channel is clocked out, as shown in Figure 80.
output pin is in three-state. In serial mode, the falling edge of the
See the Interface CRC Checksum section for more information
CS signal takes the FRSTDATA pin out of three-state and sets
on how the CRC is calculated.
the FRSTDATA pin high if the BUSY line is already deasserted,
indicating that the result from V1 is available on the DOUTA Serial ADC Read Mode, with Status Enabled
output data line. The FRSTDATA output returns to a logic low In software mode, the 8-bit status header can be turned on
following the 16th SCLK falling edge. If the CS pin is tied when using the serial interface so that it is appended after each
permanently low (3-wire mode), the falling edge of the BUSY 16-bit data conversion, extending the frame size to 24 bits per
line sets the FRSTDATA pin high when the result from V1 is channel, as shown in Figure 73.
available on DOUTA.

CS

SCLK 1 2 3 4 5 6 7 8 9 16 24
15137-175

DOUTx ADC DATA STATUS HEADER

Figure 73. Serial Interface, ADC Read Mode, Status On

Rev. A | Page 38 of 72
Data Sheet AD7606B
CS

SCLK

READ COMMAND R/W COMMAND R/W COMMAND WRITE COMMAND

REGISTER REGISTER REGISTER ADDRESS

SDI N N+1 N+2 0x00

REGISTER REGISTER REGISTER

DOUTA ADC DATA ADC DATA N N+1 N+2 ADC DATA

DOUTB TO
ADC DATA ADC DATA ADC DATA
DOUTD

15137-176
MODE ADC MODE REGISTER MODE ADC MODE

Figure 74. AD7606B Register Mode

Table 27. Status Header, Serial Interface

Bit Details Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Bit Name RESET_DETECT DIGITAL_ERROR OPEN_DETECTED AIN_OV_DIAG_ERR AIN_UV_DIAG_ERR CH.ID 2 CH.ID 1 CH.ID 0
Bit Description 1 Reset detected Error flag on At least one analog Overvoltage Undervoltage Channel ID (see Table 24)
Address 0x22 input is open detected on a detected on a
on a channel channel channel

1
See the Diagnostics section for more information.

Serial Register Mode (Reading Register Data) The format for a write command, as shown in Figure 76, is
All the registers in Table 32 can be read over the serial interface. structured as follows:
The format for a read command is shown in Figure 75. A read • The first bit in SDI must be set to 0 to enable a write
command consists of two 16-bit frames. On the first frame, command.
• The first bit in SDI must be set to 0 to enable writing the • The second bit, the R/W bit, must be cleared to 0.
address. • Bits[ADD5:ADD0] contain the register address to be
• The second bit must be set to 1 to select a read command. written.
• Bits[3:8] in SDI contain the register address to be clocked out • The subsequent eight bits (Bits[DIN7:DIN0]) contain the
on DOUTA on the following frame. data to be written to the selected register. Data is clocked in
• The subsequent eight bits, Bits[9:16], in SDI are ignored. from SDI on the falling edge of SCLK, while data is clocked
out on DOUTA on the rising edge of SCLK.
If the AD7606B is in ADC read mode, the SDO keeps clocking
ADC data on Bits[9:16], and then the AD7606B switches to When writing continuously to the device, the data that appears
register mode. on DOUTA is from the register address that was written to on the
previous frame, as shown in Figure 76. The DOUTB, DOUTC, and
If the AD7606B is in register mode, the SDO reads back the
DOUTD lines are kept low during the transmission.
content from the previous addressed register, no matter if the
previous frame was a read or a write command. To exit register While in register mode, no ADC data is clocked out because the
mode, a write to Address 0x00 is required, as shown in Figure 74. DOUTx lines are used to clock out register content. When finished
writing all needed registers, a write to Address 0x00 returns the
Serial Register Mode (Writing Register Data)
AD7606B to ADC read mode, where the ADC data is again
In software mode, all the read/write registers in Table 32 can be clocked out on the DOUTx lines, as shown in Figure 74.
written to the serial interface. To write a sequence of registers,
In software mode, when the CRC is turned on, eight additional
exit ADC read mode (default mode) by reading any register on
bits are clocked in and out on each frame. Therefore, 24-bit
the memory map. A register write command is performed by a
frames are needed.
single 16-bit SPI access. The format for a write command is
shown in Figure 76.

Rev. A | Page 39 of 72
AD7606B Data Sheet
CS

SCLK
1 8 16

SDI
WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 READ OR WRITE COMMAND

DOUTA

15137-073
ADC DATA (8LSB) OR PREVIOUS
ADC DATA (8LSB) OR XX REGISTER READ/WRITTEN REGISTER [ADD5:ADD0] CONTENT

Figure 75. Serial Interface Read Command; First Frame Points the Address; Second Frame Provides the Register Content
CS

SCLK 1 8 9 16

SDI WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DIN71 DIN61 DIN51 DIN41 DIN31 DIN21 DIN11 DIN01

DOUTA DATA OUT2

15137-074
1DATA IN DINx IS WRITTEN INTO REGISTER ADDRESS [ADD5:ADD0]
2DATA OUT IS THE REGISTER CONTENT OF PREVIOUS REGISTER WRITTEN

Figure 76. Serial Interface, Single-Write Command; SDI Clocks in the Address [ADD5:ADD0] and the Register Content [DINx] During the Same Frame, DOUTA Provides
Register Content Requested on the Previous Frame

CS

1 8 9 16 24
SCLK

SDI WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

15137-179
MSB LSB 8-BIT CRC
DOUTA

Figure 77. Reading Registers Through the SPI Interface with CRC Enabled

CS

1 8 9 16 24
SCLK

15137-180
SDI WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 MSB LSB 8-BIT CRC

Figure 78. Writing Registers Through the SPI Interface with CRC Enabled

Serial Register Mode with CRC With the CRC enabled, the SPI frames extend to 24 bits in
Registers can be written to and read from the AD7606B with length, as shown in Figure 77.
CRC enabled in software mode, by asserting the INT_CRC_ When writing a register, the controller must clock the data
ERR_EN bit (Address 0x21, Bit 2). (register address plus register content) in the AD7606B followed by
When reading a register, the AD7606B provides eight additional an 8-bit CRC word, calculated from the previous 16 bits using
bits on the DOUTA line with the CRC resultant of the data shifted the previously described polynomial. The AD7606B reads the
out previously on the same frame. The controller can then register address and the register content, calculates the
check whether the data received is correct by applying the corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit
following polynomial: (Address 0x22, Bit 2) if the calculated CRC word does not match
the CRC word received between the 17th and 24th bit through
x8 + x2 + x + 1
SDI, as shown in Figure 78.

Rev. A | Page 40 of 72
Data Sheet AD7606B

DIAGNOSTICS
Diagnostic features are available in software mode to verify When the voltage on any analog input pin goes below the
correct operation of the AD7606B. The list of diagnostic undervoltage threshold shown in Table 28, the AIN_UV_
monitors includes reset detection, overvoltage detection, DIAG_ERROR register (Address 0x27) shows which channel or
undervoltage detection, analog input open circuit detection, channels have an undervoltage event. When a bit within the
and digital error detection. AIN_UV_DIAG_ERROR register asserts, it stays at a high state
If an error is detected, a flag asserts on the status header, if after the undervoltage event disappears. To clear the error bit, the
enabled, as described in the Digital Interface section. This flag error bit must be overwritten to 1 or the error checker must be
points to the registers on which the error is located, as explained disabled.
in the following sections. Table 28. Overvoltage and Undervoltage Thresholds
In addition, a diagnostic multiplexer can dedicate any channel Analog Input Overvoltage Undervoltage
to verify a series of internal nodes, as explained in the Range (V) Threshold (V) Threshold (V)
Diagnostics Multiplexer section. ±2.5 +6.5 −3
±5 +8 −5.5
RESET DETECTION
±10 +12 −11
The RESET_DETECT bit on the status register (Address 0x01,
Bit 7) asserts if either a partial reset or full reset pulse is applied DIGITAL ERROR
to the AD7606B. On power-up, a full reset is required. This Both the status register and status header contain a
reset asserts the RESET_DETECT bit, indicating that the DIGITAL_ERROR bit. This bit asserts when any of the
power-on reset (POR) initialized correctly on the device. following monitors trigger:
The POR monitors the REGCAP voltage and issues a full reset  Memory map CRC, read only memory (ROM) CRC, and
if the voltage drops under a certain threshold. digital interface CRC
The RESET_DETECT bit can be used to detect an unexpected  SPI invalid read or write
device reset or a large glitch on the RESET pin, or a voltage  BUSY stuck high
drop on the supplies. To find out which monitor triggered the DIGITAL_ERROR bit,
The RESET_DETECT bit is only cleared by reading the status the DIGITAL_DIAG_ERR address (Address 0x22) has a bit
register. dedicated for each monitor, as explained in the following sections.
OVERVOLTAGE AND UNDERVOLTAGE EVENTS ROM CRC
The AD7606B includes on-chip overvoltage and undervoltage The ROM stores the factory trimming settings for the AD7606B.
circuitry on each analog input pin. These comparators can be After power-up, the ROM content is loaded to registers during
enabled or disabled using the AIN_OV_UV_DIAG_ device initialization. After the load, a CRC is calculated on the
ENABLE register (Address 0x25). loaded data and verified if the result matches the CRC stored in the
ROM. If an error is found, the ROM_CRC_ERR (Address 0x22,
After this register is enabled, when the voltage on any analog
Bit 0) asserts. When ROM_CRC_ERR asserts after power-up, it
input pin goes above the overvoltage threshold shown in Table 28,
is recommended to issue a full reset to reload all factory settings.
the AIN_OV_DIAG_ERROR register (Address 0x26) shows
which channel or channels have an overvoltage event. When a This ROM CRC monitoring feature is enabled by default, but
bit within the AIN_OV_DIAG_ERROR register asserts, it stays can be disabled by clearing the ROM_CRC_ERR_EN bit
at a high state even after the overvoltage event disappears. To (Address 0x21, Bit 0).
clear the error bit, the error bit must be overwritten to 1 or the Memory Map CRC
error checker must be disabled.
For added robustness, a CRC calculation is performed on the
AD7606B on-chip registers. The memory map CRC is disabled by default.
OVERVOLTAGE
THRESHOLD After the AD7606B is configured in software mode through
CHx_OV_ERR writing the required registers, the memory map CRC can be
SETS IF Vx > OV
enabled through the MM_CRC_ERR_EN bit (Address 0x21,
Vx
Bit 1). When enabled, the CRC calculation is performed on the
entire memory map and stored. Every 4 μs, the CRC on the
CHx_UV_ERR memory map is recalculated and compared to the stored CRC
SETS IF Vx < UV
value. If the calculated and the stored CRC values do not match,
15137-075

UNDERVOLTAGE
THRESHOLD the memory map is corrupted and the MM_CRC_ERR bit asserts.
Figure 79. Overvoltage and Undervoltage Circuitry on Each Analog Input Every time the memory map is written, the CRC is recalculated
and the new value stored.
Rev. A | Page 41 of 72
AD7606B Data Sheet
The error checking and correction (ECC) block can detect up to leftmost Logic 1 of the data. An exclusive OR (XOR) function is
three bits of errors (Hamming distance of four bits) within the applied to the data to produce a new, shorter number. The
memory map. Moreover, every 4 μs, the CRC on the memory polynomial is again aligned so that the MSB is adjacent to the
map is recalculated and compared to the stored CRC value. If leftmost Logic 1 of the new result, and the procedure repeats.
the calculated and the stored CRC values do not match, the This process repeats until the original data is reduced to a value
memory map is corrupted and the MM_CRC_ERR bit asserts. less than the polynomial, the 16-bit checksum.
The AD7606B uses the following 16-bit CRC polynomial to An example of the CRC calculation for the 16-bit data is shown
calculate the CRC checksum value on the memory map: in Table 30. The CRC corresponding to the data 0x064E, using
0xBAAD = x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1 the previously described polynomial, is 0x2137.
Every time the memory map is written, the CRC is recalculated The serial interface supports the CRC when enabled via the
and the new value stored. INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a 16-bit
If the MM_CRC_ERR bit asserts, it is recommended to write to word that is appended to the end of each DOUTx in use, after
the memory map to recalculate the CRC. If the error persists, it reading all the channels. An example using four DOUTx lines is
is recommended to issue a full reset to restore the default shown in Figure 80.
contents of the memory map. CNVST

If the MM_CRC_ERR bit asserts, it is recommended to write to CS

the memory map to recalculate the CRC. If the error persists, it

SCLK
is recommended to issue a full reset to restore the default
contents of the memory map. DOUTA V1 V2 CRC(V1,V2)

Interface CRC Checksum DOUTB V3 V4 CRC(V3,V4)

The AD7606B has a CRC checksum mode to improve interface

DOUTC V5 V6 CRC(V5,V6)
robustness by detecting errors in data transmission. The CRC

15137-076
feature is available in both ADC read modes (serial and DOUTD V7 V8 CRC(V7,V8)
parallel) and register mode (serial only).
Figure 80. Serial Interface ADC Reading with CRC On, Four DOUTx Lines
The AD7606B uses the following 8-bit CRC polynomial to
If using two DOUTx lines (DOUTA and DOUTB), each 16-bit CRC
calculate the CRC checksum value:
word is calculated using data from four channels, that is 64 bits,
0xBAAD = x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x + 1 as shown in Figure 81. If using only one DOUTx line, all eight
To replicate the polynomial division in hardware, the data shifts channels are clocked out through DOUTA, followed by the 16-bit
left by 16 bits to create a number ending in 16 Logic 0s. The CRC word calculated using data from the eight channels, that is,
polynomial is aligned so that the MSB is adjacent to the 128 bits.
CNVST

CS

SCLK

DOUTA V1 V2 V3 V4 CRC(V1,V4)

DOUTB V5 V6 V7 V8 CRC(V5,V8)

DOUTC
15137-077

DOUTD

Figure 81. Serial Interface ADC Reading with CRC On, Two DOUTx Lines

Rev. A | Page 42 of 72
Data Sheet AD7606B
When the AD7606B is in register mode, that is, when registers Table 29. Interface Check Conversion Results
are being read or written, the CRC polynomial used is x8 + x2 + Channel Number Conversion Result Forced (Hexadecimal)
x + 1. When reading a register, and CRC is enabled, each SPI V1 0xACCA
frame is 24 bits long and the CRC 8-bit word is clocked out V2 0x5CC5
from the 17th to 24th SCLK cycle. Similarly, when writing a V3 0xA33A
register, a CRC word can be appended on the SDI line, as shown V4 0x5335
in Figure 82 and the AD7606B checks and triggers an error, V5 0xCAAC
INT_CRC_ERR (Address 0x22, Bit 2), if the CRC given and the V6 0xC55C
internally calculated do not match. V7 0x3AA3
The parallel interface also supports CRC in ADC mode only, V8 0x3553
and it is clocked out through DB15 to DB0 after Channel 8, as SPI Invalid Read/Write
shown in Figure 67. The 16-bit CRC word calculated using data
When attempting to read back an invalid register address, the
from the eight channels, that is, 128 bits.
SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid
Interface Check readback address detection can be enabled by setting the
The integrity of the digital interface can be checked by setting SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read
the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7). error is triggered, it is cleared by overwriting that bit or disabling
Selecting the interface check forces the conversion result the checker.
registers to a known value, as shown in Table 29. When attempting to write to an invalid register address or a
Verifying that the controller receives the data shown in Table 29 read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3) is
ensures that the interface between the AD7606B and the set. The invalid write address detection can be enabled by
controller operates properly. If the interface CRC is enabled setting the SPI_WRITE _ERR bit (Address 0x21, Bit 3). If an SPI
because the data transmitted is known, this mode verifies that write error is triggered, it is cleared by overwriting that bit or
the controller performs the CRC calculation properly. disabling the checker.
CS

SCLK 1 2 3 4 15 16 17 24

DOUTA TO DOUTD DB15 DB14 DB13 DB12 DB1 DB0 CRC7 CRC0

15137-078
SDI WEN R/W ADD5 ADD4 DIN1 DIN0 CRC7 CRC0

Figure 82. Register Write with CRC On

Table 30. Example CRC Calculation for 16-Bit Data 1

Data 2 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 X X X X X X X X X X X X X X X X
Process 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data
Polynomial 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
CRC 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1

1
Table 30 represents the division of the data. Blank cells are for formatting purposes.
2
X means don’t care.

Rev. A | Page 43 of 72
AD7606B Data Sheet
BUSY Stuck High Each diagnostic multiplexer configuration is accessed, in
BUSY stuck high monitoring is enabled by setting the software mode through the corresponding register (Address 0x28
BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5). to Address 0x2B). To use the multiplexer on one channel, the
After this bit is enabled, the conversion time (tCONV in Table 3) is ±10 V range must be selected on that channel.
monitored internally with an independent clock. If tCONV exceeds Table 31. Diagnostic Mux Register Bit Decoding of Channel 1
4 μs, the AD7606B automatically issues a partial reset and asserts Address 0x28
the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5). To
Bit 2 Bit 1 Bit 0 Signal on Channel 1
clear this error flag, the BUSY_STUCK_HIGH_ERR bit must be
0 0 0 V1
overwritten with a 1.
0 0 1 Temperature sensor
When oversampling mode is enabled, the individual conversion 0 1 0 4 × VREF
time for each internal conversion is monitored. 0 1 1 4 × ALDO
Internal Clock Counters 1 0 0 4 × DLDO
1 0 1 VDRIVE
The AD7606B uses an internal clock related to functional safety
1 1 0 AGND
features (FS_CLK) as well an internal clock for oversampling
1 1 1 AVCC
(OS_CLK). Both internal clocks run at 16 MHz. To verify the
clocks are correctly operating, enable the clock counter through
the CLK_FS_OS_COUNTER_EN bit in Register 0x21, Bit 6. These TEMPERATURE
AD7606B
SENSOR
clock counters increment by 1 every time 64 clocks are counted. 4 × VREF

Thus, if either the FS_CLK_COUNTER register (Address 0x2D) or 4 × ALDO

4 × DLDO
the OS_CLK_COUNTER register (Address 0x2E) are read after VDRIVE
MUX

AGND
a certain known delay that corresponds to the chosen feature, AVCC
5MΩ
RFB
the register values must match the equivalent count for the time
elapsed. V1
V1GND
For example, if the clock counter is enabled and the 5MΩ RFB
FS_CLK_COUNTER register is read after 20 µs between the
write and read operations, the value must equal to 0x05. The
following equation calculates the FS_CLK_COUNTER value:

15137-079
16MHz
FS _ CLK _ COUNTER = Delay × Figure 83. Diagnostic Multiplexer (Channel 1 Shown as an Example)
64
where Delay is the delay shown in Figure 84. Temperature Sensor
The temperature sensor can be selected through the diagnostic
DIAGNOSTICS MULTIPLEXER
multiplexer and converted with the ADC, as shown in Figure 83.
All eight input channels contain a diagnostics multiplexer in The temperature sensor voltage is measured and is proportional to
front of the PGA that allows monitoring of the internal nodes the die temperature, as per the following equation:
described in Table 31 to ensure the correct operation of the
ADCOUT ( V ) − 0.69068 ( V )
AD7606B. Table 31 shows the bit decoding for the diagnostic mux Temperature ( °C )
= + 25 ( °C )
register on Channel 1, as an example. When an internal node is 0.019328 ( V/°C )
selected, the input voltage at input pins are deselected from the
PGA, as shown in Figure 83.

CS

FS_SCLK

SDI CLK_FS_OS_COUNTER_EN

DELAY
15137-182

DOUTA FS_CLK_COUNTER

Figure 84. FS_CLK_COUNTER Functionality

Rev. A | Page 44 of 72
Data Sheet AD7606B
Reference Voltage Internal LDOs
The reference voltage can be selected through the diagnostic The analog and digital LDO (REGCAP pins) can be selected
multiplexer and converted with the ADC, as shown in Figure 85. through the diagnostic multiplexer and converted with the
The internal or external reference is selected as the input to the ADC, as shown in Figure 83. The ADC output is four times the
diagnostic multiplexer based on the REF SELECT pin. Ideally, voltage on the REGCAPA and REGCAPD pins for the ALDO
the ADC output follows the voltage reference level and DLDO, respectively. This measurement verifies that each
ratiometrically. Therefore, if the ADC output goes beyond the LDO is at the correct operating voltage so that the internal
expected 2.5 V, either the reference buffer or the PGA is circuitry is biased correctly.
malfunctioning. Supply Voltages
AD7606B AVCC, VDRIVE, and AGND can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 83.
This setup ensures the voltage and grounds are applied to the
INT REF
4.4V device for correct operation.

EXT REF
2.5V

MUX RFB
5MΩ

Vx RFB
ADC
VxGND 5MΩ
15137-080

RFB

Figure 85. Reference Voltage Signal Path Through the Diagnostic Multiplexer

Rev. A | Page 45 of 72
AD7606B Data Sheet

TYPICAL CONNECTION DIAGRAM

There are four AVCC supply pins on the device. It is recommended parallel interface because the PAR/SER SEL pin is tied to
that each of the four pins is decoupled using a 100 nF capacitor at AGND. The analog input range for all eight channels is ±10 V,
each supply pin and a 10 µF capacitor at the supply source. The provided the RANGE pin is tied to a high level and the
AD7606B can operate with the internal reference or an externally oversampling ratio is controlled through the OSx pins by the
applied reference. When using a single AD7606B device on the controller.
board, decouple the REFIN/REFOUT pin with a 100 nF capacitor.
In Figure 87, the AD7606B is configured in software mode,
Refer to the Reference section when using an application with
because all three OS2, OS1, and OS0 pins are at logic level high.
multiple AD7606B devices. The REFCAPA and REFCAPB pins
The oversampling ratio, as well as each channel range, are
are shorted together and decoupled with a 10 µF ceramic capacitor.
configured through accessing the memory map. In this example,
The VDRIVE supply is connected to the same supply as the the PAR/SER SEL pin is at logic level high. Therefore, the serial
processor. The VDRIVE voltage controls the voltage value of the interface is used for both reading the ADC data and reading
output logic signals. For more information on layout, decoupling, and writing the memory map. The REF SELECT pin is tied to
and grounding, see the Layout Guidelines section. AGND. Therefore, the internal reference is disabled and an
After supplies are applied to the AD7606B, apply a reset to the external reference is connected externally to the REFIN/REFOUT
AD7606B to ensure that it is configured for the correct mode of pin and decoupled through a 100 nF capacitor.
operation. Figure 86 and Figure 87 are examples of typical connection
In Figure 86, the AD7606B is configured in hardware mode and is diagrams. Other combinations of reference, data interface, and
operating with the internal reference because the REF SELECT pin operation mode are also possible, depending on the logic levels
is set to logic high. In this example, the device also uses the applied to each configuration pin.
ANALOG SUPPLY DIGITAL SUPPLY
VOLTAGE 5V1 VOLTAGE +1.71V TO +3.6V

+
100nF 1µF 100nF 100nF

REFIN/REFOUT REGCAP2 AVCC VDRIVE

REFCAPA

MICROPROCESSOR/
MICROCONVERTER/
PARALLEL
DB0 TO DB15 INTERFACE
10µF + REFCAPB

DSP
REFGND CONVST
V1 CS
V1GND
RD
V2
BUSY
V2GND
V3 RESET
V3GND
AD7606B
OS2
V4
EIGHT ANALOG OS1 OVERSAMPLING
INPUTS V1 TO V8 V4GND
V5 OS0
V5GND REF SELECT VDRIVE
V6
PAR/SER SEL
V6GND
V7 RANGE
VDRIVE
V7GND STBY
V8
V8GND AGND

1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
15137-081

DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38.

2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 86. AD7606B Typical Connection Diagram, Hardware Mode

Rev. A | Page 46 of 72
Data Sheet AD7606B
ANALOG SUPPLY DIGITAL SUPPLY
VOLTAGE 5V1 VOLTAGE +1.71V TO +3.6V

REF
+
100nF 1µF 100nF 100nF

REFIN/REFOUT REGCAP2 AVCC VDRIVE

REFCAPA

MICROPROCESSOR/
MICROCONVERTER/
DB0 TO DB15
+ REFCAPB
10µF
REFGND

DSP
CONVST
V1 CS
V1GND SDI
V2 DOUTx
V2GND SCLK
V3 RESET
V3GND AD7606B
OS2
V4
EIGHT ANALOG OS1 OVERSAMPLING =
INPUTS V1 TO V8 V4GND 111b
V5 OS0
V5GND REF SELECT
V6
V6GND PAR/SER SEL
V7
RANGE VDRIVE
V7GND
V8 STBY
V8GND
AGND

1DECOUPLING

15137-082
SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AVCC PIN 37 AND PIN 38.
2DECOUPLINGSHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 87. Typical Connection Diagram, Software Mode

Rev. A | Page 47 of 72
AD7606B Data Sheet

APPLICATIONS INFORMATION
The fully integrated, 16-bit data acquisition system (DAS) of the sensor interface to current transformers and power
AD7606B enables simultaneous, high precision measurement of up transformers, as shown in Figure 88, without requiring external
to eight analog channels without requiring additional active ADC driver circuits and to accommodate ±10 V, ±5 V, or
circuits. ±2.5 V.
The AD7606B is suitable for power monitoring applications. Although transformers provide isolation from the power lines
Measure the electrical variables accurately on a power line for being monitored, place a series resistor in series to the analog
information about the operating status of the grid. Monitor the input to prevent input currents beyond the absolute maximum
voltage and current amplitude, frequency, and phase to detect ratings (see Table 6). On power line protection applications
anomalies and faults to prevent major disruptions on the where overvoltages occur, the internal ±21V clamp protects
electrical service and to enable power quality analysis, power against damage and performance impacts on adjacent channels.
factor calculation, harmonic analysis (among other applications). In case there are analog input channels beyond these limits,
Each channel contains analog input clamp protection, a PGA, a users are recommended to use external transient voltage
low-pass filter, and a 16-bit SAR ADC. The analog input suppressors (TVS) diodes.
impedance of the AD7606B is typically 5 MΩ to allow a direct
NEUTRAL
PHASE A

PHASE B

PHASE C

AV CC REGCAP AVCC REGCAP VDRIVE

ALDO AD7606B DLDO

IAP V1 5MΩ
CLAMP
V1GND 5MΩ PGA SAR
RPD CLAMP LPF CLK OSC
IAN
CONVST
VAP V2 5MΩ RESET
CLAMP CONTROL
5MΩ PGA SAR INPUTS RANGE
V2GND
VBN CLAMP LPF
OS0 TO OS2
IBP V3 5MΩ PROGRAMMABLE
CLAMP DIGITAL FILTER BUSY
V3GND 5MΩ PGA SAR SW/HW MODE FRSTDATA
RPD CLAMP LPF
IBN CONTROL
SERIAL DOUTA TO DOUTD
VBP V4 5MΩ
CLAMP SDI
ADC, PGA, AND
V4GND 5MΩ PGA SAR CHANNEL SCLK
CLAMP LPF PARALLEL/
VBN CONTROL SERIAL CS
AND INTERFACE
CONFIGURATION PARALLEL DB0 TO DB15
ICP V5 5MΩ
CLAMP RD
V5GND 5MΩ PGA SAR
RPD LPF SYSTEM GAIN, WR
ICN CLAMP
OFFSET AND
PHASE PAR/SER SEL
VCP V6 5MΩ CALIBRATION
CLAMP
V6GND 5MΩ PGA SAR
VCN CLAMP LPF
REFCAPA
INP V7 5MΩ
DIAGNOSTICS
CLAMP AND
V7GND 5MΩ PGA SAR REFCAPB
LPF ANALOG INPUT
INN CLAMP OPEN DETECT
CONFIGURATION
REFIN/REFOUT
5MΩ
LOAD

LOAD

LOAD

V8
CLAMP 2.5V
V8GND 5MΩ PGA SAR REF
CLAMP LPF REF SELECT

AGND REFGND
15137-088

NOTES
1. IxP AND IxN REPRESENT THE CURRENTS IN PHASE x, WHERE x = A, B, C, OR N. VxN/VxP REPRESENT THE VOLTAGES AT THESE TWO LINES.
FOR EXAMPLE, IAP (POSITIVE PATH) AND IAN (NEGATIVE PATH) REPRESENT THE CURRENTS IN PHASE A.

Figure 88. 8-Channel Data Acquisition System for Power Line Monitoring

Rev. A | Page 48 of 72
Data Sheet AD7606B
LAYOUT GUIDELINES Figure 89 shows the recommended decoupling on the top layer
Follow these layout guidelines when designing the PCB that of the AD7606B board. Figure 90 shows bottom layer decoupling,
houses the AD7606B: which is used for the four AVCC pins and the VDRIVE pin decoupling.
Where the ceramic 100 nF caps for the AVCC pins are placed
 The analog and digital sections are separated and confined close to their respective device pins, a single 100 nF capacitor
to different areas of the board. can be shared between Pin 37 and Pin 38.
 Use at least one ground plane. This plane can be common
or split between the digital and analog sections. In the case
of a split plane, join the digital and analog ground planes in
only one place, preferably as close as possible to the
AD7606B.
 If the AD7606B is in a system where multiple devices
require analog-to-digital ground connections, make the
connection at only one point: a star ground point that is
established as close as possible to the AD7606B.
 Make stable connections to the ground plane. Avoid
sharing one connection for multiple ground pins. Use
individual vias or multiple vias to the ground plane for
each ground pin.
 Avoid running digital lines under the device because doing

15137-083
so couples noise on the die. Allow the analog ground plane
to run under the AD7606B to avoid noise coupling. Figure 89. Top Layer Decoupling REFIN/REFOUT,
 Shield fast switching signals like CONVST, or clocks with REFCAPA, REFCAPB, and REGCAP Pins
digital ground to avoid radiating noise to other sections of
the board and ensure that they never run near analog
signal paths.
 Avoid crossover of digital and analog signals.
 Traces on layers in close proximity on the board run at
right angles to each other to reduce the effect of
feedthrough through the board.
 Power supply lines to the AVCC and VDRIVE pins on the
AD7606B use as large a trace as possible to provide low
impedance paths and reduce the effect of glitches on the
power supply lines. Where possible, use supply planes and
make stable connections between the AD7606B supply
pins and the power tracks on the board. Use a single via or
15137-084
multiple vias for each supply pin.
 Place the decoupling capacitors close to (ideally, directly
against) the supply pins and their corresponding ground Figure 90. Bottom Layer Decoupling
pins. Place the decoupling capacitors for the REFIN/
REFOUT pin and the REFCAPA pin and REFCAPB pin as
close as possible to their respective AD7606B pins. Where
possible, place the pins on the same side of the board as the
AD7606B device.

Rev. A | Page 49 of 72
AD7606B Data Sheet
To ensure stable device to device performance matching in a
AVCC
system that contains multiple AD7606B devices, a symmetrical
layout between the AD7606B devices is important.
Figure 91 shows a layout with two AD7606B devices. The AVCC
supply plane runs to the right of both devices, and the VDRIVE
U2
supply track runs to the left of the two devices. The reference
chip is positioned between the two devices, and the reference
voltage track runs north to Pin 42 of U1 and south to Pin 42 of
U2. A solid ground plane is used.
These symmetrical layout principles can also be applied to a
system that contains more than two AD7606B devices. The
AD7606B devices can be placed in a north/south direction, with
the reference voltage located midway between the devices and
the reference track running in the north/south direction,
similar to Figure 91.

U1

15137-085
Figure 91. Layout for Multiple AD7606B Devices—Top Layer and
Supply Plane Layer

Rev. A | Page 50 of 72
Data Sheet AD7606B

REGISTER SUMMARY
Table 32. Register Summary
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x01 STATUS RESET_ DIGITAL_ RESERVED 0x00 R
DETECT ERROR
0x02 CONFIG RESERVED STATUS_ EXT_OS_CLOCK DOUT_FORMAT RESERVED OPERATION_MODE 0x08 R/W
HEADER
0x03 RANGE_CH1_ CH2_RANGE CH1_RANGE 0x33 R/W
CH2
0x04 RANGE_CH3_ CH4_RANGE CH3_RANGE 0x33 R/W
CH4
0x05 RANGE_CH5_ CH6_RANGE CH5_RANGE 0x33 R/W
CH6
0x06 RANGE_CH7_ CH8_RANGE CH7_RANGE 0x33 R/W
CH8
0x08 OVERSAMPLING OS_PAD OS_RATIO 0x00 R/W
0x09 CH1_GAIN RESERVED CH1_GAIN 0x00 R/W
0x0A CH2_GAIN RESERVED CH2_GAIN 0x00 R/W
0x0B CH3_GAIN RESERVED CH3_GAIN 0x00 R/W
0x0C CH4_GAIN RESERVED CH4_GAIN 0x00 R/W
0x0D CH5_GAIN RESERVED CH5_GAIN 0x00 R/W
0x0E CH6_GAIN RESERVED CH6_GAIN 0x00 R/W
0x0F CH7_GAIN RESERVED CH7_GAIN 0x00 R/W
0x10 CH8_GAIN RESERVED CH8_GAIN 0x00 R/W
0x11 CH1_OFFSET CH1_OFFSET 0x80 R/W
0x12 CH2_OFFSET CH2_OFFSET 0x80 R/W
0x13 CH3_OFFSET CH3_OFFSET 0x80 R/W
0x14 CH4_OFFSET CH4_OFFSET 0x80 R/W
0x15 CH5_OFFSET CH5_OFFSET 0x80 R/W
0x16 CH6_OFFSET CH6_OFFSET 0x80 R/W
0x17 CH7_OFFSET CH7_OFFSET 0x80 R/W
0x18 CH8_OFFSET CH8_OFFSET 0x80 R/W
0x19 CH1_PHASE CH1_PHASE_OFFSET 0x00 R/W
0x1A CH2_PHASE CH2_PHASE_OFFSET 0x00 R/W
0x1B CH3_PHASE CH3_PHASE_OFFSET 0x00 R/W
0x1C CH4_PHASE CH4_PHASE_OFFSET 0x00 R/W
0x1D CH5_PHASE CH5_PHASE_OFFSET 0x00 R/W
0x1E CH6_PHASE CH6_PHASE_OFFSET 0x00 R/W
0x1F CH7_PHASE CH7_PHASE_OFFSET 0x00 R/W
0x20 CH8_PHASE CH8_PHASE_OFFSET 0x00 R/W
0x21 DIGITAL_DIAG_ INTERFACE_ CLK_FS_OS_ BUSY_STUCK_ SPI_READ_ SPI_WRITE_ INT_CRC_ MM_CRC_ ROM_ 0x01 R/W
ENABLE CHECK_EN COUNTER_EN HIGH_ERR_EN ERR_EN ERR_EN ERR_EN ERR_EN CRC_
ERR_EN
0x22 DIGITAL_DIAG_ RESERVED BUSY_STUCK_ SPI_READ_ SPI_WRITE_ INT_CRC_ERR MM_CRC_ ROM_ 0x00 R/W
ERR HIGH_ERR ERR ERR ERR CRC_
ERR
0x23 OPEN_ CH8_OPEN_ CH7_OPEN_ CH6_OPEN_ CH5_OPEN_ CH4_OPEN_ CH3_OPEN_ CH2_OPEN_ CH1_ 0x00 R/W
DETECT_ DETECT_EN DETECT_EN DETECT_EN DETECT_EN DETECT_EN DETECT_EN DETECT_EN OPEN_
ENABLE DETECT_
EN
0x24 OPEN_ CH8_OPEN CH7_OPEN CH6_OPEN CH5_OPEN CH4_OPEN CH3_OPEN CH2_OPEN CH1_ 0x00 R/W
DETECTED OPEN
0x25 AIN_OV_UV_ CH8_OV_ CH7_OV_UV_EN CH6_OV_UV_EN CH5_OV_ CH4_OV_ CH3_OV_ CH2_OV_ CH1_OV_ 0x00 R/W
DIAG_ENABLE UV_EN UV_EN UV_EN UV_EN UV_EN UV_EN
0x26 AIN_OV_DIAG_ CH8_OV_ERR CH7_OV_ERR CH6_OV_ERR CH5_OV_ERR CH4_OV_ERR CH3_OV_ERR CH2_OV_ERR CH1_ 0x00 R/W
ERROR OV_ERR
0x27 AIN_UV_DIAG_ CH8_UV_ERR CH7_UV_ERR CH6_UV_ERR CH5_UV_ERR CH4_UV_ERR CH3_UV_ERR CH2_UV_ERR CH1_ 0x00 R/W
ERROR UV_ERR
0x28 DIAGNOSTIC_ RESERVED CH2_DIAG_MUX_CTRL CH1_DIAG_MUX_CTRL 0x00 R/W
MUX_CH1_2
0x29 DIAGNOSTIC_ RESERVED CH4_DIAG_MUX_CTRL CH3_DIAG_MUX_CTRL 0x00 R/W
MUX_CH3_4

Rev. A | Page 51 of 72
AD7606B Data Sheet
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x2A DIAGNOSTIC_ RESERVED CH6_DIAG_MUX_CTRL CH5_DIAG_MUX_CTRL 0x00 R/W
MUX_CH5_6
0x2B DIAGNOSTIC_ RESERVED CH8_DIAG_MUX_CTRL CH7_DIAG_MUX_CTRL 0x00 R/W
MUX_CH7_8
0x2C OPEN_ OPEN_DETECT_QUEUE 0x00 R/W
DETECT_
QUEUE
0x2D FS_CLK_ CLK_FS_COUNTER 0x00 R
COUNTER
0x2E OS_CLK_ CLK_OS_COUNTER 0x00 R
COUNTER
0x2F ID DEVICE_ID SILICON_REVISION 0x14 R

Rev. A | Page 52 of 72
Data Sheet AD7606B

REGISTER DETAILS
Address: 0x01, Reset: 0x00, Name: STATUS
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] RESET_DETECT (R) [5:0] RESERVED

A reset has been detected, either
full or partial reset
[6] DIGITAL_ERROR (R)
Error present in DIGITAL_DIAG_ERROR
register

Table 33. Bit Descriptions for STATUS

Bits Bit Name Description Reset Access
7 RESET_DETECT A reset has been detected, either full or partial reset. 0x0 R
6 DIGITAL_ERROR Error present in DIGITAL_DIAG_ERROR register. 0x0 R
[5:0] RESERVED Reserved. 0x0 R

Address: 0x02, Reset: 0x08, Name: CONFIG

7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0

[7] RESERVED [1:0] OPERATION_MODE (R/W)

Operation m ode
[6] STATUS_HEADER (R/W) 00: norm al m ode.
Enable STATUS header to be appended 01: standby m ode.
to ADC data in both serial and parallel 10: autostandby m ode.
interface 11: shutdown m ode.
[5] EXT_OS_CLOCK (R/W) [2] RESERVED
In oversam pling m ode, enable external
oversam pling clock. Oversam pling [4:3] DOUT_FORMAT (R/W)
conversions are triggered through Num ber of DOUT lines used in serial
a clock signal applied to CONVST m ode when reading conversions
pin, instead of m anaged by the internal 00: 1 D OUTx.
oversam pling clock 01: 2 D OUTx.
10: 4 D OUTx.
11: 1 D OUTx.

Table 34. Bit Descriptions for CONFIG

Bits Bit Name Description Reset Access
7 RESERVED Reserved. 0x0 R
6 STATUS_HEADER Enable STATUS header to be appended to ADC data in both serial and parallel interface. 0x0 R/W
5 EXT_OS_CLOCK In oversampling mode, enable external oversampling clock. Oversampling conversions are 0x0 R/W
triggered through a clock signal applied to CONVST pin, instead of managed by the
internal oversampling clock.
[4:3] DOUT_FORMAT Number of DOUTx lines used in serial mode when reading conversions. 0x1 R/W
00: 1 DOUTx.
01: 2 DOUTx.
10: 4 DOUTx.
11: 1 DOUTx.
2 RESERVED Reserved. 0x0 R
[1:0] OPERATION_MODE Operation mode. 0x0 R/W
00: normal mode.
01: standby mode.
10: autostandby mode.
11: shutdown mode.

Rev. A | Page 53 of 72
AD7606B Data Sheet
Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 1

[7:4] CH2_RANGE (R/W) [3:0] CH1_RANGE (R/W)

Range options for Channel 2 Range options for Channel 1
0000: ±2.5V single-ended range. 0000: ±2.5V single-ended range.
0001: ±5V single-ended range. 0001: ±5V single-ended range.
0010: ±10V single-ended range. 0010: ±10V single-ended range.
... ...
1101: reserved. 1101: reserved.
1110: reserved. 1110: reserved.
1111: reserved. 1111: reserved.

Table 35. Bit Descriptions for RANGE_CH1_CH2

Bits Bit Name Description Reset Access
[7:4] CH2_RANGE Range options for Channel 2. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH1_RANGE Range options for Channel 1. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.

Rev. A | Page 54 of 72
Data Sheet AD7606B
Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 1

[7:4] CH4_RANGE (R/W) [3:0] CH3_RANGE (R/W)

Range options for Channel 4 Range options for Channel 3
0000: ±2.5V single-ended range. 0000: ±2.5V single-ended range.
0001: ±5V single-ended range. 0001: ±5V single-ended range.
0010: ±10V single-ended range. 0010: ±10V single-ended range.
... ...
1101: reserved. 1101: reserved.
1110: reserved. 1110: reserved.
1111: reserved. 1111: reserved.

Table 36. Bit Descriptions for RANGE_CH3_CH4

Bits Bit Name Description Reset Access
[7:4] CH4_RANGE Range options for Channel 4. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH3_RANGE Range options for Channel 3. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.

Rev. A | Page 55 of 72
AD7606B Data Sheet
Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 1

[7:4] CH6_RANGE (R/W) [3:0] CH5_RANGE (R/W)

Range options for Channel 6 Range options for Channel 5
0000: ±2.5V single-ended range. 0000: ±2.5V single-ended range.
0001: ±5V single-ended range. 0001: ±5V single-ended range.
0010: ±10V single-ended range. 0010: ±10V single-ended range.
... ...
1101: reserved. 1101: reserved.
1110: reserved. 1110: reserved.
1111: reserved. 1111: reserved.

Table 37. Bit Descriptions for RANGE_CH5_CH6

Bits Bit Name Description Reset Access
[7:4] CH6_RANGE Range options for Channel 6. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH5_RANGE Range options for Channel 5. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.

Rev. A | Page 56 of 72
Data Sheet AD7606B
Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 1

[7:4] CH8_RANGE (R/W) [3:0] CH7_RANGE (R/W)

Range options for Channel 8 Range options for Channel 7
0000: ±2.5V single-ended range. 0000: ±2.5V single-ended range.
0001: ±5V single-ended range. 0001: ±5V single-ended range.
0010: ±10V single-ended range. 0010: ±10V single-ended range.
... ...
1101: reserved. 1101: reserved.
1110: reserved. 1110: reserved.
1111: reserved. 1111: reserved.

Table 38. Bit Descriptions for RANGE_CH7_CH8

Bits Bit Name Description Reset Access
[7:4] CH8_RANGE Range options for Channel 8. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH7_RANGE Range options for Channel 7. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.

Rev. A | Page 57 of 72
AD7606B Data Sheet
Address: 0x08, Reset: 0x00, Name: OVERSAMPLING
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:4] OS_PAD (R/W) [3:0] OS_RATIO (R/W)

Oversam pling padding, extend the Oversam pling ratio
internal oversam pling period allowing 0: no oversam pling.
evenly spaced sam pling between 1: oversam pling by 2.
CONVST rising edges. 10: oversam pling by 4.
...
1101: oversam pling off.
1110: oversam pling off.
1111: oversam pling off.

Table 39. Bit Descriptions for OVERSAMPLING

Bits Bit Name Description Reset Access
[7:4] OS_PAD Oversampling padding, extend the internal oversampling period allowing evenly spaced sampling 0x0 R/W
between CONVST rising edges.
[3:0] OS_RATIO Oversampling ratio. 0x0 R/W
0: no oversampling.
1: oversampling by 2.
10: oversampling by 4.
11: oversampling by 8.
100: oversampling by 16.
101: oversampling by 32.
110: oversampling by 64.
111: oversampling by 128.
1000: oversampling by 256.
1001: oversampling off.
1010: oversampling off.
1011: oversampling off.
1100: oversampling off.
1101: oversampling off.
1110: oversampling off.
1111: oversampling off.

Address: 0x09, Reset: 0x00, Name: CH1_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH1_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 40. Bit Descriptions for CH1_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH1_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x0A, Reset: 0x00, Name: CH2_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH2_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 41. Bit Descriptions for CH2_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH2_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Rev. A | Page 58 of 72
Data Sheet AD7606B
Address: 0x0B, Reset: 0x00, Name: CH3_GAIN
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH3_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 42. Bit Descriptions for CH3_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH3_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x0C, Reset: 0x00, Name: CH4_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH4_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 43. Bit Descriptions for CH4_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH4_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x0D, Reset: 0x00, Name: CH5_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH5_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 44. Bit Descriptions for CH5_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH5_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x0E, Reset: 0x00, Name: CH6_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH5_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 45. Bit Descriptions for CH6_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH6_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Rev. A | Page 59 of 72
AD7606B Data Sheet
Address: 0x0F, Reset: 0x00, Name: CH7_GAIN
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH7_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 46. Bit Descriptions for CH7_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH7_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x10, Reset: 0x00, Name: CH8_GAIN

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [5:0] CH8_GAIN (R/W)

R FILTER calibration register. Resolution:
1024 Ω. Range: 0 Ω to 65,536 Ω

Table 47. Bit Descriptions for CH8_GAIN

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH8_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W

Address: 0x11, Reset: 0x80, Name: CH1_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH1_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 48. Bit Descriptions for CH1_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH1_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x12, Reset: 0x80, Name: CH2_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH2_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 49. Bit Descriptions for CH2_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH2_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Rev. A | Page 60 of 72
Data Sheet AD7606B
Address: 0x13, Reset: 0x80, Name: CH3_OFFSET
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH3_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 50. Bit Descriptions for CH3_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH3_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x14, Reset: 0x80, Name: CH4_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH4_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 51. Bit Descriptions for CH4_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH4_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x15, Reset: 0x80, Name: CH5_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH5_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 52. Bit Descriptions for CH5_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH5_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x16, Reset: 0x80, Name: CH6_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH6_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 53. Bit Descriptions for CH6_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH6_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Rev. A | Page 61 of 72
AD7606B Data Sheet
Address: 0x17, Reset: 0x80, Name: CH7_OFFSET
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH7_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 54. Bit Descriptions for CH7_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH7_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x18, Reset: 0x80, Name: CH8_OFFSET

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

[7:0] CH8_OFFSET (R/W)

Offset register. Range from –128
LSB to +127 LSB.

Table 55. Bit Descriptions for CH8_OFFSET

Bits Bit Name Description Reset Access
[7:0] CH8_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset; 0x80 R/W
0xFF = +127 LSB offset.

Address: 0x19, Reset: 0x00, Name: CH1_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH1_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 56. Bit Descriptions for CH1_PHASE

Bits Bit Name Description Reset Access
[7:0] CH1_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x1A, Reset: 0x00, Name: CH2_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH2_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 57. Bit Descriptions for CH2_PHASE

Bits Bit Name Description Reset Access
[7:0] CH2_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x1B, Reset: 0x00, Name: CH3_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH3_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 58. Bit Descriptions for CH3_PHASE

Bits Bit Name Description Reset Access
[7:0] CH3_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Rev. A | Page 62 of 72
Data Sheet AD7606B
Address: 0x1C, Reset: 0x00, Name: CH4_PHASE
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH4_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 59. Bit Descriptions for CH4_PHASE

Bits Bit Name Description Reset Access
[7:0] CH4_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x1D, Reset: 0x00, Name: CH5_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH5_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 60. Bit Descriptions for CH5_PHASE

Bits Bit Name Description Reset Access
[7:0] CH5_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x1E, Reset: 0x00, Name: CH6_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH6_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 61. Bit Descriptions for CH6_PHASE

Bits Bit Name Description Reset Access
[7:0] CH6_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x1F, Reset: 0x00, Name: CH7_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH7_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 62. Bit Descriptions for CH7_PHASE

Bits Bit Name Description Reset Access
[7:0] CH7_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Address: 0x20, Reset: 0x00, Name: CH8_PHASE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CH8_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75
µs in steps of 1.25 µs

Table 63. Bit Descriptions for CH8_PHASE

Bits Bit Name Description Reset Access
[7:0] CH8_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W

Rev. A | Page 63 of 72
AD7606B Data Sheet
Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1

[7] INTERFACE_CHECK_EN (R/W) [0] ROM_CRC_ERR_EN (R/W)

Enable interface check. Provides Enable ROM CRC check
a fixed data on each channel when
reading ADC data [1] MM_CRC_ERR_EN (R/W)
Enable m em ory m ap CRC check
[6] CLK_FS_OS_COUNTER_EN (R/W)
Enable FS and OS clock counter [2] INT_CRC_ERR_EN (R/W)
Enable interface CRC check
[5] BUSY_STUCK_HIGH_ERR_EN (R/W)
Enable busy stuck high check [3] SPI_WRITE_ERR_EN (R/W)
Enable checking if attem pting to write
[4] SPI_READ_ERR_EN (R/W) to an invalid address
Enable checking if attem pting to read
from an invalid address

Table 64. Bit Descriptions for DIGITAL_DIAG_ENABLE

Bits Bit Name Description Reset Access
7 INTERFACE_CHECK_EN Enable interface check. Provides a fixed data on each channel when reading ADC 0x0 R/W
data.
6 CLK_FS_OS_COUNTER_EN Enable FS and OS clock counter. 0x0 R/W
5 BUSY_STUCK_HIGH_ERR_EN Enable busy stuck high check. 0x0 R/W
4 SPI_READ_ERR_EN Enable checking if attempting to read from an invalid address. 0x0 R/W
3 SPI_WRITE_ERR_EN Enable checking if attempting to write to an invalid address. 0x0 R/W
2 INT_CRC_ERR_EN Enable interface CRC check. 0x0 R/W
1 MM_CRC_ERR_EN Enable memory map CRC check. 0x0 R/W
0 ROM_CRC_ERR_EN Enable ROM CRC check. 0x1 R/W

Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [0] ROM_CRC_ERR (R/W1C)

ROM CRC error
[5] BUSY_STUCK_HIGH_ERR (R/W1C)
Busy stuck high error. Busy line has [1] MM_CRC_ERR (R/W1C)
been at high logic level for longer Mem ory m ap CRC error
than 4us
[2] INT_CRC_ERR (R/W1C)
[4] SPI_READ_ERR (R/W1C) Interface CRC error
SPI invalid read address
[3] SPI_WRITE_ERR (R/W1C)
SPI invalid write address

Table 65. Bit Descriptions for DIGITAL_DIAG_ERR

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
5 BUSY_STUCK_HIGH_ERR Busy stuck high error. Busy line has been at high logic level for longer than 4 μs. 0x0 R/W1C
4 SPI_READ_ERR SPI invalid read address. 0x0 R/W1C
3 SPI_WRITE_ERR SPI invalid write address. 0x0 R/W1C
2 INT_CRC_ERR Interface CRC error. 0x0 R/W1C
1 MM_CRC_ERR Memory map CRC error. 0x0 R/W1C
0 ROM_CRC_ERR ROM CRC error. 0x0 R/W1C

Rev. A | Page 64 of 72
Data Sheet AD7606B
Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] CH8_OPEN_DETECT_EN (R/W) [0] CH1_OPEN_DETECT_EN (R/W)

In autom atic m ode, enable analog In autom atic m ode, enable analog
input open detection for Channel input open detection for Channel
8. In m anual m ode, sets the PGA 1. In m anual m ode, sets the PGA
com m on m ode to high com m on m ode to high
[6] CH7_OPEN_DETECT_EN (R/W) [1] CH2_OPEN_DETECT_EN (R/W)
In autom atic m ode, enable analog In autom atic m ode, enable analog
input open detection for Channel input open detection for Channel
7. In m anual m ode, sets the PGA 2. In m anual m ode, sets the PGA
com m on m ode to high com m on m ode to high
[5] CH6_OPEN_DETECT_EN (R/W) [2] CH3_OPEN_DETECT_EN (R/W)
In autom atic m ode, enable analog In autom atic m ode, enable analog
input open detection for Channel input open detection for Channel
6. In m anual m ode, sets the PGA 3. In m anual m ode, sets the PGA
com m on m ode to high com m on m ode to high
[4] CH5_OPEN_DETECT_EN (R/W) [3] CH4_OPEN_DETECT_EN (R/W)
In autom atic m ode, enable analog In autom atic m ode, enable analog
input open detection for Channel input open detection for Channel
5. In m anual m ode, sets the PGA 4. In m anual m ode, sets the PGA
com m on m ode to high com m on m ode to high

Table 66. Bit Descriptions for OPEN_DETECT_ENABLE

Bits Bit Name Description Reset Access
7 CH8_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 8. In manual 0x0 R/W
mode, sets the PGA common mode to high.
6 CH7_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 7. In manual 0x0 R/W
mode, sets the PGA common mode to high.
5 CH6_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 6. In manual 0x0 R/W
mode, sets the PGA common mode to high.
4 CH5_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 5. In manual 0x0 R/W
mode, sets the PGA common mode to high.
3 CH4_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 4. In manual 0x0 R/W
mode, sets the PGA common mode to high.
2 CH3_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 3. In manual 0x0 R/W
mode, sets the PGA common mode to high.
1 CH2_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 2. In manual 0x0 R/W
mode, sets the PGA common mode to high.
0 CH1_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 1. In manual 0x0 R/W
mode, sets the PGA common mode to high.

Address: 0x24, Reset: 0x00, Name: OPEN_DETECTED

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] CH8_OPEN (R/W1C) [0] CH1_OPEN (R/W1C)

Analog Input 8 open detected Analog Input 1 open detected
[6] CH7_OPEN (R/W1C) [1] CH2_OPEN (R/W1C)
Analog Input 7 open detected Analog Input 2 open detected
[5] CH6_OPEN (R/W1C) [2] CH3_OPEN (R/W1C)
Analog Input 6 open detected Analog Input 3 open detected
[4] CH5_OPEN (R/W1C) [3] CH4_OPEN (R/W1C)
Analog Input 5 open detected Analog Input 4 open detected

Table 67. Bit Descriptions for OPEN_DETECTED

Bits Bit Name Description Reset Access
7 CH8_OPEN Analog Input 8 open detected. 0x0 R/W1C
6 CH7_OPEN Analog Input 7 open detected. 0x0 R/W1C
5 CH6_OPEN Analog Input 6 open detected. 0x0 R/W1C
4 CH5_OPEN Analog Input 5 open detected. 0x0 R/W1C
3 CH4_OPEN Analog Input 4 open detected. 0x0 R/W1C

Rev. A | Page 65 of 72
AD7606B Data Sheet
Bits Bit Name Description Reset Access
2 CH3_OPEN Analog Input 3 open detected. 0x0 R/W1C
1 CH2_OPEN Analog Input 2 open detected. 0x0 R/W1C
0 CH1_OPEN Analog Input 1 open detected. 0x0 R/W1C

Address: 0x25, Reset: 0x00, Name: AIN_OV_UV_DIAG_ENABLE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] CH8_OV_UV_EN (R/W) [0] CH1_OV_UV_EN (R/W)

Enable overvoltage/undervoltage Enable overvoltage/undervoltage
error check on Channel 8 error check on Channel 1
[6] CH7_OV_UV_EN (R/W) [1] CH2_OV_UV_EN (R/W)
Enable overvoltage/undervoltage Enable overvoltage/undervoltage
error check on Channel 7 error check on Channel 2
[5] CH6_OV_UV_EN (R/W) [2] CH3_OV_UV_EN (R/W)
Enable overvoltage/undervoltage Enable overvoltage/undervoltage
error check on Channel 6 error check on Channel 3
[4] CH5_OV_UV_EN (R/W) [3] CH4_OV_UV_EN (R/W)
Enable overvoltage/undervoltage Enable overvoltage/undervoltage
error check on Channel 5 error check on Channel 4

Table 68. Bit Descriptions for AIN_OV_UV_DIAG_ENABLE

Bits Bit Name Description Reset Access
7 CH8_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 8. 0x0 R/W
6 CH7_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 7. 0x0 R/W
5 CH6_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 6. 0x0 R/W
4 CH5_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 5. 0x0 R/W
3 CH4_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 4. 0x0 R/W
2 CH3_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 3. 0x0 R/W
1 CH2_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 2. 0x0 R/W
0 CH1_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 1. 0x0 R/W

Address: 0x26, Reset: 0x00, Name: AIN_OV_DIAG_ERROR

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] CH8_OV_ERR (R/W1C) [0] CH1_OV_ERR (R/W1C)

Overvoltage error on Channel 8 Overvoltage error on Channel 1
[6] CH7_OV_ERR (R/W1C) [1] CH2_OV_ERR (R/W1C)
Overvoltage error on Channel 7 Overvoltage error on Channel 2
[5] CH6_OV_ERR (R/W1C) [2] CH3_OV_ERR (R/W1C)
Overvoltage error on Channel 6 Overvoltage error on Channel 3
[4] CH5_OV_ERR (R/W1C) [3] CH4_OV_ERR (R/W1C)
Overvoltage error on Channel 5 Overvoltage error on Channel 4

Table 69. Bit Descriptions for AIN_OV_DIAG_ERROR

Bits Bit Name Description Reset Access
7 CH8_OV_ERR Overvoltage error on Channel 8. 0x0 R/W1C
6 CH7_OV_ERR Overvoltage error on Channel 7. 0x0 R/W1C
5 CH6_OV_ERR Overvoltage error on Channel 6. 0x0 R/W1C
4 CH5_OV_ERR Overvoltage error on Channel 5. 0x0 R/W1C
3 CH4_OV_ERR Overvoltage error on Channel 4. 0x0 R/W1C
2 CH3_OV_ERR Overvoltage error on Channel 3. 0x0 R/W1C
1 CH2_OV_ERR Overvoltage error on Channel 2. 0x0 R/W1C
0 CH1_OV_ERR Overvoltage error on Channel 1. 0x0 R/W1C

Rev. A | Page 66 of 72
Data Sheet AD7606B
Address: 0x27, Reset: 0x00, Name: AIN_UV_DIAG_ERROR
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7] CH8_UV_ERR (R/W1C) [0] CH1_UV_ERR (R/W1C)

Undervoltage error on Channel 8 Undervoltage error on Channel 1
[6] CH7_UV_ERR (R/W1C) [1] CH2_UV_ERR (R/W1C)
Undervoltage error on Channel 7 Undervoltage error on Channel 2
[5] CH6_UV_ERR (R/W1C) [2] CH3_UV_ERR (R/W1C)
Undervoltage error on Channel 6 Undervoltage error on Channel 3
[4] CH5_UV_ERR (R/W1C) [3] CH4_UV_ERR (R/W1C)
Undervoltage error on Channel 5 Undervoltage error on Channel 4

Table 70. Bit Descriptions for AIN_UV_DIAG_ERROR

Bits Bit Name Description Reset Access
7 CH8_UV_ERR Undervoltage error on Channel 8. 0x0 R/W1C
6 CH7_UV_ERR Undervoltage error on Channel 7. 0x0 R/W1C
5 CH6_UV_ERR Undervoltage error on Channel 6. 0x0 R/W1C
4 CH5_UV_ERR Undervoltage error on Channel 5. 0x0 R/W1C
3 CH4_UV_ERR Undervoltage error on Channel 4. 0x0 R/W1C
2 CH3_UV_ERR Undervoltage error on Channel 3. 0x0 R/W1C
1 CH2_UV_ERR Undervoltage error on Channel 2. 0x0 R/W1C
0 CH1_UV_ERR Undervoltage error on Channel 1. 0x0 R/W1C
Address: 0x28, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH1_2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [2:0] CH1_DIAG_MUX_CTRL (R/W)

Channel 1 diagnostic mux control. Select
[5:3] CH2_DIAG_MUX_CTRL (R/W) ±10V range.
Channel 2 diagnostic mux control. Select 000: Analog Input pin.
±10V range. 001: Die temperature = (output voltage − 0.69068)/0.019328
000: Analog Input pin. + 25°C.
001: Die temperature = (output voltage − 0.69068)/0.019328 010: 2.5V Reference x 4.
+ 25°C. 011: ALDO 1.8V x 4.
010: 2.5V Reference x 4. 100: DLDO 1.8V x 4.
011: ALDO 1.8V x 4. 101: VDRIVE.
100: DLDO 1.8V x 4. 110: AGND.
101: VDRIVE. 111: AVCC.
110: AGND.
111: AVCC.

Table 71. Bit Descriptions for DIAGNOSTIC_MUX_CH1_2

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH2_DIAG_MUX_CTRL Channel 2 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: ALDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.
[2:0] CH1_DIAG_MUX_CTRL Channel 1 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: DLDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.

Rev. A | Page 67 of 72
AD7606B Data Sheet
Address: 0x29, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH3_4
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [2:0] CH3_DIAG_MUX_CTRL (R/W)

Channel 3 diagnostic mux control. Select
[5:3] CH4_DIAG_MUX_CTRL (R/W) ±10V range.
Channel 4 diagnostic mux control. Select 000: Analog Input pin.
±10V range. 001: Die temperature = (output voltage − 0.69068)/0.019328
000: Analog Input pin. + 25°C.
001: Die temperature = (output voltage − 0.69068)/0.019328 010: 2.5V Reference x 4.
+ 25°C. 011: ALDO 1.8V x 4.
010: 2.5V Reference x 4. 100: DLDO 1.8V x 4.
011: ALDO 1.8V x 4. 101: VDRIVE.
100: DLDO 1.8V x 4. 110: AGND.
101: VDRIVE. 111: AVCC.
110: AGND.
111: AVCC.

Table 72. Bit Descriptions for DIAGNOSTIC_MUX_CH3_4

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH4_DIAG_MUX_CTRL Channel 4 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: ALDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.
[2:0] CH3_DIAG_MUX_CTRL Channel 3 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: DLDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.

Rev. A | Page 68 of 72
Data Sheet AD7606B
Address: 0x2A, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH5_6
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [2:0] CH5_DIAG_MUX_CTRL (R/W)

Channel 5 diagnostic mux control. Select
[5:3] CH6_DIAG_MUX_CTRL (R/W) ±10V range.
Channel 6 diagnostic mux control. Select 000: Analog Input pin.
±10V range. 001: Die temperature = (output voltage − 0.69068)/0.019328
000: Analog Input pin. + 25°C.
001: Die temperature = (output voltage − 0.69068)/0.019328 010: 2.5V Reference x 4.
+ 25°C. 011: ALDO 1.8V x 4.
010: 2.5V Reference x 4. 100: DLDO 1.8V x 4.
011: ALDO 1.8V x 4. 101: VDRIVE.
100: DLDO 1.8V x 4. 110: AGND.
101: VDRIVE. 111: AVCC.
110: AGND.
111: AVCC.

Table 73. Bit Descriptions for DIAGNOSTIC_MUX_CH5_6

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH6_DIAG_MUX_CTRL Channel 6 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage – 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: ALDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.
[2:0] CH5_DIAG_MUX_CTRL Channel 5 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: DLDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.

Rev. A | Page 69 of 72
AD7606B Data Sheet
Address: 0x2B, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH7_8
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:6] RESERVED [2:0] CH7_DIAG_MUX_CTRL (R/W)

Channel 7 diagnostic mux control. Select
[5:3] CH8_DIAG_MUX_CTRL (R/W) ±10V range.
Channel 8 diagnostic mux control. Select 000: Analog Input pin.
±10V range. 001: Die temperature = (output voltage − 0.69068)/0.019328
000: Analog Input pin. + 25°C.
001: Die temperature = (output voltage − 0.69068)/0.019328 010: 2.5V Reference x 4.
+ 25°C. 011: ALDO 1.8V x 4.
010: 2.5V Reference x 4. 100: DLDO 1.8V x 4.
011: ALDO 1.8V x 4. 101: VDRIVE.
100: DLDO 1.8V x 4. 110: AGND.
101: VDRIVE. 111: AVCC.
110: AGND.
111: AVCC.

Table 74. Bit Descriptions for DIAGNOSTIC_MUX_CH7_8

Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH8_DIAG_MUX_CTRL Channel 8 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: ALDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.
[2:0] CH7_DIAG_MUX_CTRL Channel 7 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: Analog input pin.
001: Die temperature = (output voltage − 0.69068)/0.019328 + 25°C.
010: 2.5 V Reference × 4.
011: ALDO 1.8 V × 4.
100: DLDO 1.8 V × 4.
101: VDRIVE.
110: AGND.
111: AVCC.

Address: 0x2C, Reset: 0x00, Name: OPEN_DETECT_QUEUE

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] OPEN_DETECT_QUEUE (R/W)

Num ber of conversions for no change
on output codes before enabling
open detect function. Range = 2 to
256. Queue = 1 enables m anual
m ode

Table 75. Bit Descriptions for OPEN_DETECT_QUEUE

Bits Bit Name Description Reset Access
[7:0] OPEN_DETECT_QUEUE Number of conversions for no change on output codes before enabling open detect 0x0 R/W
function. Range = 2 to 256. Queue = 1 enables manual mode.

Rev. A | Page 70 of 72
Data Sheet AD7606B
Address: 0x2D, Reset: 0x00, Name: FS_CLK_COUNTER
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CLK_FS_COUNTER (R)

Determ ine the frequency of the FS
clock oscillator. Counter is increm ented
at 16 M/64.

Table 76. Bit Descriptions for FS_CLK_COUNTER

Bits Bit Name Description Reset Access
[7:0] CLK_FS_COUNTER Determine the frequency of the FS clock oscillator. Counter is incremented at Delay × 0x0 R
16 MHz/64.

Address: 0x2E, Reset: 0x00, Name: OS_CLK_COUNTER

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:0] CLK_OS_COUNTER (R)

Determ ine the frequency of the OS
clock oscillator. Counter resolution
= 200 kHz.

Table 77. Bit Descriptions for OS_CLK_COUNTER

Bits Bit Name Description Reset Access
[7:0] CLK_OS_COUNTER Determine the frequency of the OS clock oscillator. Counter resolution = 200 kHz. 0x0 R

Address: 0x2F, Reset: 0x14, Name: ID

7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[7:4] DEVICE_ID (R) [3:0] SILICON_REVISION (R)

Generic Silicon revision
0000: reserved.
0001: AD7606B Generic.

Table 78. Bit Descriptions for ID

Bits Bit Name Description Reset Access
[7:4] DEVICE_ID Generic. 0x1 R
0000: reserved.
0001: AD7606B generic.
[3:0] SILICON_REVISION Silicon revision. 0x4 R

Rev. A | Page 71 of 72
AD7606B Data Sheet

OUTLINE DIMENSIONS
12.20
0.75 12.00 SQ
0.60 1.60 11.80
0.45 MAX
64 49
1 48

PIN 1

10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 16 33
0°
0.05 SEATING 17 32
PLANE 0.08
COPLANARITY VIEW A 0.27
0.50
BSC 0.22
VIEW A LEAD PITCH 0.17
ROTATED 90° CCW

051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 92. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD7606BBSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7606BBSTZ-RL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVAL-AD7606BFMCZ Evaluation Board for the AD7606B
EVAL-SDP-CH1Z Evaluation Controller Board
1
Z = RoHS Compliant Part.

©2019–2021 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D15137-4/21(A)

Rev. A | Page 72 of 72
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