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The 8086 Microprocessor Hardware Specifications

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Hadeel N Abdullah
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 University of Technology
Department of Electrical Engineering
Microprocessor Engineering
Third Class

The 8086 Microprocessor

Hardware Specifications

Assist. Prof. Dr. Hadeel Nasrat Abdullah

Pin Diagram of 8086 and Pin description of 8086
Figure (1) shows the Pin diagram of 8086. The 8086 can be configured to
work in either of two modes:
The minimum mode is selected by applying logic 1 to the MN/MX
MN / MX

input. It is typically used for larger multiple microprocessor systems.

The maximum mode is selected by applying logic 0 to the MN / MX input.
It is typically used for larger multiple microprocessor systems.
Depending on the mode of operation selected, the 8086 signals can be
categorized in three groups.
•The first are the signal having common functions in minimum as well as
maximum mode.
•The second are the signals which have special functions for minimum
mode.
•The third are the signals having special functions for maximum mode.
Lecture 8/Part 1: The 8086 Up. Hardware
Specifications Assist. Prof. Dr. Hadeel N.
Abdullah
8086 Pin Diagram

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
 Minimum mode Operation
 Minimum mode operation is the least expensive way to operate the 8086.
 In minimum mode, the 8086 itself provides all the control signals needed
to implement the memory and I/O interfaces.
Power supply
Vcc GND

 These control signals

are identical to those INTR
Address / data bus

of the Intel 8085A an _____

INTA
AD0-AD15,
A16/S3-A19/S6
earlier 8-bit
_____
microprocessor. TEST
Interrupt ALE
Interface ____
 This mode allows the NMI BHE/S7
8086 MPU
8085A peripherals to RESET
’⁄

be used with the DT/

Memory/IO
___
8086 without any HOLD RD
Controls

special consideration.
___
DMA HLDA WR
Interface ____
DEN

Mode Select READY

MN/

Lecture 8/Part 1: The 8086 Up. Hardware Specifications CLK

Assist. Prof. Dr. Hadeel N. Abdullah
 Maximum mode Operation
 This mode supports existence of more than one processor in a system i.e.
multiprocessor system.
 In a multiprocessor system environment more than one processor exists in the system,
and each processor is executing its own program.
 In maximum mode
the 8086 provides
facilities by
generating some of
the control signals
externally.
 In maximum-mode, a
separate chip (the
8288 Bus Controller)
is used to help in
sending control
signals over the
shared bus.

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
The Common Signals for Both Minimum & Maximum Modes
Common Signals
Name Function Type Operation
These line contain the address bus which is 20
Bi- bits long [A0 (the LSB) to A19 (the MSB)]
Address/
AD15-AD0 directional whenever ALE is logic 1, and contain the data
Data Bus
3-state bus which is 16 bits long [D0 (the LSB) to D15
(the MSB)] whenever ALE is logic 0.
These are the time multiplexed to provide
address signals (A19-A16) and status lines (S6-
S3). Bits S6 always remains logic 0, bit S5
indicates the condition of interrupt flag (IF) bits.
A19/S6 - Address/S Output
S4 and S3 together form a 2-bit binary code that
A16/S3 tatus 3-state
identifies which of the internal segment registers
was used to generate the physical address that
was output on the address bus during the
current bus cycle (See Table A)
Min/Max If the pin goes high(1) the 8086 operates in
MN / MX mode Input minimum mode. If the pin goes low(0) 8086 is
control configured to support multiprocessor system.
Lecture 8/Part 1: The 8086 Up. Hardware Specifications
Assist. Prof. Dr. Hadeel N. Abdullah
The Common Signals for Both Minimum & Maximum Modes
Common Signals
Name Function Type Operation
RD Read Output is logic 0 (low) when the data is read from
Control 3-state memory or I/O location
is only used by the wait instruction. If the pin
TEST goes LOW (logic 0), execution will continue (WAIT
Wait on
Input instruction functions as a NOP), else if pin goes
test control HIGH (logic 1) the processor remains in an idle
state.
If the pin goes LOW(0) the processor enters into
READY Wait state wait state and remains in an idle state. If the pin
Input goes HIGH(1) it has no effect on the operation of
control
the processor.

is the system set reset input signal. If this pin held

System HIGH for a minimum of four clocking periods
RESET Input
reset causes to processor to reset itself and start
execution from FFFF0H i.e. reinitialize the system.

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
The Common Signals for Both Minimum & Maximum Modes
Common Signals
Name Function Type Operation
The clock input provides the basic timing for
processor operation and bus control activity.
System
CLK Input Its an asymmetric square wave with 33% duty
clock cycle (HIGH for one-third of the clocking period
and LOW for two-third).

5V power supply for the operation of the

Vcc +5V Input internal circuit.
Ground for the internal circuit. The 8086
microprocessor have two pins labeled GND
GND Ground Input both must be connected to ground for proper
operation.

Bus High The bus high enable signal goes low to indicate
BHE /S7 Enable/ Input the transfer of data over the higher order (D15-
Status D8). The state S7 is always logic 1.

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
The Common Signals for Both Minimum & Maximum Modes
Common Signals
Name Function Type Operation
is a maskable interrupt input. This is a triggered
input. This is sampled during the last clock
cycles of each instruction to determine the
Interrupt availability of the request. If any interrupt
INTR Input
Request request is pending (IF=1), the processor enters
the interrupt acknowledge cycle ( INTA
becomes active) after the current instruction
has complete execution.

is the non maskable interrupt input. The NMI is

non maskable not maskable internally by software. A
NIM interrupt Input transition from low to high initiates the
Request interrupt response at the end of the current
instruction.

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
The Minimum Modes Signals
Minimum Mode Signals
Name Function Type Operation
This is a status line logically equivalent to S2 in
maximum mode. When it is LOW, it indicates
Memory/IO Output
/ the CPU is having an I/O operation, and when
Control 3-state it is HIGH, it indicates that the CPU is having a
memory operation.
indicates that the processor is performing a
WRITE Output
write memory or write I/O cycle, depending on
Control 3-state the state of the M/IO signal.
It is an output signal provided by the 8086 and
Address
can be used to demultiplexed AD0 to AD15 in
ALE Latch Output to A10 toA15 and D0 to D15. This signal is
Enable active high and is never tristated.
Interrupt This signal is used as a read strobe for interrupt
Acknowled- Output acknowledge cycles. i.e. when it goes low, the
gment processor has accepted the interrupt.

Lecture 8/Part 1: The 8086 Up. Hardware Specifications

Assist. Prof. Dr. Hadeel N. Abdullah
The Minimum Modes Signals
Minimum Mode Signals
Name Function Type Operation
This output is used to decide the direction of
Data data flow through the transceiver (bidirectional
Output
/ Transmit/ buffers). When ( / =1) the processor sends
3-state data out (transmitting), when ( / =0) the
Receive
processor receiving data.

Output
DEN Data Enable activate external data bus buffers.
3-state
When an external device wants to take control
of the system bus (Data, Address, Control), it
Hold
HOLD Input signals to the 8086 by switching HOLD to logic
request 1. The hold input requests a direct memory
access (DMA).
Hold The bus high enable signal goes low to indicate
HLDA Acknowled- Output the transfer of data over the higher order (D15-
gment D8). The state S7 is always logic 1.
Lecture 8/Part 1: The 8086 Up. Hardware
Specifications Assist. Prof. Dr. Hadeel
N. Abdullah
The Maximum Modes Signals
Minimum Mode Signals
Name Function Type Operation
Request/G These lines are bidirectional, and are used to both
/ rant bus Bi- request and grant a DMA operation in maximum
/ access direction
mode.
control
This pin indicates that other system bus master will
Bus
be prevented from gaining the system bus, while the
priority Output
LOCK signal is low. The LOCK signal is activated by
lock 3-state the ‘LOCK’ prefix instruction and remains active until
control
the completion of the next instruction.
These three bit are input to the external bus
Status Output controller device 8288, which decodes them to
, ,
Lines 3-state identify the type of next bus cycle. Table (B) shows
the function of these status bits in maximum mode.
provide status to allow external tracking of the
internal 8086 instruction queue. These pins are
Queue
QS1, QS2 Output provided for access by the numeric coprocessor
Status (8087). Table (C) shows the operation of the queue
status bits.
Lecture 8/Part 1: The 8086 Up. Hardware Specifications
Assist. Prof. Dr. Hadeel N. Abdullah
 Table (A) Table (B): Bus Status Codes
S4 S3 Indication CPU Cycle 8288 Command
Interrupt
0 0 Extra Data Segment 0 0 0
Acknowledge
0 1 Stack Segment 0 0 1 Read I/O port
1 0 Code or No Segment 0 1 0 Write I/O port ,
0 1 1 Halt None
1 1 Data Segment 1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory ,
1 1 1 Passive None

Table (C): Queue Status bits

QS1 QS0 Indication
0 0 No Operation (Queue is idle)
0 1 First Byte of the opcode from the queue
1 0 Empty Queue
1 1 Subsequent Byte from the Queue
Lecture 8/Part 1: The 8086 Up. Hardware
Specifications Assist. Prof. Dr. Hadeel
N. Abdullah

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