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Multiplier Shift Add

This document describes a 4x4 bit multiplier circuit. It uses a process to iterate through states to multiply a 4-bit multiplier and 4-bit multiplicand. The accumulator signal ACC is used to store the resulting 8-bit product. The state is incremented each clock cycle until it reaches 9, at which point the Done signal is asserted to indicate completion.

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wallra
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110 views1 page

Multiplier Shift Add

This document describes a 4x4 bit multiplier circuit. It uses a process to iterate through states to multiply a 4-bit multiplier and 4-bit multiplicand. The accumulator signal ACC is used to store the resulting 8-bit product. The state is incremented each clock cycle until it reaches 9, at which point the Done signal is asserted to indicate completion.

Uploaded by

wallra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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library BITLIB;

use BITLIB.bit_pack.all;

entity mult4X4 is
port (Clk, St: in bit;
Mplier,Mcand : in bit_vector(3 downto 0);
Done: out bit);
end mult4X4;

architecture behavel of mult4X4 is


signal State: integer range 0 to 9;
signal ACC: bit_vector(8 downto 0);
alias M: bit is ACC(0);

begin
proces
s
begin
wait until Clk = ‘1’;
case State is
when 0 =>
if St='1' then
ACC(8 downto 4) <= 00000";
ACC(3 downto 0) <= Mplier;
State <= 1;
end if;
when 1 | 3 | 5 | 7 =>
if M = ‘1’ then
ACC(8 downto 4) <= add4(ACC(7 downto
4),Mcand,'0'); State <= State+1;
else
ACC <= 'O' & ACC(8 downto 1);
State <= State + 2;
end if;
when 2 | 4 | 6 | 8 =>
ACC <= '0' & ACC(8 downto 1);
State <= State + 1;
when 9 =>
State <= 0;
end case;
end process;
Done <= '1' when State = 9 else
'O'; end behavel;

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