Report

On

Implementation of Fifo Memory in Verilog

Submitted by
NABEEL AHMAD
Reg. No. 2019VL04

M. Tech. (1st SEM)

Microelectronics and VLSI Design

Submitted to
Prof. R.K. Nagari
Prof. R.A. Mishra

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY
ALLAHABAD,PRAYAGRAJ- 211004, INDIA

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 Content

Acknowledgement .............................................................................................. 3

Abstract ..............................................................................................................4

Introduction ........................................................................................................5

Block diagram and architecture ............................................................................7

Verilog code…………………………. ..................................................................10

Test bench and Simulation results .......................................................................13

Reference ..........................................................................................................14

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 ACKNOWLEDGEMENT

I would like to express my special thanks of gratitude to Prof. R.K. Nagaria and Prof. R.A.

Mishra who gave me the golden opportunity to do this wonderful project on the topic

“Implementation of Fifo Memory in verilog”, which also helped me in doing a lot of Research

and I came to know about so many new things. I am really thankful to him.

Secondly I would also like to thank my friends who helped me a lot in finalizing this project within

the limited time frame.

By

NABEEL AHMAD

(2019VL04)

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 Abstract

First-In First-Out (FIFO) memory structures have been the dominant mechanism to
control the flow of data between source and destination. The function of FIFO runs
around memory element and control circuitry. It has control logic embedded with it,
which efficiently manages read and write operations. It has the capability to notify the
concerned modules regarding its empty status and full status to help ensure no underflow
or overflow of data. This FIFO design is classified as synchronous, as clocks control the
read and write operations. Both read and write operations happen simultaneously using
of Dual port RAM or an array of flip-flops in the design.

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 Introduction

FIFO is a First-In-First-Out memory queue with control logic that manages the read and write
operations, generates status flags, and provides optional handshake signals for interfacing
with the user logic. It is often used to control the flow of data between source and destination.
FIFO can be classified as synchronous or asynchronous depending on whether same clock or
different (asynchronous) clocks control the read and write operations. In this project the
objective is to design, verify and synthesize a synchronous FIFO using binary coded read and
write pointers to address the memory array. FIFO full and empty flags are generated and
passed on to source and destination logics, respectively, to pre-empt any overflow or
underflow of data. In this way data integrity between source and destination is maintained. In
computer programming, FIFO (first-in, first-out) is an approach to handling program work
requests from queues or stacks so that the oldest request is handled first. In hardware it is
either an array of flops or Read/Write memory that store data given from one clock domain
and on request supplies with the same data to other clock domain following the first in first
out logic. The clock domain that supplies data to FIFO is often referred as WRITE OR
INPUT LOGIC and the clock domain that reads data from the FIFO is often referred as
READ OR OUTPUT LOGIC. FIFOs are used in designs to safely pass multi-bit data words
from one clock domain to another or to control the flow of data between source and
destination side sitting in the same clock domain. If read and write clock domains are
governed by same clock signal the FIFO is said to be SYNCHRONOUS and if read and write
clock domains are governed by different (asynchronous) clock signals FIFO is said to be
ASYNCHRONOUS. FIFO full and FIFO empty flags are of great concern as no data should
be written in full condition and no data should be read in empty condition, as it can lead to
loss of data or generation of non-relevant data. The full and empty conditions of FIFO are
controlled using binary or gray pointers. In this report we deal with binary pointers only since
we are designing SYNCHRONOUS FIFO. The gray pointers are used for generating full and
empty conditions for ASYNCHRONOUS FIFO.

Synchronous FIFO

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Synchronous FIFOs are controlled based on methods of control proven in processor systems.
Every digital processor system works synchronized with a system-wide clock signal. This
system timing continues to run even if no actions are being executed. Enable signals, also
often called chip-select signals, start the synchronous execution of write and read operations
in the various devices, such as memories and ports.

Functional Block Diagram

The above figure depicts the basic building blocks of a synchronous FIFO which are:
memory array, write control logic and read control logic. The memory array can be
implemented either with array of flip-flops or with a dual-port read/write memory. Both of
these implementations allow simultaneous read and write accesses. This simultaneous access
gives the FIFO its inherent synchronization property. There are no restrictions regarding
timing between accesses of the two ports. This means simply, that while one port is writing to
the memory at one rate, the other port NAMEI/ODESCRIPTIONread_dataORead data in
response to a read request.fifo_emptyOIndicates that FIFO’s internal memory is empty and
therefore has no data to serve upon.

can be reading at another rate totally independent of one another. The only restriction placed
is that the simultaneous read and write access should not be from/to the same memory
location. The Synchronous FIFO has a single clock port clk for both data-read and data-write
operations. Data presented at the module's data-input port write_data is written into the next
available empty memory location on a rising clock edge when the write-enable input
write_enable is high. The full status output fifo_full indicates that no more empty locations
remain in the module's internal memory. Data can be read out of the FIFO via the module's
data-output port read_data in the order in which it was written by asserting read-enable signal
read_enable prior to a rising clock edge. The memory-empty status output fifo_empty
indicates that no more data resides in the module's internal memory. There are almost empty
and almost full flags too viz. fifo_aempty and fifo_afull which can be used to control the read
and write speeds of the requestor and the source.WRITE CONTROL LOGIC : Write Control
Logic is used to control the write operation of the FIFO’s internal memory. It generates
binary-coded write pointer which points to the memory location where the incoming data is
to be written. Write pointer is incremented by one after every successful write operation.
Additionally it generates FIFO full and almost full flags which in turn are used to prevent any
data loss. For example if a write request comes when FIFO is full then Write Control Logic
stalls the write into the memory till the time fifo_full flag gets de-asserted. It intimates the
stalling of write to source by not sending any acknowledgement in response to the write
request.

READ CONTROL LOGIC :

Read Control Logic is used to control the read operation of the FIFO’s internal memory. It
generates binary-coded read pointer which points to the memory location from where the data
is to be read. Read pointer is incremented by one after every successful read operation.
Additionally it generates FIFO empty and almost empty flags which in turn are used to
prevent any spurious data read. For example if a read request comes when FIFO is empty
then Read Control Logic stalls the read from the memory till the time fifo_empty flag gets
de-asserted. It intimates the stalling of read to the requestor by not asserting rdata_valid in
response to the read request.

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 Fig:- Circular Queue

MEMORY ARRAY :

Memory Array is an array of flip-flops which stores data. Number of data words that the
memory array can store is often referred as DEPTH of the FIFO. Length of the data word is
referred as WIDTH of the FIFO. Besides flop-array it comprises read and write address
decoding logic. The functionality of Memory Array is relatively straight forward as
described below:

1.If write_enable signal is high DATA present on write_data is written into the row pointed
by write_addr on the next rising edge of the clock signal clk. Note that is high and FIFO is
not full to avoid any data corruption.

2. If read_enable signal is high the DATA present in the row pointed by read_addr is sent
onto the read_data bus on the next rising edge of the clock signal clk. Note that read_enable
is asserted only when read_req is high and FIFO is not empty to avoid any spurious data
being sent to the requestor.

3. It can handle simultaneous read and write enables as long as their addresses do not match.

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FULL AND EMPTY FLAG GENERATION :

FIFO full and almost full flags are generated by Write Control Logic whereas empty and
almost empty flags are generated by Read Control Logic. FIFO almost full and almost empty
flags are generated to intimate the source and the requestor about impending full or empty
conditions. The almost full and almost empty levels are parameterized. It is important to note
that read and write pointers point to the same memory location at both full and empty
conditions. Therefore, in order to differentiate between the two one extra bit is added to read
and write pointers. For example if a FIFO has depth of 256 then to span it completely 8-bits
will be needed. Therefore with one extra bit read and write pointers will be of 9-bits. When
their lower 8-bits point to same memory location their MSBs are used to ascertain whether it
is a full condition or empty condition. In empty conditions the MSBs are equal whereas in
full condition MSBs are different.

Switch debouncing

When we press a pushbutton or toggle switch or a micro switch, two metal parts come into
contact to short the supply. But they don’t connect instantly but the metal parts connect and
disconnect several times before the actual stable connection is made. The same thing happens
while releasing the button. This results the false triggering or multiple triggering like the
button is pressed multiple times. Its like falling a bouncing ball from a height and it keeps
bouncing on the surface, until it comes at rest. Software debouncing is method to get rid of
bounces in the circuit. The basic principle is to sample the switch signals and filter out
glitches if any. There are two methods for software debouncing.

 Using counters
 Using shift registers

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Seven Segment Display

An LED or Light Emitting Diode, is a solid state optical pn-junction diode which emits light
energy in the form of photons. The emission of these photons occurs when the diode junction
is forward biased by an external voltage allowing current to flow across its junction, and in
Electronics we call this process electroluminescence. Each of the seven LEDs is called a
segment because when illuminated the segment forms part of a numerical digit (both Decimal
and Hex) to be displayed. An additional 8th LED is sometimes used within the same package
thus allowing the indication of a decimal point, (DP) when two or more 7-segment displays
are connected together to display numbers greater than ten.

Fig:-7 segment connection on Nexys-4

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Verilog code for Synchronous FIFO

`timescale 1ns / 1ps

Test bench

`timescale 1ns / 1ps

Simulation result for FIFO MEMORY

Advantage of Synchronous FIFO

(1) Synchronous FIFO have retransmit feature which allow board which is sending data
to re-transmit data when error occurs.

(2) FIFO’s are used to safely pass data between two asynchronous clock domains. In
System-on-Chip designs there are components which often run on different clocks.

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Application areas of FIFO memory

 Connection of Peripherals to Processors

 Block Transfer of Data
 Programmable Delay
 Collecting Data Before and After an Event

Conclusion
The design of synchronous fifo memory is studied and also verified on 7segment
display of Nexys-4 DDR for multiple read and writes operations in a single clock
domain. and generating fifo full and empty conditions. Here we have designed,
simulated and synthesized a memory using register file

References

1. D. Wyland. New features in synchronous FIFOs. InProceedings of WESCON

’93,pages 580–585, September 1993.
2. HoSuk Han, Kenneth S. Stevens, “Clocked and AsynchronousFIFO
Characterization and Comparison”, Electrical and Computer Engineering,
University of Utah.
3. http://www.ti.com/lit/an/scaa042a/scaa042a.pdf.
4. Verilog HDL:A Guide to Digital Design and Syntesis by Samir Palnitkar.
5. FPGA PROTOTYPING BY VERILOG EXAMPLES by PONG P.CHU.

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