2023 IEEE 2nd International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA)

The Principle and Applications of Asynchronous

FIFO
2023 IEEE 2nd International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA) | 978-1-6654-6253-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/EEBDA56825.2023.10090696

Zixu Hao† Lingxi Liu† Birong Tian*, †

Department of Informatics, Beijing International School of Nanjing College of Science, Wuhan University
University of Technology Yuhuatai High School of Technology, Wuhan, 430000, China
Beijing, 100083, China Nanjing, 210019, China 631301100227@mails.cqjtu.edu.cn
*Corresponding author
†
These authors contribute equally.

Abstract—With the rapid development of integrated circuits, II. THE DEFINITION AND PRINCIPLE OF FIFO
a complete system of integrated Circuits contains multiple
clocks in a chip. Under the control of different clock domains, A. Definition of FIFO
data can become metastable state between transfers or storage. In the system design, when the input data rate and output
This paper describes one of the effective methods to solve the data rate do not match, FIFO is used as a temporary storage
problem about the metastable state, the method is asynchronous
unit. Additionally, synchronization across several clock
FIFO. We study Synchronous FIFO and Asynchronous FIFO in
domains is accomplished using FIFO. In reality, data transfer
this paper. The article analyses the reasons for the emergence of
sub-stability metastable state and how to use the Gray Code to
across different time domains will be necessary [2]. FIFO not
solve metastable state problems effectively. We can generate only serves as a temporary data storage unit, but also plays a
empty/full status bits via Gray Code pointer, it can effectively role in data synchronization. When the data bit width does
reduce the probability of metastable state. This paper has the not match between the input data path and the output data
significance of guiding the use of FIFO. path, it can also be used in the data bit width adjustment
circuit.
Keywords—Asynchronous FIFO, Metastable state, Gray Code
B. Synchronous FIFO
I. INTRODUCTION The clock of the data writing FIFO and the clock of the
FIFO simply means First in First out. Due to the rapid data reading FIFO are synchronous. FIFO operates on the
development of microelectronics technology, the new principle of dual port RAM. The FIFO will generate an empty
generation of FIFO chip capacity is getting larger and smaller, or full signal indicating the current state. If it's full, you can't
the price is getting cheaper and cheaper. Because of its write any more data into it, and if it's empty, you can't read it
flexibility, convenience, and efficiency, FIFO chips, a new out.
form of large-scale integrated circuit, are being utilized C. Asynchronous FIFO
increasingly frequently in high-speed data collection, high-
When data is read from one clock domain and written to
speed data processing, high-speed data transmission, and
the FIFO from a different clock domain, this is known as
multi-machine processing systems. In the next chapters, we
asynchronous FIFO. Data transport across clock domains is
give the difference between the synchronous and the
a major use for asynchronous FIFO. We can opt to use two-
asynchronous FIFO, especially the design and potential
stage flip-flop synchronization [3], which is difficult for
problems of the asynchronous FIFO, including the
multi-bit variable signals, for single-bit data processing over
metastable of it. The last part of the passage is about the
the clock domain. And asynchronous FIFO is better able to
principle of the Gray code and its application [1].
address this issue. The operation of an asynchronous FIFO
In the second part we study FIFO, FIFO is divided into read or write pointer. The storage location to be written to is
synchronous FIFO and asynchronous FIFO, and they can be always indicated by the write pointer. The write pointer in a
classified according to the clock domain when the FIFO is write operation increases by 1 to point to the following
working. When the input and output are in different clock storage location to be written once data has been written to
domains, FIFO plays a synergistic role, and asynchronous the storage location.
FIFO can be used. If the input and output bus are in the same
Comparably, the read pointer always directs attention to
clock domain, FIFO plays the role of cache, this time to use
the current data position in the FIFO that must be read. The
synchronous FIFO. Additionally, in a synchronous FIFO,
FIFO is empty and the pointer is cleared after a reset. The
both write and read operations use the same clock. Data flows
read pointer currently links to incorrect data. The read pointer
and associated control logic are processed and worked in the
still points to the first data storage place in the FIFO when
same clock dom in Synchronous FIFO are used to store data
the first data is written, the null indicator signal is cleared, the
temporarily, where write and read operations can occur
write pointer accumulates, and the data is immediately
simultaneously or at different times. Since only one clock is
visible in the read data port and ready to be read.
used in the synchronous FIFO, its control logic is much
simpler than that of the asynchronous FIFO.. III. IMPLEMENTATION OF SYNCHRONOUS FIFO
In the synchronous FIFO, both write and read operations
use the same clock, data flow and control logic are worked in
the same clock domain. The synchronous FIFO is used to

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store data temporarily, so we can use write or read operations the data has been written to the location the write pointer
in the same time or in the different time. We also require the points to, the write pointer adds one and then points to the
signals write en, read en, write data, read data, fifo full, and following location. The read pointer similarly constantly
fifo empty in addition to read pointers and write pointers.The displays the location that will be read next. When it resets,
signals write en and read en determine whether it is permitted the FIFO is empty and the pointer is cleared. After the initial
to write or read data.The words "write data" and "read data" data is put to the FIFO, the read pointer points to that position.
refer to the data that will be written to and read from the FIFO, The date will immediately appear in the read data port,
respectively[4].It can be filled or empty by using the fifo full waiting to be read.
and fifo empty symbols. Don't post data to a full FIFO and
don't receive data from an empty FIFO is a key synchronous B. Judgment of empty and full state
FIFO principle.We can use the address pointer to check if the The FIFO is empty and has the same read and write
FIFO is full. The address pointer is shown in figure 1. pointers when we read the last data in it[6].The FIFO fills up
when we write a lot of data in it, and the write pointer
becomes identical to the read pointer. We are unable to
distinguish between two scenarios in which the read and
write pointers are identical. We can add an extra bit to every
one of the two pointers to fix this issue. When the write
pointer increase to the maximum address of the FIFO, a carry
signal will be written in the extra bit, and the rest will be
cleared. The same is reading pointers. So if the highest extra
bits of the two pointers are different, that means the FIFO is
full. If the highest extra bits and the rest bits of the two
pointers are same, that means the FIFO is empty.
V. THE KEY TECHNICAL ISSUES OF ASYNCHRONOUS FIFO
DESIGN

Figure 1. The address pointer A. The emergence of metastable state and its solution
Registers in digital integrated circuits must conform to
At first, both the read pointer and the write pointer are setup time and holdup time requirements. The setup time is
pointing at the same address. With each write to the data and the amount of time before the clock is reset during which the
each read of the data, the write address pointer and read data input must still be accurate. The holdup time is the
address pointer are subsequently increased by 1. Once the amount of time, in milliseconds, that the data input must
read address pointer overtakes the write address pointer, the remain valid after the clock has reset. So long as there are
FIFO is empty.The write address pointer surpasses the read asynchronous components in the system, metastable state just
address pointer once again when the FIFO is full. The new can't be avoided. On account of asynchronous circuits always
address pointer is shown in figure 2. have two clock signals, when the sensitive edges of the two
clock signals are very close to each other and exceed the
allowed limit ,the data signal will be instability, metastable
state is then created.
To solve this problem, we can use two-stage synchronizer
and Gray Code Counter[7]. The easiest way is to use two-
stage synchronizer. If we use two-stage synchronizer
continuous locking two beats of Input signals in different
clock domains, the first trigger latches to an unstable signal.
after one clock cycle, the unstable signal is likely to stabilize
at definite value 0 or 1. The second trigger will get a stable
signal when it locks the signal.
B. Principle of handshake Protocol
In order to prevent metastable state, we can use
handshake protocol to complete Cross-clock domain data
Figure 2. The new address pointer transfer. When we use handshake protocol[8],there are two
signals named req and ack. Prior to transmitting a valid
The synchronous FIFO has only one clock domain [5], so request signal to the receiving domain, the sending domain
we use natural binary address to judge FIFO is empty or full. loads the data into the bus. After a valid req signal is detected,
When FIFO's read and write pointers are identical, it is either the receive domain latches the data bus, and once reading is
empty or full. So we need a extra bit to distinguish whether it complete, a valid ack signal is provided. Following the
is empty or full. detection of a valid ack signal, the sending domain will
IV. ASYNCHRONOUS FIFO STATE DETERMINATION DESIGN revoke the current req signal, and the receiving domain will
withdraw the ack signal when the req signal is detected. After
A. The process of generating read/write pointers that , a completion handshake communicate is finished.
We have two pointers in Asynchronous FIFO, one is VI. A SYSTEM ABOUT THE GRAY CODE
write pointer, another is read pointer. In a write operation, the
write pointer always points to the following location. Once Obviously, in the application of asynchronous FIFO, the

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handshake synchronization will result in a slow transfer rate. make deviation. To accelerate the multi-bit Gray code
A more suitable pointer counting scheme is to use a Gray counter and make the operation stable, we divide the large
Code[9] scheme. A Gray Code, or typical Binary Gray Code, counter into a combination of several small counters [11].
is a set of integers where any two adjacent codes only differ
by one binary digit. The coding technique known as gray VII. CONCLUSION
code is trustworthy and minimizes errors. Absolute encoding In this paper, we study Synchronous FIFO and
is used, and the code is a single-step self-complement with Asynchronous FIFO. Firstly we get to know what is FIFO
reflective and cyclic properties. When fetching numbers at and how the FIFO works. Then we discussed the emergence
random, its cyclic and one-step properties completely rule of metastable state and its solution. To solve the problem of
out the potential of catastrophic errors. Features make metastable state, we can use two-stage synchronizer and
negation very convenient. Gray Code Counter. To improve the traditional generation
A. Gray Code encoding methods method of empty/full flag bit , we can add an extra bit to each
of the two pointers, this extra bit can help us distinguish the
Although the natural binary number can be converted into empty FIFO and full FIFO. At last we introduce the Gray
an analog signal by Digital-to-Analog converter, in some Code. Through the above study, we can conclude that
cases, it will produce a large pulse spike. For example, in Asynchronous FIFO are more widely used than synchronous
8421 binary cording rule, the number “0111” will turn into FIFO because it is more common for data to be transferred in
“1000”, with 4 digit change at once. This is not achievable in different time domains. The Gray Code address is better than
real circuits, because an analog circuit must go through an natural binary address when we use Asynchronous FIFO. It
intermediate state like “0110”. This will cause errors and can effectively reduce the probability of metastable state, so
pulse spike. The Gray Code can be used to avoid these errors. that FIFO has a better stability. This paper has the
B. Gray Code and binary numbers conversion significance of guiding the use of FIFO.
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