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Unit 5: Low - Power CMOS Logic Circuits

The document discusses sources of power consumption in CMOS logic circuits including dynamic and static power. Dynamic power is caused by switching activity and charging/discharging capacitance. Static power comes from leakage currents, even when circuits are not switching. Short-circuit current also contributes to dynamic power when both PMOS and NMOS transistors are briefly on during input transitions. Accurate power analysis requires considering these sources at different design stages.

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Vijay Raj
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81 views21 pages

Unit 5: Low - Power CMOS Logic Circuits

The document discusses sources of power consumption in CMOS logic circuits including dynamic and static power. Dynamic power is caused by switching activity and charging/discharging capacitance. Static power comes from leakage currents, even when circuits are not switching. Short-circuit current also contributes to dynamic power when both PMOS and NMOS transistors are briefly on during input transitions. Accurate power analysis requires considering these sources at different design stages.

Uploaded by

Vijay Raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIT 5:

Low – Power CMOS Logic Circuits


INTRODUCTION
• The VLSI low power design problems can be broadly classified into
two:
1) Analysis
2) Optimization
• Analysis problems are concerned about the accurate estimation of
the power or energy dissipation at different phases of the design
process.

• The purpose is to increase confidence of the design with the


assurance that the power consumption specifications are not
violated.

• Analysis techniques differ in their accuracy and efficiency.


Overview of Power Consumption
• The accuracy of analysis depends on the availability of
design information.
• In early design phases, the emphasis is to obtain power
dissipation estimates rapidly with very little available
information on the design.
• In these phases, less accurate analysis results are
expected and tolerated.
• As the design proceeds to reveal more lower-level
details, a more accurate analysis can be performed.
• Here, better accuracy is demanded and longer analysis
time is allowed.
Needs for Low Power VLSI Chips
• Power dissipation of VLSI chips is traditionally a neglected subject.

• In the past, the device density and operating frequency were low
enough that it was not a constraining factor in the chips.

• As the scale of integration improves, more transistors, faster and


smaller than their predecessors, are being packed into a chip.

• This leads to the steady growth of the operating frequency and


processing capacity per chip, resulting in increased power
dissipation.
Overview of Power Consumption
• There are two types of power dissipation in CMOS circuits:
1) Dynamic
2) Static

• Dynamic power dissipation is caused by switching activities of the


circuits. A higher operating frequency leads to more frequent
switching activities in the circuits and results in increased power
dissipation.

• Static power dissipation is related to the logical states of the


circuits rather than switching activities.

• In CMOS logic, leakage current is the only source of static power


dissipation.
• The most significant source of dynamic power
dissipation in CMOS circuits is the charging
and discharging of capacitance.
• The capacitance forms due to parasitic effects
of interconnection wires and transistors.
• Such parasitic capacitance cannot be avoided
and it has a significant impact on the power
dissipation of the circuits.
• We now discuss the generality and applicability of the P = C L V^2f
equation by reviewing the derivation procedure.
• During charging,
• C L V^2 energy is drawn from the energy source, half of which is
dissipated in the charging resistance Rc and the other half is stored in the
capacitor.
• During discharge,
• The energy stored in the capacitor is dissipated as heat in the discharging
resistor Rd.
• Only a few assumptions are made in our derivation:
1. The capacitance C L is constant.
2. The voltage V is constant.
3. The capacitor is fully charged and discharged, i.e., v/to) = 0, v /t]) = V,
v c(t2) = 0.
Short-circuit Current in CMOS Circuit
• Another component of power dissipation also caused by signal switching
called short-circuit power.
1)Short-circuit Current of an Inverter

• When the input signal level is above Vtn' the N-transistor is turned on.
Similarly, when the signal level is below Vtp' the P-transistor is turned on.

• When the input signal Vi switches, there is a short duration in which the
input level is between V tn and Vtp and both transistors are turned on.
This causes a short-circuit current from Vdd to ground and dissipates
power.

• The electrical energy drawn from the source is dissipated as heat in the P
and N -transistors.
A CMOS inverter and its transfer
curve
The shape of the short-circuit current curve is
dependent on several factors:

1. The duration and slope of the input signal.


2. The I-V curves of the P and N transistors, which
depend on their sizes, process technology,
temperature, etc.
3. The output loading capacitance of the inverter.
Short-circuit current of a CMOS
inverter during input transition
Short-circuit Current Variation with Output
Load
Fig. Total current under varying output capacitance
Effects of increasing output loading
capacitance
Short-circuit Current Variation with
Input Signal Slope
CMOS Leakage Current
• Reverse Biased PN-junction
• The first source of leakage current occurs when the source or drain of an
N-transistor (P-transistor) is at Vdd (Gnd}.

• PN-junctions are fonned at the source or drain of transistors because of a


parasitic effect of the bulk CMOS device structure.

• Subthreshold Channel Leakage


• The second source of leakage current is the subthreshold leakage through
a MOS device channel. Even though a transistor is logically turned off,
there is a non-zero leakage current through the channel at the microscopic
level.

• This current is known as the subthreshold leakage because it occurs when


the gate voltage is below its threshold voltage.
Static Current
• CMOS circuits are not supposed to consume
static power from constant static current flow.
All non-leakage current in CMOS circuits
should only occur in transient when signals
are switching.
• However, there are times when deviations
from CMOS style circuit design are necessary.
• Pseudo NMOS circuit is not used on random logic.
• For special circuits such as PLAs or Register Files, it may be
useful due to its efficient area usage.
• In such a circuit, there is a constant current flow from Vdd to
Gnd which dissipates power.
• This is an example where power is traded for area efficiency.

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