Unit-3

• In order to develop techniques for minimizing power dissipation, it is essential

to identify various sources of power dissipation and different parameters
involved in each of them.
• Power dissipation may be specified in two ways.
• One is maximum power dissipation, which is represented by “peak instantaneous
power dissipation.”
• Peak instantaneous power dissipation occurs when a circuit draws maximum power,
which leads to a supply voltage spike due to resistances on the power line.
• Glitches may be generated due to this heavy flow of current and the circuit may
malfunction, if proper care is not taken to suppress power-line glitches.
• The second one is the “average power dissipation,” which is important in the
context of battery-operated portable devices.
• The average power dissipation will decide the battery lifetime.
• Static power dissipation takes place continuously even if the inputs and outputs do
not change.
• For some logic families, such as nMOS and pseudo-nMOS, both pull-up and pull-
down devices are simultaneously ON for low output level causing direct current (DC)
flow.
• This leads to static power dissipation..
Power and Energy:

 Power dissipation is essentially the rate at which energy is drawn from the
power supply, which is proportional to the average power dissipation.
 Power dissipation is important from the viewpoint of cooling and packaging of
the integrated circuit (IC) chips.
 On the other hand, energy consumed is important for battery-driven portable
systems. As power dissipation is proportional to the clock frequency, to reduce
power dissipation by half we may reduce the clock frequency by half.
 Although this will reduce the power dissipation and keep the chip cooler, the time
required to perform a computation will double that of the previous case. In this case,
the energy is drawn from the battery at half the rate of the previous case.
 But, the total energy drawn from the battery for performing a particular computation
remains the same.
 The height of the graphs represents the power and the area under the curve
represents the energy. Here, the same energy is drawn for different average power
dissipation.
 Dynamic power dissipation:
 In CMOS circuits, power dissipation can be divided into two broad categories:
dynamic and static.
 Dynamic power dissipation in CMOS circuits occur when the circuits are in working
condition or active mode, that is, there are changes in input and output conditions
with time. In this section, we introduce the following three basic mechanisms
involved in dynamic power dissipation:
 Short-circuit power: Short-circuit power dissipation occurs when both the nMOS
and pMOS networks are ON. This can arise due to slow rise and fall times of the
inputs.
 Switching power dissipation: As the input and output values keep on changing,
capacitive loads at different circuit points are charged and discharged, leading to
power dissipation. This is known as switching power dissipation
 Glitching power dissipation: Due to a finite delay of the logic gates, there are
spurious transitions at different nodes in the circuit.
 Apart from the abnormal behavior of the circuits, these transitions also result in
power dissipation known as glitching power dissipation.Static power dissipation
occurs due to various leakage mechanisms
Static power dissipation:
 Static power dissipation occurs due to various leakage mechanisms.Reverse-bias p–
n junction diode leakage current
 Reverse-biased p–n junction current due to the tunneling of elections from the
valence bond of the p region to the conduction bond of the n region, known as band-
to-band-tunneling current.Sub-threshold leakage current between source and drain
when the gate voltage is less than the threshold voltage Vt
 Oxide-tunneling current due to a reduction in the oxide thicknessGate current due to
a hot-carrier injection of elections Gate-induced drain-leakage (GIDL) current due
to high field effect in the drain junction.Channel punch-through current due to close
proximity of the drain and the source in short-channel devices
Short-Circuit Power Dissipation:

• When there are finite rise and fall times at the input of CMOS logic gates, both
pMOS and nMOS transistors are simultaneously ON for a certain duration, shorting
the power supply line to ground. This leads to current flow from supply to ground.
• Short-circuit power dissipation takes place for input voltage in the range Vtn < Vin
< Vdd − | Vtp |, when both pMOS and nMOS transistors turn ON creating a
conducting path between Vdd and ground (GND).
• To estimate the average short-circuit current.It is assumed that τ is both rise and fall
times of the input (τr =τ f = τ ) and the inverter is symmetric, i.e., βn = βp = β and
Vtn = − Vtp = V t .The mean short-circuit current of the inverter having no load
attached to

As the nMOS transistor is operating in the saturation region,

Switching Power Dissipation
• There exists capacitive load at the output of each gate. The exact value of
capacitance depends on the fan-out of the gate, output capacitance, and
wiring capacitances and all these parameters depend on the technology
generation in use.
• As the output changes from a low to high level and high to low level, the
load capacitor charges and discharges causing power dissipation.
• This component of power dissipation is known as switching power
dissipation.
Fig:Dynamic Power Dissipation Model
 For some input combinations, the pMOS network is ON and nMOS network
is OFF.In this state, the capacitor is charged to Vdd by drawing power from
the supply.
 For some other input combinations, the nMOS network is ON and pMOS
network is OFF,In this state, the capacitor discharges through the nMOS
network. For simplicity, let us assume that the CMOS gate is an inverter.
During the transition of the output from 0 to Vdd, the energy drawn from the
power supply is given by

where i( t) is an instantaneous current drawn from the supply voltage Vdd,

and it can be expressed as

Regardless of the waveform and time taken to charge the capacitor,

C L Vdd 2 is the energy drawn from the power supply for 0 to Vdd transition
at the load capacitance.
Part of the energy drawn from the supply is stored in the load capacitance

This implies that half of the energy is stored in the capacitor, and the
remaining half (1/ 2)CL Vdd2 is dissipated in the pMOS transistor network.
 Switching power reduces by 56 %, if the supply voltage is reduced from 5 to
3.3 V, and if the supply voltage is lowered to 1 V, the switching power is
reduced by 96 % compared to that of 5V.
 This is the reason why voltage scaling is considered to be the most dominant
approach to reduce switching power.

Switching Power Dissipation

• Dynamic Power for a Complex Gate
• Reduced Voltage Swing
• Internal Node Power
• Switching Activity
• Switching Activity of Static CMOS Gates
• Inputs Not Equiprobable
• Mutually Dependent Inputs
• Transition Probability in Dynamic Gates
• Power Dissipation due to Charge Sharing
Dynamic Power for a Complex Gate:
 For an inverter having a load capacitance CL, the dynamic power expression
is C L Vdd2 f. Here, it is assumed that the output switches from rail to rail and
input switching occurs for every clock.
 This simple assumption does not hold good for complex gates because of
several reasons. First, apart from the output load capacitance, there exist
capacitances at other nodes of the gate.
 As these internal nodes also charge and discharge, dynamic power
dissipation will take place on the internal nodes. This leads to two
components of dynamic power dissipation-load power and internal node
power.
 Second, at different nodes of a gate, the voltage swing may not be from rail
to rail. This reduced voltage swing has to be taken into consideration for
estimating the dynamic power.
 Finally, to take into account the condition when the capacitive node of a
gate might not switch when the clock is switching, a concept known as
switching activity is introduced.
 Reduced Voltage Swing:

 There are situations where a rail-to-rail swing does not take place on a
capacitive node. This situation arises in pass transistor logic and when the
pull-up device is an enhancement-type nMOS transistor in nMOS logic
gates.In such cases, the output can only rise to Vdd − Vt.This situation also
happens in interval nodes of CMOS gates.
 Instead of C L Vdd2 f for full-rail charging, the energy drawn from power
supply for charging the capacitance to ( Vdd − Vt) is given by

• Internal Node Power:

Fig:Switching nodes of a three-input NAND gate

 Apart from the output capacitance CL, two capacitances C1 and C2 are
shown in two interval nodes of the gate. For input combination 110, the
output is “1” and transistors Q3, Q4, and Q5 are ON.
 All the capacitors will draw energy from the supply. Capacitor CL will
charge to Vdd through Q3, capacitor C1 will charge to ( Vdd − Vt) through
Q3 and Q4. Capacitor C2 will also charge to ( Vdd − Vt) through Q3, Q4,
and Q5. For each 0-to-Vdd transition at an internal node, the energy drawn
is given by

Where Ci is the internal node capacitance and Vi is internal voltage swing

at node i.

• Switching Activity:
• For a complex logic gate, the switching activity depends on two factors—
the topology of the gate and the statistical timing behavior of the circuit.
• To handle the transition rate variation statistically, let n( N) be the number
of 0-to-Vdd output transitions in the time interval [0,N].
• Total energy EN drawn from the power supply for this interval is given by

 Where α0 is the switching activity at the output node, αi is the switching

activity on the ith internal node, and f is the clock frequency. Here, it is
assumed that there are k internal nodes.
Switching Activity of Static CMOS Gates:
• The switching activity at the output of a static CMOS gate depends strongly
on the function it realizes.
• It is assumed that the inputs are independent to each other and the
probability of occurrence of “0” and “1” is same, let P0 be the probability
that the output will be “0” and P1 is the probability that the output will be
“1.” Then,

• For an n-input gate, the total number of input combinations is 2n.

• Out of 2n combinations in the truth table, let n0 be the total number of
combinations for which the output is 0 and n1 is the total number of
combinations for which the output is “1,” then

• For example, consider a two-input NAND gate with the truth table given in
Table. In this case,

• For NAND/NOR gates, the switching activity decreases with the increase in
the number of inputs.
• On the other hand, the switching activity at the output of an EXOR gate in
1/4, which is independent on the number of inputs. Output activities for
different gates are shown in Table.
The variation of the switching activity at the output of NAND, NOR, and EX-OR
gates with the increase in the number of inputs is shown in Fig.

• Inputs Not Equiprobable:

• we have assumed that the inputs are independent of each other and
equiprobable. But, inputs might not be equiprobable.
• In such cases, the probability of transitions at the output depends on the
probability of transitions at the primary inputs.
• Let us consider a two-input NAND gate with two inputs A and B having
mutually independent signal probabilities of PA and PB.
• The probability of logical “0” at the output is P0 = PAPB and the
probability of “1” at the output is P1 = (1− P0 ) = (1− PAPB ) .

• In a similar manner, the switching activity of a two-input NOR gate (output

is 1 when both the inputs are 0) is
• Mutually Dependent Inputs;
• When a multilevel network of complex gates are considered, the inputs to a
gate at a particular stage might not be independent.
• This can happen because the signal from one input may propagate through
multiple paths and again recombine at a particular stage.
This problem of re-convergent fan-out is shown with the help of a simple
example given in Fig.
 Fig:Three different realizations for the six-input OR function
 Provides details of various gates used for the realization of the three
implementations.
 The table provides the area in terns of unit area called cell grid, output and
input capacitances, and delay in terms of output capacitance C0 in
picofarad.For all transistors, Wp = 2Wn = 10 μm.

• Transition Probability in Dynamic Gates:

• The logic style has a strong influence on the node transition probability.
• For static CMOS, we calculated the transition probability as P0 P1= P0(1- P0
). In the case of dynamic gates, the situation is different.
• As we have seen, in the case of domino or NORA logic styles, the output
nodes are pre-charged to a high level in the Pre-charge phase and then are
discharged in the evaluation phase, depending on the outcome of
evaluation.
• In other words, the output transition probability will depend on the signal
probability P0, i.e.,

• where P0 is the probability for the output is in the zero state. For n
independent inputs to a gate

• where N0 is the number of zero entries in the truth table

 Gives the output transition probabilities for NAND, NOR, and inverter.
 Compared to the static CMOS, transition probabilities are more, because the
output is always pre-charged to 1, i.e., P1 = 1. It may be noted that the
switching activity for NAND and NOR gates is more in the dynamic gates
than their static gate counterparts.
Power Dissipation due to Charge Sharing:
• Moreover, in the case of dynamic gates, power dissipation takes place due to
the phenomenon of charge sharing even when the output is not 0 at the time
evaluation, i.e., the output load capacitance is not discharged, but part of the
charge of the load capacitance might get redistributed leading to a reduction
in the output voltage level.
In the next pre-charge period, the output is again pre-charged back to Vdd
The power transferred from the supply is

Glitching Power Dissipation:

• In the power calculations so far, we have assumed that the gates have
zero delay.
• In practice, the gates will have finite delay and this delay will lead to
spurious undesirable transitions at the output.
• These spurious signals are known as glitches.
• In the case of a static CMOS circuit, the output node or internal nodes
can make undesirable transitions before attaining a stable value.
• If the inputs ABC change value from 101 to 000, ideally for zero gate delay
the output should remain at the 0 logic level.
• However, considering unit gate delay of the first gate stage, output O1 is
delayed compared to the C input
• As a consequence, the output switches to 1 logic level for one gate delay
duration.
• This transition increases the dynamic power dissipation and this component
of dynamic power is known as glitching power.
• Usually, cascaded circuits as shown in Fig. a exhibit high glitching
power.The glitching power can be minimized by realizing a circuit by
balancing delays, as shown in Fig. b.
Leakage Power Dissipation:
• When the circuit is not in an active mode of operation, there is static power
dissipation due to various leakage mechanisms.
• In deep-submicron devices, these leakage currents are becoming a
significant contributor to power dissipation of CMOS circuits.

• I1 is the reverse- bias p–n junction diode leakage current;

• I2 is the reverse-biased p–n junction current due to tunneling of electrons
from the valence bond of the p region to the conduction bond of the n
region;
 • I3 is the sub-threshold leakage current between the source and the drain
when the gate voltage is less than the threshold voltage Vt;
• I4 is the oxide-tunneling current due to a reduction in the oxide thickness;
• I5 is gate current due to hot-carrier injection of elections;
• I6 is the GIDL current due to a high field effect in the drain junction; and
I7 is the channel punch-through current due to the close proximity of the
drain and the source in short-channel devices.
p–n Junction Reverse-Biased Current:

Fig: nMOS Inverter and its Physical Structure

 Let us consider the physical structure of a CMOS inverter shown in Fig.
 As shown in the figure, source–drain diffusions and n-well diffusions form
parasitic diodes in the bulk of silicon substrate. As parasitic diodes are
reverse-biased, their leakage currents contribute to static power dissipation.
The current for one diode is given by

where Js is the reverse saturation current density (this increases with

temperature),Is is the AJs, Vd is the diode voltage, n is the emission coefficient of
the diode (sometimes equal to 1), q is the charge of an electron (1.602 × 10−19),
K is the Boltzmann constant (1.38 × 10−23 j/k), T is the temperature in K, VT
=KT/q is known as the thermal voltage. At room temperature, VT =26 mV
  The reverse saturation current per unit area is defined as the current density
Js, and the resulting current is approximately IL = AD · Js, where AD is
area of drain diffusion.
For a typical CMOS process, Js ≈ 1− 5pA/μm2 at room temperature, and the AD
is about 6 μm2 for a 1.0-μm minimum feature size.
The current for one diode is given by

The total static diode leakage current for n devices is given by

The total static power dissipation for n devices is equal to

Then, the total static power dissipation due to diode leakage current for one million
transistors is given by

• This is small enough to make any significant impact on the power

dissipation when the circuit is in a normal mode (active) of operation.

Band-to-Band Tunneling Current:

  When both n regions and p regions are heavily doped, a high electric field
across a reverse biased p–n junction causes a significant current to flow
through the junction due to tunneling of electrons from the valence band of
the p region to the conduction band of n region.
 This is illustrated in Fig. 6.19. It is evident from this diagram that for the
voltage drop across that junction should be more than the band gap.
The tunneling current density is given by

where m* is the effective mass of electron, E is the elective field at the junction, q
is the electronic charge, and h is the reduced Planck’s constant (1/2π times).

• where Na and Nd are the doping in the p and n side, respectively. εsi is the
permittivity of silicon and Vbi is the built-in voltage across the junction.
• High doping concentrations and abrupt doping profiles are responsible for a
significant band-to-band tunneling BTBT current in scaled devices through
the drain–well junction.

Subthreshold Leakage Current:

 • The subthreshold leakage current in CMOS circuits is due to carrier
diffusion between the source and the drain regions of the transistor in
weak inversion, when the gate voltage is below Vt.
• The behavior of an MOS transistor in the subthreshold operating region is
similar to a bipolar device, and the subthreshold current exhibits an
exponential dependence on the gate voltage.
• The amount of the subthreshold current may become significant when the
gate-to-source voltage is smaller than, but very close to, the threshold
voltage of the device.
The sub-threshold current expression as given by the BSIM3 model is stated
below:

Where m is the sub-threshold swing coefficient, VT = KT/q is the thermal voltage,

μ0 is the zero bias mobility, cox is the gate oxide capacitance per unit area, wdm is
the maximum depletion layer width, and tox is the gate oxide thickness.
• The inverse of the slope of the log10( Ids) versus Vgs characteristic is called
the sub-threshold slope (St), which is given by the following relationship

 Where Cdm is capacitance of the depletion layer and Cox is oxide

capacitance. Here, St is measured in mVs per decade of the drain current.
 Typical values St for a bulk CMOS process can range from 70 to 120
mV/decade. As a low value of St is desirable, the gate oxide thickness tox is
reduced or the doping concentration is lowered to achieve this.
Sub-threshold Leakage Current:
• Various mechanisms which affect the sub-threshold leakage current are:
• Drain-induced barrier lowering (DIBL)
• Body effect
• Narrow-width effect
• Effect of channel length and Vth roll-off
• Effect of temperature
Drain-induced barrier lowering (DIBL):
• For long-channel devices, the sources and drain region are separated far
apart and the depletion regions around the drain and source have little effect
on the potential distribution in the channel region. So, the threshold voltage
is independent of the channel length and drain bias for such devices.
• However, for short-channel devices, the source and drain depletion width in
the vertical direction and the source drain potential have a strong effect on a
significant portion of the device leading to variation of the subthreshold
leakage current with the drain bias. This is known as the DIBL effect.
• Because of the DIBL effect, the barrier height of a short-channel device
reduces with an increase in the subthreshold current due to a lower threshold
voltage.
• DIBL occurs when the depletion regions of the drain and the source interact
with each other near the channel surface to lower the source potential
barrier.
•
Figure shows the lateral energy band diagram at the surface versus
distance from the source to the drain.
• It is evident from the figure that DIBL occurs for short-channel lengths
and it is further enhanced at high drain voltages.
• Ideally, the DIBL effect does not change the value of St, but does lower
Vth.
Body Effect:
• As a negative voltage is applied to the substrate with respect to the
source, the well-to-source junction, the device is reverse-biased and
bulk depletion region is widened.
• This leads to an increase in the threshold voltage. This effect is known
as the body effect.
• The threshold voltage equation given below gives the relationship of the
threshold voltage with the body bias
 Where Vfb is the flat-band voltage, Na is the doping density in the
substrate,

• The variation of the threshold voltage with respect to the substrate bias
dVth/dVbs is referred to as the substrate sensitivity:

• Taking into consideration all the three effects, e.g., weak inversion,
DIBL, body effect and subthreshold leakage can be modeled as

Narrow-Width Effect:
• The width of a gate, particularly when it becomes narrow, affects the
threshold voltage as shown in Fig.
• The reduction in threshold voltage also leads to an increase in the
subthreshold leakage current (Fig.
Vth Roll-Off:
• As the channel length is reduced, the threshold voltage of metal–oxide–
semiconductor field-effect transistor (MOSFET) decreases.
• This reduction of channel length is known as Vth roll-off.
• Figure shows the reduction of threshold voltage with a reduction in channel
length.This effect is caused by the proximity of the source and drain regions
leading to a 2D field pattern rather than a 1D field pattern in short-channel
devices.

• The bulk change that needs to be inverted by the application of gate voltage
is proportional to the area under the trapezoidal region, shown in Fig. 6.27,
given by QB‘ Wdm( L + L) / 2 .
• So, the gate voltage has to invert less bulk charge to turn the transistor on
leading to more band bending in the Si–SiO2 interface in the short-channel
device compared to long-channel devices. As a consequence, the threshold
voltage is lower for a short-channel device.
• Moreover, the effect of the source–drain depletion region is more severe for
high drain bias voltage. This results in a further decrease in threshold
voltage and larger subthreshold current.
Temperature Effect:
• There is a strong dependence of threshold voltage on temperature.

• The equation indicates that the

subthreshold slope changes linearly with temperature.
• As the temperature varies from − 50 to + 25 °C in the 0.3-μm technology as
shown in Fig. the IOFF increases from 0.45 to 100 pA, an increase by a
factor of 356, for a 20-μm-wide device (23 fA/μm to 8 pA/μm)..
• The following two parameters are responsible for increases in subthreshold
leakage current:
(i) St increases linearly with temperature.
(ii) The threshold voltage decreases with temperature at the rate of 0.8
mV/°C.
Tunneling Through Gate Oxide:
• Device size scaling leads to a reduction in oxide thickness, which in turn
results in an increase in the field across the oxide. The high electric field
along with low oxide thickness leads to the tunneling of electrons from the
substrate to the gate and vice versa, through the gate.
• The basic phenomenon of tunneling is explained with the help of a heavily
doped n + type poly-silicon gate and a p-type substrate.
• Because of higher mobility, primarily electrons take part in the tunneling
process.An energy band diagram in flat-band condition is shown in Fig.
where Φ is the Si–SiO2 interface barrier height for electrons.
 •
• The energy band diagram changes to that of Fig.b, when a positive bias is
applied to the gate. The electrons at the strongly inverted surface can tunnel
through the SiO2 because of the small width of the potential barrier arising
out of small oxide thickness.

• Similarly, if a negative gate bias is applied, the electrons from the n + poly-
silicon can tunnel through the oxide layer as shown in Fig. c.
• This results in gate oxide-tunneling current, which violates the classical
infinite input impedance assumption of MOS transistors and thus affects the
circuit performance significantly.
Hot-Carrier Injection:
• Electrons and holes near the Si–SiO2 interface can gain sufficient
energy due to the high electric field in short-channel MOSFETs and
cross the interface potential barrier and enter into the oxide layer as
shown in below Fig.
• This phenomenon is known as the hot-carrier injection. Because of the
lower effective mass and smaller barrier height (3.1 eV) for electrons
compared to holes (4.5 eV), the possibility of an injection due to electrons is
more than the holes.
Gate-Induced Drain Leakage:
• Due to a high electric field ( Vdg) across the oxide, a deep depletion region
under the drain overlap region is created, which generates electrons and
holes by band-to band tunneling. The resulting drain to body current is
called GIDL current.

• When the negative gate bias is large ( v, gate at zero or negative voltages
with respect to drain at Vdd), the n + region under the gate can be
depleted and even inverted as shown in Fig.
• As a consequence, minority carriers are emitted in the drain region
underneath the gate. As the substrate is at a lower potential, the minority
 carriers at the drain depletion region are swept away laterally to the
substrate, creating a GIDL current.
• At low drain doping, the electric field is not high enough to cause tunneling.
• At very high drain doping, the depletion width and hence the tunneling is
limited.The GIDL is worse for moderated doping, when the depletion width
and electric field are both considerable
Punch-Through:
• Due to the proximity of the drain and the source in short-channel devices,
the depletion regions at the source–substrate and drain–substrate junctions
extend into the channel.
• If the doping is kept constant while the channel length is reduced, the
separation between the depletion region boundaries decreases. Increased
reverse bias (higher Vds) across the junction further decreases the
separation.
• When the depletion region merge, a majority of the carriers in the source
enter into the substrate and get collected by the drain. This situation is
known as punch-through condition.
• The net effect of punch through is an increase in the subthreshold current.
• Moreover, punch through degrades the subthreshold slope.
• The punch-through voltage VPT estimates the value of Vds for which punch
through occurs at Vgs = 0:

•
where NB is the doping concentration at the bulk, L is the channel length, and
Wj is the junction width.

Supply Voltage Scaling for Low Power:

• The total power dissipation can be represented by the simplified equation:
• Although the dynamic power has three components, the switching power
is the most dominant component.

• The switching power caused by the charging

and discharging of capacitances at

different nodes of a circuit can be optimized by reducing each of the
components such as the clock frequency f, the total switched capacitance
and the supply voltage Vdd.
• Another dynamic power component, the glitching power is often neglected.
• But, it can account for up to 15 % of the dynamic power.The third
component, the short-circuit power, captures the power dissipation as a
result of a short-circuit current, which flows between the supply voltage and
ground (GND), when the CMOS logic gates switches from 0 to 1 or from 1
to 0.This can be minimized by minimizing the rise and fall times.
• The static power dissipation has also three dominant components.
• The most significant among them is the sub-threshold leakage power due to
the flow of current between the drain and source. The second important
component is the gate leakage power due to the tunneling of electrons from
the bulk silicon through the gate oxide potential barrier into the gate.
• In sub-50-nanometer devices, the source–substrate and drain–substrate
reversed p–n junction band-to-band tunneling current, the third
component, is also large.
• From the above discussion, it is quite evident that reducing the supply
voltage, Vdd, is the most effective way to reduce both dynamic and static
power dissipations. The normalized energy, which is equivalent to the
power-delay product (PDP), can be considered as the most appropriate
performance metric for low-power applications.
• Unfortunately, this reduction in power dissipation comes at the expense of
performance.
•
 •

a Variation of normalized energy with respect to supply voltage; b

variation of delay with respect to supply voltage

• The plot shows that the delay increases with the decrease in supply voltage
in a nonlinear manner, and it increases sharply as the supply voltage
approaches the threshold voltage.
• It is essential to devise a suitable mechanism to contain this loss in
performance due to the supply voltage scaling for the realization of low-
power high-performance circuits.
• The loss in performance can be compensated by using suitable techniques at
different levels of design hierarchy, that is, the physical level, logic level,
architectural level, algorithmic level, and system level.
The voltage scaling approaches can be divided into the following four categories:
• Static Voltage Scaling (SVS) In this case, fixed supply voltages are applied
to one or more subsystems or blocks.
• Multilevel Voltage Scaling (MVS) This is an extension of the SVS, where
two or few fixed discrete voltages are applied to different blocks or
subsystems
• Dynamic Voltage and Frequency Scaling (DVFS) :This is an extension of
the MVS, where a large number of discrete voltages are applied in response
to the changing workload conditions of the subsystems.
• Adaptive Voltage Scaling (AVS): This is an extension of the DVFS, where a
close-loop control system continuously monitors the workload and adjusts
the supply voltage.
 Static Voltage Scaling:
• Device Feature Size Scaling (Physical Level Approach)
 Constant Field Scaling
 Constant Voltage Scaling
• Architectural-Level Approaches
 Parallelism for Low Power
 Multi-Core for Low Power
 Pipelining for Low Power
 Combining Parallelism with Pipelining
 Voltage Scaling Using High-Level
Transformations
Device Feature Size Scaling:
• In the first physical-level-based approach, the device feature size is scaled to
overcome the loss in performance.
• Continuous improvements in process technology and photolithographic
techniques have made the fabrication of MOS transistors of smaller and
smaller dimensions to provide a higher packaging density.
• As a reduction in feature size reduces the gate capacitance, this leads to an
improvement in performance.This has opened up the possibility of scaling
device feature sizes to compensate for the loss in performance due to
voltage scaling.
• The reduction of the size, i.e., the dimensions of MOSFETs, is commonly
referred to as scaling. To characterize the process of scaling, a parameter S,
known as scaling factor, is commonly used.
• All horizontal and vertical dimensions are divided by this scaling factor,
S ˃ 1, to get the dimensions of the devices of the new generation technology.
• Obviously, the extent of scaling, in other words the value of S, is decided by
the minimum feature size of the prevalent technology.
• It has been observed that over a period of every 2 to 3 years, a new
generation technology is introduced by downsizing the device dimensions
by a factor of S, lying in the range 1.2–1.5.
• Trends in metal–oxide–semiconductor (MOS) device scaling
•

• It may be noted that the slope of all the curves in this figure is equal to the
scaling parameter S.
• Figure a and b shows the reduction in gate delay for the n-type MOS
(nMOS) and p-type MOS (pMOS) transistor, respectively.
• Figure c shows how gate oxide thickness varies with the scaling of channel
length, whereas Fig.d shows how the supply voltage is scaled with the
scaling of channel length
Basic geometry of an MOSFET and the various parameters scaled by a scaling
factor S.
• It may be noted that all the three dimensions are proportionally reduced
along with a corresponding increase in doping densities.
• There are two basic approaches of device size scaling–constant-field scaling
and constant voltage scaling.
Constant-Field Scaling:
• In this approach, the magnitudes of all the internal electric fields within the
device are preserved, while the dimensions are scaled down by a factor of S.
• This requires that all potentials must be scaled down by the same factor.
• Accordingly, supply and threshold voltages are scaled downproportionately.
This also dictates that the doping densities are to be increased by a factor of
S to preserve the field conditions.

• As a consequence of scaling, various electrical parameters are affected.

• For example, the gate oxide capacitance per unit area increases by a factor
of S as given by the following relationship:

• As both length and width parameters are scaled down by the same factor,
the W/L remains unchanged.
• So, the transconductance parameter Kn is also scaled by a factor S.
• Both linear-mode and saturation-mode drain currents are reduced by a
factor of S, as given below:

• This significant reduction in power dissipation is the most attractive feature

of the constant-field scaling approach:

This leads to the reduction of delay time and the consequent improvement in
performance.
 • Important benefits of constant-field scaling are:
(i) Smaller device sizes leading to a reduced chip size, higher yield, and more
number of integrated circuits (ICs) per wafer,
(ii) Higher speed of operation due to smaller delay
(iii) Reduced power consumption because of the smaller supply voltage and
device currents.
Constant-Voltage Scaling:
• In constant-voltage scaling, all the device dimensions are scaled down by a
factor of S just like constant-voltage scaling. However, in many situations,
scaling of supply voltage may not be feasible in practice.
• For example, if the supply voltage of a central processing unit (CPU) is
scaled down to minimize power dissipation, it leads to electrical
compatibility with peripheral devices, which usually operate at higher
supply voltages.
• It may be necessary to use multiple supply voltages and complicated-level
translators to resolve this problem. In such situations, constant-voltage
scaling may be preferred.
• In a constant-voltage scaling approach, power supply voltage and the
threshold voltage of the device remain unchanged.
• To preserve the charge–field relations, however, the doping densities have
to be scaled by a factor of S2.
Short-Channel Effects:
• Short-channel effects arise when channel length is of the same order of
magnitude as depletion region thickness of the source and drain junctions or
when the length is approximately equal to the source and drain junction
depths.
• As the channel length is reduced below 0.6 μm, the short-channel effect
starts manifesting.
• This leads to an increase in subthreshold leakage current, reduction in
threshold voltage with Vgs, and a linear increase in the saturation current
instead of square of the gate-to-source voltage.
• Moreover, if channel length is scaled down without scaling the supply
voltage (constant-voltage scaling), the electric field across a gate oxide
device continues to increase, creating a hot carrier.
• Hot carriers can cause an avalanche breakdown of the gate oxide.
• It is necessary to restrict the maximum electric field across the gate oxide to
7 MV/cm, which translates into 0.7 V/10 Å of gate oxide thickness.
• For gate oxide thickness of 70 Å, the applied gate voltage should be limited
to 4.9 V for long-term reliable operation.
• However, if voltage scaling is not done along with the scaling of feature size
because of some other design constraints, it will be necessary to use an
appropriate measure to reduce the number of hot carriers.

a Conventional structure; b lightly doped drain structure

• One technique is to use lightly doped drain structure shown in Fig.
• The physical device structure is modified so that the carriers do not gain
energy from the field to become hot carriers.
Of course, the performance of the device is traded to obtain long-term
reliability
Architectural-Level Approaches:
• Architectural-level refers to register-transfer-level (RTL), where a circuit
is represented in terms of building blocks such as adders, multipliers, read-
only memories (ROMs), register files, etc..
• High-level synthesis technique transforms a behavioral-level specification to
an RTL-level realization. It is envisaged that low power synthesis technique
on the architectural level can have a greater impact than that of gate-level
approaches.
• Possible architectural approaches are: parallelism, pipelining, and power
management
 Parallelism for Low Power:
• Parallel processing is traditionally used for the improvement of
performance at the expense of a larger chip area and higher power
dissipation.
• Basic idea is to use multiple copies of hardware resources, such as
arithmetic logic units (ALUs) and processors, to operate in parallel to
provide a higher performance.
• Instead of using parallel processing for improving performance, it can also
be used to reduce power.
• Unfortunately, the savings in power come at the expense of performances
or, more precisely, maximum operating frequency.
This follows from the equation

Parallelism for Low Power:

• 16-bit adder

• Parallel architecture of the 16-bit adder. MUX multiplexer

 Multi-Core for Low Power:
• Four-core Multiplier Architecture. MUX Multiplexer

Pipelining for Low Power:

• Pipelined realization 16-bit adder
 Combining Parallelism with Pipelining:
• Parallel-pipelined realization of 16-bit adder. MUX multiplexer
 Voltage Scaling Using High-Level Transformations:
• For automated synthesis of digital systems, high-level transformations such
as dead code elimination, common sub-expression elimination, constant
folding, in-line expansion, and loop unrolling are typically used to optimize
the design parameters such as the area and throughput .
• These high-level transformations can also be used to reduce the power
consumption either by reducing the supply voltage or the switched
capacitance. loop unrolling can be used to minimize power by voltage
scaling

Fig:a A first-order infinite impulse response (IIR) filter; b directed acyclic

graph (DAG) corresponding to the IIR filter
 •
• Directed acyclic graph (DAG) after unrolling

• Directed acyclic graph (DAG) after unrolling and using distributivity and
constant propagation

Multilevel Voltage Scaling:

• Assignment of multiple supply voltages based on delay on the critical path
Multilevel Voltage Scaling:
Clustered voltage scaling. FF flip-flop

• Distribution of path delays under single supply voltage (SSV) and multiple
supply voltage (MSV)
 • A number of studies have shown that the use of multiple supply voltages
results in the reduction of dynamic power from less than 10 % to about 50
%, with an average of about 40 %.
• It is possible to use more than two, say three or four, supply voltages.
However, the benefit of using multiple Vdd saturates quickly.
• Extending the approach to more than two supply voltages yields only a
small incremental benefit. The major gain is obtained by moving from a
single Vdd to a dual Vdd.
• It has been found that in a dual-Vdd/single-Vt system, the optimal lower Vdd
is about 60–70 % of the original Vdd.
• The optimal supply voltage depends on the threshold voltage Vt of the MOS
transistors as well.
• Challenges in MVS
• Voltage Scaling Interfaces
• Converter Placement
• Floor Planning, Routing, and Placement
• Static Timing Analysis
• Power-Up and Power-Down Sequencing
• Clock Distribution
• Low-Voltage Swing
Dynamic Voltage and Frequency Scaling(DVFS):
• DVFS has emerged as a very effective technique to reduce CPU energy.
• The technique is based on the observation that for most of the real-life
applications, the workload of a processor varies significantly with time and
the workload is bursty in nature for most of the applications.
• The energy drawn for the power supply, which is the integration of power
over time, can be significantly reduced.
• This is particularly important for battery-powered portable systems.
• Basic Approach
• The energy drawn from the power supply can be reduced by using the
following two approaches:
 • Dynamic Frequency Scaling
• Dynamic Voltage and Frequency Scaling
• Dynamic Frequency Scaling:

Four different cases with two different workloads and with voltage and frequency
scaling
DVFS with Varying Work Load:
• The implementation of the DVFS system will require the following
hardware building blocks:
• Variable voltage processor μ( r)
• Variable voltage generator V( r)
• Variable frequency generator f( r)
• Variable voltage processor μ( r)
• The need of a processor which can operate over a frequency range with a
corresponding lower supply voltage range can be manufactured using the
present-day process technology and several such processors are
commercially available.
• Variable voltage processor μ( r)
• Transmeta’s TM 5400 or “Crusoe” processor and Strong ARM processor
are examples of such variable voltage processors.
• Transmeta’s Crusoe processor can operate over the voltage range of 1.65–
1.1 V, with the corresponding frequency range of 700– 200 MHz.
• Variable voltage processor μ( r)
It allows the following adjustments:
• Frequency change in steps of 33 MHz
• Voltage change in steps of 25 mV
• Up to 200 frequency/voltage change per second
• Another processor, Strong ARM, also allows voltage scaling.
• Experimental results performed on Strong ARM 1100 are shown in Fig.
7.26.
• The diagram shows the operating frequency and corresponding supply
voltages for the ARM processor.

• Variable voltage generator V( r):

Block diagram of a direct current (DC)-to-DC converter

• Variable frequency generator f( r)
• The variable frequency is generated with the help of a phase lock loop
(PLL) system.
 • The heart of the device is the high-performance PLL-core, consisting of a
phase frequency detector (PFD), programmable on-chip filter, and voltage-
controlled oscillator (VCO).
• The PLL generates a high-speed clock which drives a frequency divider.
• The divider generates the variable frequency f( r).
• The PLL and the divider together generate the independent frequencies
related to the PLL operating frequency.
• Model for dynamic voltage scaling

Adaptive Voltage Scaling:

• A better alternative that can overcome this limitation is the adaptive voltage
scaling (AVS) where a close-loop feedback system is implemented between
the voltage scaling power supply and delay-sensing performance monitor at
execution time.