List of EDA Tools http://www.csie.ntu.edu.tw/~r93080/EDA_TOOL.

htm

List of EDA Tools, July 2002

Vendor Toolname Description Link
Adelante Techn. A|RT Builder Converts ANSI C to VHDL http://www.adelantetechnologies.com/
Adelante Techn. A|RT Designer Mapping to architecture
Axys Design MaxCore developer Toolset for automatic generation of processor models and SW development tools http://www.axysdesign.com/
Suite Virtual prototyping for multi-processor SoC designs

- Embedded software development

- Architecture exploration and analysis
- Functional chip and system verification
- SystemC 2.0 is supported
- Designs are done in C/C++

MaxSim Designer
- Block diagram editor used to create multicore SoC models
- Uses designs from the MaxLib component library (processor cores, or other existing C models)
- Graphical Representation

MaxLib
- library of modules
- available ARM cores, TriCore, AMBA memory models, AMBA bus

MaxSimExplorer
- Simulate and Analyze SoC models
- Provides Access to the Registerinterface of the peripherals
- 10.000 times faster than RTL

- Existing ISS models can be integrated

- Cosimulation with VHDL/Verilog simulators is possible

MaxSimControl Center
- Control the simulation for embedded software

Generated models can be used as standalone simulation models or integrated into HW simulation or HW/SW co-simulation tools.
Axys Design MaxLib Library of models for popular SoC components
Axys Design MaxSim - Cycle based simulation
- Supports also SystemC 2.0
Berkeley Polis Framework for HW/SW codesign based http://www-cad.eecs.berkeley.edu/~polis/
on CFSM (Codesign Finite State machine) model
Main usage for description of control dominated systems

Uses the Ptolemy simulation engine

Concept of Polis is reused in VCC from Cadence
Berkeley Ptolemy High Level System Description, supports different application areas, http://ptolemy.eecs.berkeley.edu/
digital, timeless, mechanics ?/font>
Blue Pacific BlueWave HDL Simulator http://www.bluepc.com/
C Level Design Cycle C C/C++ coding style that support hardware functions http://www.cleveldesign.com
C Level Design System Compiler To compile from Cycle C to VHDL
Cadence SPW SDF modeling tool http://www.cadence.com/

- Can incorporate SystemC and Matlab models

- Fenite State Machine Editor
- Control access and modifications, as well as revision history and track changes option
- Graphical register transfer level (RTL) design capabilities with parameterized design capture that enable reuse
- Bit accurate architectural simulation
- Mixed fixed- and floating- point simulation
- Fixed-point library
- Verilog simulation and VHDL generation for synthesis tools

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Cadence VCC Virtual Component Composer: Architecture Mapping and evaluation

- function architecture mapping

- performance simulation
- communication refinement
- communication synthesis
- design export to implementation
- import possibility of SPW ,SDL, C, C++
Celoxica DK1 design suite DK1 is the design suite which provides the possibility for a direct flow from C to hardware. Main focus is on design, validation, iterative refinement of complex http://www.celoxica.com/
algorithm in hardware
Integrated Development environment with profiling possibility of the code

- Possible output of VHDL-Code

- Cosimulation with Instruction Set Simulator
Celoxica Handel-C Hardwaredescription extensions for ANSI-C based on OCCAM, usage of parallel and serial constructs
semaphores, communication over channels for different clockdomains possible.
Co-Design SYSTEMSIM SUPERLOG http://www.co-design.com/
Automation SYSTEMSIM, SYSTEMEX
SUPERLOG
CoWare CoWare N2C Design set of tools and methods for system-level design, HW/SW codesign http://www.coware.com/
System
- C/C++ based description
- Automatic generation of glue logic

Simulator

Hardware / Software Co-design

C / C++ Based Open System
Automatic Creation of Glue Logic Using Interface Synthesis
Analysis for Software and Hardware Partitioning
HDL and ISS Co-Simulation
Path to Embedded Software Development
Virtual Prototypes for Early Software Development
Hardware Refinement Path to Implementation (C to HDL)
Legacy Code Support
Platform-Based Methodology
Top-Down Design Methodology
Third-Party and IP Integration
Continuos System Verification Environment
Cosimualtion possible
provides SystemC and VSIA standard compliantt
Interface synthesis
DARPA RASSP Rapid prototyping of application specific signal processors http://www.eda.org/rassp/
Design methodology
Denali DataBahn Memory Memory models http://www.denali.com/
Subsystem Generator
Esterel Esterel Studio V3.1 Design tool suite with graphical editor, simulator, verifier, code generator and documentation generator http://www.esterel-technologies.com
System description is done with state diagrams so called SynChart. Suited for reactive systems not for data driven systems

- Importpossibility of UML descriptions

- Synchart is translated into the language Esterel and Esterel can be translated into C (VHDL is planned)
ESTEREL itself is an implementation of a synchronous language -> every function is waiting for valid inputs and will than be executed.

- Verifier searches for states which are not reached during testing
- Cosimulation with ESTEREL simulator and other simulators possible
- Optimizer for reducing area and length of the critical path
- Graphical notation used to represent hierarchical state diagrams
- Synchronous language and compiler
- Visual modelling toolset
- Provide formal executable specification downto embedded target code
- Code and test pattern can be automatically generated whenever specification changes
- Formal verification tool based on BDD internal representation of Esterel programs

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- Observer is able to find unwanted situations (states) of the system

if the system finds a bad situation a event path is given which leads into that state and a scenario which can
be replayed in the simulator
- The verification tools can be used to produce scenarios which lead into a given state or transition of the state diagram
- For Control the Esterel Code is simpler and more readable than the C description
- Test coverage is done by measuring the covered states of a state machine ( not code coverage)
- Out of Esterel C and VHDL can be generated
- Esterel is based on mathematical semantics so that it is possible to apply formal verification methods
Forte Design Cynlib Tool Suite Cynthesizer http://www.forteds.com/
System CynLib to VHDL-Verilog translator
Cynchronizer: VHDL-Verilog t to Cynlib translator performance improvement

Cynlib
C++ Hardware Extension like systemC. Tools provided:
Cyn++: macro in C to includes Verilog behaviors
Cynware: Generic C++ Classes of HW

Cyntax: Checker for the Syntax concerning also syntactical correctness but leading to wrong hardware
Checks also for race conditions

QuickBench
Multi layer verification systems. Propose:
QB-Modeler: Converting waves of protocol description into C testbench
QB-Sequencer: Design and generate streams of data by creating and assembling data sources.
QB-Manager: assemble your models, test sequences, and other resources into a testbench that is ready for simulation
IKOS Vstation Co-Modelling http://www.ikos.com/
Innoveda Visual Elite-Architect System level design mixing SystemC, C++, VHDL and verilog http://www.innoveda.com/default.asp
Integrated Environment to do System level design. Define transaction model model and a virtual prototype. Co-simulation C-VHDL simulator is possible. Visual Elite
is the general GUI. Earchitect is the virtual prototyping tool and allows to put empty blocks (VP0). VisualIP provides secured IP and Regent allows to do the memory
mapping in a graphical manner too. Virtual CPU incorporate cores models

- Single environment for system level design

- graphical and text based entry
- verification with mixed language description and (C/HDL) RTOS and SW
- Genaration of VP for Software development
- data mangement tools, documentation features
- Communication between blocks over communication channel (implementation of
protocol like queue, secure link, userdefined communication possible)
- Refinement is provided as far as the user can replace C description with VHDL descriptions

Regent
Programmable Register Editor
It creates the RTL code for the hardware design and the C header files for the software design
Innoveda Earchitect Architectural exploration, virtual prototyping tool
Innoveda Regent Design, documentation and verification of programmable register modules
Innoveda VisualIP IP Model protection and distribution system
LisaTek LISA Processor commands description language, toolset for generating HW and SW tools http://www.lisatek.com/
- Control part is available
- Pipelining functionality has to be written by hand
- compiler
- linker
- debugger
Mentor Graphics Modelsim VHDL/Verilog Simulator
Mentor Graphics Seamless CVE Hardware/Software co-verification
Mentor Graphics Platform Express To build SOCs by drag and drop. Can connect difference cores/components automatically over standard bus (AMBA, VSIAs VCI, ? http://www.mentor.com/
Milan Milan Multilevel Simulation environment http://milan.usc.edu/
Simulink Simulink Algorithm simulation tool http://www.mathworks.com/products/simulink/
Stanford Olympus Olympus Synthesis System is a vertically integrated design tool for specification and synthesis of digital circuits. The system has the following features: http://akebono.stanford.edu/users
/cad/synthesis/olympus.html
A hardware design language, HardwareC, for design specification.
High-level synthesis tools, Hercules and Here for performing behavioral and structural synthesis. Hercules takes HardwareC and passes results to Hebe, which

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performs the tasks of scheduling and binding, and outputs a logic-level description of the design.
A technology mapping tool, Ceres, which translates a logic-level descriptions into a technology dependent netlist.
Two simulators, Venus and Mercury for performing behavioral- and logic-level simulation.
Synopsys CoCentrics System Successor of Cossap with SystemC integration. New description models called Primmodelles with variable http://www.synopsys.com/
Studio datarates. Provides GUI with libraries and interface to versioncontrol
Synopsys Cossap Synchronous Data Flow description. C and extensions: Generic C
Synopsys Design Compiler Synthesis
Synopsys Behavioral Compiler Synthesis
Synopsys SCC Synopsys Toolsuite for the whole design process
Cocentric SystemC
compiler
Tanner EDA Tanner EDA was founded in 1988 to provide designers with easy-to-use and affordable integrated circuit design tools for PC platforms. Now producing innovative http://www.tanner.com/eda/
software solutions for Windows and Unix platforms, Tanner specializes in design entry, simulation, layout, routing and verification tools for custom IC design.
TestBuilder TestBuilder Extension of C++ with libraries providing an easy way to create test benches http://www.testbuilder.net
- C++ Class interface for HDL
- transaction based verification
Translogic EASE/EALE Graphical entry for VHDL http://www.translogiccorp.com/
Transmodelling System Modeler 2000
Inc.
TU Braunschweig Cosyma COSYMA (COSYnthesis for eMbedded micro Architectures) is a platform for exploration of the co-synthesis process http://www.ida.ing.tu-bs.de/projects/cosyma/
Partitioning in COSYMA starts with an all software solution and tries to extract hardware components iteratively until all timing constraints are met. The partitioning
goals are in order of decreasing importance :
Veritools SuperC SuperC™ is the Veritools adaptation of the SystemC simulator. Veritools has adapted the SystemC simulator to allow the simulator to write out the Veritools http://www.veritools-web.com/
very compressed data formats for the waveform and trace data files. The SuperC output files will be up to be 20-100 times smaller than those output by the current
SystemC simulators.
Virtio Virtual Prototyping to A Virtio Virtual Platform is more than just a model of the hardware. It includes all of the building blocks of the embedded system, i.e. processor and peripherals. http://www.virtio.com/
SystemC Each platform is ensured to integrate with software IP (RTOS, drivers and protocol stacks) and development tools (IDE, debuggers and compilers) delivering a
complete environment for the software development team
WHDL Language Rule Checker & Rule SystemC language checker http://www.whdl.com/
Generator
can check:
- SystemC compliance
- Connectivity
- Untimed functional or timed functional
- userdefined coding rule

report generation can be customized

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